OSDN Git Service
NAKAMURA Takumi [Mon, 16 Jul 2012 15:09:11 +0000 (15:09 +0000)]
Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCommonTableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160276
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Mon, 16 Jul 2012 15:08:47 +0000 (15:08 +0000)]
Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160275
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Samsonov [Mon, 16 Jul 2012 14:33:36 +0000 (14:33 +0000)]
Fix tests that failed on i686-win32 after r160248:
1. FileCheck-ize epilogue.ll and allow another asm instruction to restore %rsp.
2. Remove check in widen_arith-3.ll that was hitting instruction in epilogue instead of
vector add.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160274
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Mon, 16 Jul 2012 14:17:19 +0000 (14:17 +0000)]
test/CodeGen/R600: Add some basic tests v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160273
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Mon, 16 Jul 2012 14:17:16 +0000 (14:17 +0000)]
Build script changes for R600/SI Codegen v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160272
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Mon, 16 Jul 2012 14:17:14 +0000 (14:17 +0000)]
include/llvm: Add R600 Intrinsics v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160271
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Mon, 16 Jul 2012 14:17:08 +0000 (14:17 +0000)]
AMDGPU: Add core backend files for R600/SI codegen v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Mon, 16 Jul 2012 14:09:42 +0000 (14:09 +0000)]
[asan] initialize asan error callbacks in runOnModule instead of doing that on-demand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160269
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Mon, 16 Jul 2012 10:52:25 +0000 (10:52 +0000)]
Fix a bug in the 3-address conversion of LEA when one of the operands is an
undef virtual register. The problem is that ProcessImplicitDefs removes the
definition of the register and marks all uses as undef. If we lose the undef
marker then we get a register which has no def, is not marked as undef. The
live interval analysis does not collect information for these virtual
registers and we crash in later passes.
Together with Michael Kuperstein <michael.m.kuperstein@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160260
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Mon, 16 Jul 2012 10:01:02 +0000 (10:01 +0000)]
Revert r160254 temporarily.
It turns out that ASan relied on the at-the-end block insertion order to
(purely by happenstance) disable some LLVM optimizations, which in turn
start firing when the ordering is made more "normal". These
optimizations in turn merge many of the instrumentation reporting calls
which breaks the return address based error reporting in ASan.
We're looking at several different options for fixing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160256
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Mon, 16 Jul 2012 08:58:53 +0000 (08:58 +0000)]
Teach AddressSanitizer to create basic blocks in a more natural order.
This is particularly useful to the backend code generators which try to
process things in the incoming function order.
Also, cleanup some uses of IRBuilder to be a bit simpler and more clear.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160254
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Mon, 16 Jul 2012 08:56:46 +0000 (08:56 +0000)]
Add a basic test for AddressSanitizer. This is just a bare-bones
functionality test.
In general, unless the functionality is substantially separated, we
should lump more basic testing into this file. The test running
infrastructure likes having a few test files with more comprehensive
testing within them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160253
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Mon, 16 Jul 2012 07:45:06 +0000 (07:45 +0000)]
Add support for attaching branch weight metadata directly from the IRBuilder.
Added a basic unit test for this with CreateCondBr. I didn't go all the
way and test the switch side as the boilerplate for setting up the
switch IRBuilder unit tests is a lot more. Fortunately, the two share
all the interesting code paths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160251
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Mon, 16 Jul 2012 07:44:51 +0000 (07:44 +0000)]
Add a boring bit of boilerplate to start testing IRBuilder::CreateCondBr.
This is in anticipation of changing CreateCondBr and wanting to test
those changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160250
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Mon, 16 Jul 2012 07:44:45 +0000 (07:44 +0000)]
Move the IRBuilder unittest from Support to VMCore. This got missed in
the original move of IRBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160249
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Samsonov [Mon, 16 Jul 2012 06:54:09 +0000 (06:54 +0000)]
This CL changes the function prologue and epilogue emitted on X86 when stack needs realignment.
It is intended to fix PR11468.
Old prologue and epilogue looked like this:
push %rbp
mov %rsp, %rbp
and $alignment, %rsp
push %r14
push %r15
...
pop %r15
pop %r14
mov %rbp, %rsp
pop %rbp
The problem was to reference the locations of callee-saved registers in exception handling:
locations of callee-saved had to be re-calculated regarding the stack alignment operation. It would
take some effort to implement this in LLVM, as currently MachineLocation can only have the form
"Register + Offset". Funciton prologue and epilogue are now changed to:
push %rbp
mov %rsp, %rbp
push %14
push %15
and $alignment, %rsp
...
lea -$size_of_saved_registers(%rbp), %rsp
pop %r15
pop %r14
pop %rbp
Reviewed by Chad Rosier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160248
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Sun, 15 Jul 2012 23:45:24 +0000 (23:45 +0000)]
Move llvm/Support/TypeBuilder.h -> llvm/TypeBuilder.h. This completes
the move of *Builder classes into the Core library.
No uses of this builder in Clang or DragonEgg I could find.
If there is a desire to have an IR-building-support library that
contains all of these builders, that can be easily added, but currently
it seems likely that these add no real overhead to VMCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160243
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Sun, 15 Jul 2012 23:45:20 +0000 (23:45 +0000)]
Update the header guard I missed when moving the header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160242
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Sun, 15 Jul 2012 23:26:50 +0000 (23:26 +0000)]
Move llvm/Support/MDBuilder.h to llvm/MDBuilder.h, to live with
IRBuilder, DIBuilder, etc.
This is the proper layering as MDBuilder can't be used (or implemented)
without the Core Metadata representation.
Patches to Clang and Dragonegg coming up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160237
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Sun, 15 Jul 2012 20:39:08 +0000 (20:39 +0000)]
Fix a bug in the scalarization of BUILD_VECTOR. BUILD_VECTOR elements may be wider than the output element type. Make sure to trunc them if needed.
Together with Michael Kuperstein <michael.m.kuperstein@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160235
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Sun, 15 Jul 2012 20:27:43 +0000 (20:27 +0000)]
Teach getTargetVShiftNode about TargetConstant nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160234
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Sun, 15 Jul 2012 14:38:35 +0000 (14:38 +0000)]
llvm/test/CodeGen/X86/2012-07-15-broadcastfold.ll: Rewrite expressions to fit various targets.
- Make sure existence of "barrier".
- Confirm reload corresponding to spill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160232
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Sun, 15 Jul 2012 12:26:30 +0000 (12:26 +0000)]
Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention.
Allow the folding of vbroadcastRR to vbroadcastRM, where the memory operand is a spill slot.
PR12782.
Together with Michael Kuperstein <michael.m.kuperstein@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160230
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Sun, 15 Jul 2012 08:38:23 +0000 (08:38 +0000)]
Refactor the code that checks that all operands of a node are UNDEFs.
Add a micro-optimization to getNode of CONCAT_VECTORS when both operands are undefs.
Can't find a testcase for this because VECTOR_SHUFFLE already handles undef operands, but Duncan suggested that we add this.
Together with Michael Kuperstein <michael.m.kuperstein@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160229
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Sun, 15 Jul 2012 03:29:46 +0000 (03:29 +0000)]
Reapply r160194, switching to use LV information for finding local kills.
The notable fix is to look at any dependencies attached to the kill
instruction (or other instructions between MI nad the kill) where the
dependencies are specific to the register in question.
The old code implicitly handled this by rejecting the transform if *any*
other uses were found within the block, but after the start point. The
new code directly finds the kill, and has to re-use the existing
dependency scan to check for non-kill uses.
This was caught by self-host, but I found the bug via inspection and use
of absurd assert scaffolding to compute the kills in two ways and
compare them. So I have no useful testcase for this other than
"bootstrap". I'd work harder to reduce a test case if this particular
code were likely to live for a long time.
Thanks to Benjamin Kramer for reviewing the fix itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160228
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Sun, 15 Jul 2012 00:23:36 +0000 (00:23 +0000)]
Move IsSameValue from clang's ASTImporter to be methods on the
APInt/APSInt classes.
Part of rdar://
11875995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160223
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Sat, 14 Jul 2012 22:26:05 +0000 (22:26 +0000)]
AVX: Fix a bug in getTargetVShiftNode. The shift amount has to be a 128bit vector with the same element type as the input vector.
This is needed because of the patterns we have for the VP[SLL/SRA/SRL][W/D/Q] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160222
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Sat, 14 Jul 2012 21:30:27 +0000 (21:30 +0000)]
Add a dagcombine optimization to convert concat_vectors of undefs into a single undef.
The unoptimized concat_vectors isd prevented the canonicalization of the vector_shuffle node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160221
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Sat, 14 Jul 2012 18:45:35 +0000 (18:45 +0000)]
Account for early-clobber reload instructions.
No test case, there are no in-tree targets that require this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160219
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 13 Jul 2012 23:39:05 +0000 (23:39 +0000)]
Be more verbose when detecting dominance problems.
Catch uses of undefined physregs that haven't been added to basic block
live-in lists. Run the verifier to pinpoint the problem.
Also run the verifier when a virtual register use is not jointly
dominated by defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160207
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Fri, 13 Jul 2012 23:33:10 +0000 (23:33 +0000)]
LSR Fix: check SCEV expression safety before expansion.
All SCEV expressions used by LSR formulae must be safe to
expand. i.e. they may not contain UDiv unless we can prove nonzero
denominator.
Fixes PR11356: LSR hoists UDiv.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160205
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Fri, 13 Jul 2012 23:33:05 +0000 (23:33 +0000)]
IVUsers should only generate SCEV's for values that are safe to speculate.
This allows SCEVExpander to run on the IV expressions.
This codifies an assumption made by LSR to complete the fix for
PR11356, but I haven't been able to generate a separate unit test for
this part. I'm adding it as an extra safety check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160204
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Fri, 13 Jul 2012 23:33:03 +0000 (23:33 +0000)]
Factor SCEV traversal code so I can use it elsewhere. No functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160203
91177308-0d34-0410-b5e6-
96231b3b80d8
Joel Jones [Fri, 13 Jul 2012 23:25:25 +0000 (23:25 +0000)]
This is one of the first steps at moving to replace target-dependent
intrinsics with target-indepdent intrinsics. The first instruction(s) to be
handled are the vector versions of count leading zeros (ctlz).
The changes here are to clang so that it generates a target independent
vector ctlz when it sees an ARM dependent vector ctlz. The changes in llvm
are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp
to update any existing bc files containing ARM dependent vector ctlzs with
target-independent ctlzs. There are also changes to an existing test case in
llvm for ARM vector count instructions and a new test for the bitcode upgrade.
<rdar://problem/
11831778>
There is deliberately no test for the change to clang, as so far as I know, no
consensus has been reached regarding how to test neon instructions in clang;
q.v. <rdar://problem/
8762292>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160200
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 13 Jul 2012 22:23:32 +0000 (22:23 +0000)]
Revert r160194, which switched to use LV information for finding local
kills.
This is causing miscompiles that I'm working on tracking down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160196
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 13 Jul 2012 21:18:38 +0000 (21:18 +0000)]
Use the LiveVariables information to efficiently get local kills. This
removes the largest scaling problem in the test cases from PR13225 when
ASan is switched to insert basic blocks in the natural CFG order.
It may also solve some scaling problems for more normal code with large
numbers of basic blocks and variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160194
91177308-0d34-0410-b5e6-
96231b3b80d8
Galina Kistanova [Fri, 13 Jul 2012 21:06:54 +0000 (21:06 +0000)]
Fixed few warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160192
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 13 Jul 2012 20:44:29 +0000 (20:44 +0000)]
Remove variable_ops from call instructions in most targets.
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 13 Jul 2012 20:27:00 +0000 (20:27 +0000)]
Remove variable_ops from ARM call instructions.
Function argument registers are added to the call SDNode, but
InstrEmitter now knows how to make those operands implicit, and the call
instruction doesn't have to be variadic.
Explicit register operands should only be those that are encoded in the
instruction, implicit register operands are for extra dependencies like
call argument and return values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160188
91177308-0d34-0410-b5e6-
96231b3b80d8
Jack Carter [Fri, 13 Jul 2012 19:15:47 +0000 (19:15 +0000)]
The Mips specific relocation R_MIPS_GOT_DISP
is used in cases where global symbols are
directly represented in the GOT and we use an
offset into the global offset table.
This patch adds direct object support for R_MIPS_GOT_DISP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160183
91177308-0d34-0410-b5e6-
96231b3b80d8
Jack Carter [Fri, 13 Jul 2012 18:14:01 +0000 (18:14 +0000)]
test case for revision 160084: Alignment filling between Mips function units
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160177
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Fri, 13 Jul 2012 13:25:15 +0000 (13:25 +0000)]
Make helper functions static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160173
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexander Kornienko [Fri, 13 Jul 2012 12:55:23 +0000 (12:55 +0000)]
Initializers for some fields were missing in Option::Option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160170
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Fri, 13 Jul 2012 12:44:23 +0000 (12:44 +0000)]
ReleaseNotes.html: add note about specifying TLS models
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160168
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan Sands [Fri, 13 Jul 2012 10:11:28 +0000 (10:11 +0000)]
Post-dom frontier was removed in 3.0. Patch by chenwj.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160166
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan Sands [Fri, 13 Jul 2012 07:02:00 +0000 (07:02 +0000)]
Restrict this to x86, hopefully fixing ARM buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160163
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 13 Jul 2012 05:46:28 +0000 (05:46 +0000)]
Mark VINSERTI128rm as MayLoad=1. Fixes PR13348.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160162
91177308-0d34-0410-b5e6-
96231b3b80d8
Galina Kistanova [Fri, 13 Jul 2012 01:25:27 +0000 (01:25 +0000)]
Fixed few warnings; trimmed empty lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160159
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Fri, 13 Jul 2012 00:29:09 +0000 (00:29 +0000)]
Provide function name in 'Cannot select' fatal error.
When dumping the DAG for a fatal 'Cannot select' back-end error, also
provide the name of the function the construct is in. Useful when dealing
with large testcases, as the next step is to llvm-extract the function
in question to get a small(er) testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160152
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 12 Jul 2012 23:30:25 +0000 (23:30 +0000)]
The end of the prologue should be marked with is_stmt.
Fixes PR13303.
Patch by Paul Robinson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160148
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Thu, 12 Jul 2012 21:37:20 +0000 (21:37 +0000)]
TableGen: Assembly matcher 'insufficient operands' diagnostic.
Make sure the tblgen'erated asm matcher correctly returns numoperands+1
as the ErrorInfo when the problem was that there weren't enough operands
specified.
rdar://
9142751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160144
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Thu, 12 Jul 2012 21:19:32 +0000 (21:19 +0000)]
Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160143
91177308-0d34-0410-b5e6-
96231b3b80d8
Galina Kistanova [Thu, 12 Jul 2012 20:45:36 +0000 (20:45 +0000)]
Fixed few warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160142
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Thu, 12 Jul 2012 18:14:57 +0000 (18:14 +0000)]
Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and MachineLICM don't touch it.
I already had the necessary things in place for IR-level passes but missed the machine passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160137
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 12 Jul 2012 17:59:12 +0000 (17:59 +0000)]
Regenerate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160134
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Thu, 12 Jul 2012 13:45:15 +0000 (13:45 +0000)]
The LIT tests below do not specify the exact cpu model and fail on AVX2 machines, because we select different instructions such as vbroadcast, new shuffles, etc.
Patch by Michael Liao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160129
91177308-0d34-0410-b5e6-
96231b3b80d8
Gabor Greif [Thu, 12 Jul 2012 13:18:13 +0000 (13:18 +0000)]
detabify
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160128
91177308-0d34-0410-b5e6-
96231b3b80d8
Gabor Greif [Thu, 12 Jul 2012 13:05:12 +0000 (13:05 +0000)]
fix typo in generated comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160127
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Thu, 12 Jul 2012 10:22:57 +0000 (10:22 +0000)]
llvm/test/CodeGen/X86/rdrand.ll: Relax expression corresponding to Win64 CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160124
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Thu, 12 Jul 2012 10:15:48 +0000 (10:15 +0000)]
llvm/test/CMakeLists.txt: Add llvm-diff to deps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160123
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Thu, 12 Jul 2012 09:36:29 +0000 (09:36 +0000)]
Use %s instead of the explicit name, the latter doesn't work in out-of-tree builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160120
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Thu, 12 Jul 2012 09:31:43 +0000 (09:31 +0000)]
Add intrinsics for Ivy Bridge's rdrand instruction.
The rdrand/cmov sequence is the same that is emitted by both
GCC and ICC.
Fixes PR13284.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160117
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan Sands [Thu, 12 Jul 2012 09:01:35 +0000 (09:01 +0000)]
The result type of EXTRACT_VECTOR_ELT doesn't have to match the element type of
the input vector, it can be bigger (this is helpful for powerpc where <2 x i16>
is a legal vector type but i16 isn't a legal type, IIRC). However this wasn't
being taken into account by ExpandRes_EXTRACT_VECTOR_ELT, causing PR13220.
Lightly tweaked version of a patch by Michael Liao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160116
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2012 06:52:41 +0000 (06:52 +0000)]
Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110
91177308-0d34-0410-b5e6-
96231b3b80d8
Evan Cheng [Thu, 12 Jul 2012 01:45:35 +0000 (01:45 +0000)]
Instcombine was transforming:
%shr = lshr i64 %key, 3
%0 = load i64* %val, align 8
%sub = add i64 %0, -1
%and = and i64 %sub, %shr
ret i64 %and
to:
%shr = lshr i64 %key, 3
%0 = load i64* %val, align 8
%sub = add i64 %0,
2305843009213693951
%and = and i64 %sub, %shr
ret i64 %and
The demanded bit optimization is actually a pessimization because add -1 would
be codegen'ed as a sub 1. Teach the demanded constant shrinking optimization
to check for negated constant to make sure it is actually reducing the width
of the constant.
rdar://
11793464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160101
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Thu, 12 Jul 2012 00:53:31 +0000 (00:53 +0000)]
TableGen: Location information for diagnostic.
def Pat<...>;
Results in 'record name is not a string!' diagnostic. Not the best,
but the lack of location information moves it from not very helpful
into completely useless. We're in the Record class when throwing the
error, so just add the location info directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160098
91177308-0d34-0410-b5e6-
96231b3b80d8
Manman Ren [Wed, 11 Jul 2012 23:47:00 +0000 (23:47 +0000)]
ARM: fix typo in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160093
91177308-0d34-0410-b5e6-
96231b3b80d8
Manman Ren [Wed, 11 Jul 2012 22:51:44 +0000 (22:51 +0000)]
ARM: Fix optimizeCompare to correctly check safe condition.
It is safe if CPSR is killed or re-defined.
When we are done with the basic block, check whether CPSR is live-out.
Do not optimize away cmp if CPSR is live-out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160090
91177308-0d34-0410-b5e6-
96231b3b80d8
Jack Carter [Wed, 11 Jul 2012 22:17:39 +0000 (22:17 +0000)]
Patch for Mips direct object generation.
When WriteFragmentData() case FT_align called
Asm.getBackend().writeNopData() is called, nothing
is done since Mips implementation of writeNopData just
returned "true".
For some reason this has not caused problems in 32 bit
mode, but in 64 bit mode it caused an assert when processing
multiple function units.
The test case included will assert without this patch. It
runs twice with different flags to prevent false positives
due to changes in code generation over time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160084
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Wed, 11 Jul 2012 21:49:14 +0000 (21:49 +0000)]
Fixup broken doc link. Patch by Sean Silva <silvas@purdue.edu>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160082
91177308-0d34-0410-b5e6-
96231b3b80d8
Jack Carter [Wed, 11 Jul 2012 21:41:49 +0000 (21:41 +0000)]
This change removes an "initialization" warning.
Even though variable in question could not
be initialized before use, the code was such that
the compiler had no way of knowing that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160081
91177308-0d34-0410-b5e6-
96231b3b80d8
Stepan Dyatkovskiy [Wed, 11 Jul 2012 21:02:57 +0000 (21:02 +0000)]
Fixed diff comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160076
91177308-0d34-0410-b5e6-
96231b3b80d8
Argyrios Kyrtzidis [Wed, 11 Jul 2012 20:59:20 +0000 (20:59 +0000)]
In MemoryBuffer::getOpenFile() don't verify that the mmap'ed
file buffer is null-terminated.
If the file is smaller than we thought, mmap will not allow dereferencing
past the pages that are enough to cover the actual file size,
even though we asked for a larger address range.
rdar://
11612916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160075
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Wed, 11 Jul 2012 20:51:50 +0000 (20:51 +0000)]
In register classes in MipsRegisterInfo.td, list the registers in ascending
order of binary encoding.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160073
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Wed, 11 Jul 2012 19:58:38 +0000 (19:58 +0000)]
[x86 fast-isel] Per discussion with Eric, add all cases to switch with verbose
comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160069
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Wed, 11 Jul 2012 19:50:46 +0000 (19:50 +0000)]
Test case for r160036.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160067
91177308-0d34-0410-b5e6-
96231b3b80d8
Manman Ren [Wed, 11 Jul 2012 19:35:12 +0000 (19:35 +0000)]
X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.
When Movr0 is between sub and cmp, we move Movr0 before sub if it enables
removal of Cmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160066
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Wed, 11 Jul 2012 19:32:27 +0000 (19:32 +0000)]
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160064
91177308-0d34-0410-b5e6-
96231b3b80d8
Evan Cheng [Wed, 11 Jul 2012 18:55:07 +0000 (18:55 +0000)]
InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:
r1025 = s/zext r1024, 4
r1026 = extract_subreg r1025, 4
to a copy:
r1026 = copy r1024
This is correct. However it uses TII->isCoalescableExtInstr() which can return
true for instructions which essentially does a sext_in_reg so this can end up
with an illegal copy where the source and destination register classes do not
match. Add a check to avoid it. Sorry, no test case possible at this time.
rdar://
11849816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160059
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Wed, 11 Jul 2012 18:31:59 +0000 (18:31 +0000)]
PR13326: Fix a subtle edge case in the udiv -> magic multiply generator.
This caused 6 of 65k possible 8 bit udivs to be wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160058
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Wed, 11 Jul 2012 17:34:12 +0000 (17:34 +0000)]
test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160056
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Wed, 11 Jul 2012 17:23:17 +0000 (17:23 +0000)]
[x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall back
to Selection DAG isel. Patch by Andrew Kaylor <andrew.kaylor@intel.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160055
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Wed, 11 Jul 2012 13:27:05 +0000 (13:27 +0000)]
When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, allow loads/stores of 64bit values from xmm registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160044
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Wed, 11 Jul 2012 11:02:16 +0000 (11:02 +0000)]
Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, Ptr, etc.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160042
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Wed, 11 Jul 2012 09:39:04 +0000 (09:39 +0000)]
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160040
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Wed, 11 Jul 2012 08:52:09 +0000 (08:52 +0000)]
Refactor the DAG Legalizer by extracting the legalization of
Load and Store nodes into their own functions.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160037
91177308-0d34-0410-b5e6-
96231b3b80d8
Owen Anderson [Wed, 11 Jul 2012 06:38:55 +0000 (06:38 +0000)]
Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns an MVT::i1, i.e. before type legalization.
This is a speculative fix for a problem on Mips reported by Akira Hatanaka.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160036
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Wed, 11 Jul 2012 00:53:32 +0000 (00:53 +0000)]
Lower RETURNADDR node in Mips backend.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160031
91177308-0d34-0410-b5e6-
96231b3b80d8
Jack Carter [Tue, 10 Jul 2012 22:41:20 +0000 (22:41 +0000)]
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 10 Jul 2012 22:39:56 +0000 (22:39 +0000)]
Require and preserve LoopInfo for early if-conversion.
It will surely be needed by heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160027
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 10 Jul 2012 22:25:21 +0000 (22:25 +0000)]
Teach the LiveInterval::join function to use the fast merge algorithm,
generalizing its implementation sufficiently to support this value
number scenario as well.
This cuts out another significant performance hit in large functions
(over 10k basic blocks, etc), especially those with "natural" CFG
structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160026
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 10 Jul 2012 22:18:23 +0000 (22:18 +0000)]
Run early if-conversion in domtree post-order.
This ordering allows nested if-conversion without using a work list, and
it makes it possible to update the dominator tree on the fly as well.
Any erased basic blocks will always be dominated by the current
post-order position, so the domtree can be pruned without invalidating
the iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160025
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 10 Jul 2012 18:27:15 +0000 (18:27 +0000)]
Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo to
X86MachineFunctionInfo as this is currently only used by X86. If this ever
becomes an issue on another arch (e.g., ARM) then we can hoist it back out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160009
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 10 Jul 2012 17:57:00 +0000 (17:57 +0000)]
Add newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160006
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 10 Jul 2012 17:49:39 +0000 (17:49 +0000)]
Add test case accidentally omitted from r160002.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160004
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 10 Jul 2012 17:45:53 +0000 (17:45 +0000)]
Add support for dynamic stack realignment in the presence of dynamic allocas on
X86. Basically, this is a reapplication of r158087 with a few fixes.
Specifically, (1) the stack pointer is restored from the base pointer before
popping callee-saved registers and (2) in obscure cases (see comments in patch)
we must cache the value of the original stack adjustment in the prologue and
apply it in the epilogue.
rdar://
11496434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 10 Jul 2012 15:41:33 +0000 (15:41 +0000)]
Fix a bug where I didn't test for an empty range before inspecting the
back of it.
I don't have anything even remotely close to a test case for this. It
only broke two build bots, both of them doing bootstrap builds, one of
them a dragonegg bootstrap. It doesn't break for me when I bootstrap
either. It doesn't reproduce every time or on many machines during the
bootstrap. Many thanks to Duncan Sands who got the exact command (and
stage of the bootstrap) which failed on the dragonegg bootstrap and
managed to get it to trigger under valgrind with debug symbols. The fix
was then found by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159993
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Tue, 10 Jul 2012 13:25:08 +0000 (13:25 +0000)]
Improve the loading of load-anyext vectors by allowing the codegen to load
multiple scalars and insert them into a vector. Next, we shuffle the elements
into the correct places, as before.
Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the
migration of bitcasts happened too late in the SelectionDAG process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Barton [Tue, 10 Jul 2012 12:51:09 +0000 (12:51 +0000)]
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 10 Jul 2012 06:38:33 +0000 (06:38 +0000)]
Reverse assembler/disassembler operand order for gather instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983
91177308-0d34-0410-b5e6-
96231b3b80d8