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Ying Yi [Tue, 30 Aug 2016 07:01:37 +0000 (07:01 +0000)]
[llvm-cov] Use the native path in the coverage report.
The coverage reports contain the source or binary file paths. On Windows,
the file path might contain the seperators of both '/' and '\'. This patch
uses the native path in the coverage reports. For example, on Windows,
all '/' are converted to '\'.
Differential Revision: https://reviews.llvm.org/D23922
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280061
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Lang Hames [Tue, 30 Aug 2016 06:00:21 +0000 (06:00 +0000)]
[Support][Error] Suppress warning about unused result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280059
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Lang Hames [Tue, 30 Aug 2016 05:32:41 +0000 (05:32 +0000)]
[Support] Add a conditionally defined default constructor (available on MSVC
only) for Expected<T> so that it can interoperate with MSVC's std::future
implementation.
MSVC 2013's std::future implementation requires the wrapped type to be default
constructible.
Hopefully this will fix the bot breakage in
http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/9937 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280058
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James Y Knight [Tue, 30 Aug 2016 03:16:16 +0000 (03:16 +0000)]
Replace incorrect "#ifdef DEBUG" with "#ifndef NDEBUG".
The former is simply wrong -- the code will either never be used or will
always be used, rather than being dependent upon whether it's built with
debug assertions enabled.
The macro DEBUG isn't ever set by the llvm build system. But, the macro
DEBUG(X) is defined (unconditionally) if you happen to include
llvm/Support/Debug.h.
The code in Value.h which was erroneously protected by the #ifdef DEBUG
didn't even compile -- you can't cast<> from an LLVMOpaqueValue
directly. Fortunately, it was never invoked, as Core.cpp included
Value.h before Debug.h.
The conditionalized code in AArch64CollectLOH.cpp was previously always
used, as it includes Debug.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280056
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Kostya Serebryany [Tue, 30 Aug 2016 03:05:50 +0000 (03:05 +0000)]
[libFuzzer] use bits instead of bytes for memcmp/strcmp value profile -- the fuzzer reaches the goal much faster, at least on the simple puzzles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280054
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Anna Thomas [Tue, 30 Aug 2016 02:36:48 +0000 (02:36 +0000)]
[RewriteStatepointsForGC] Update comment for same PHI node check. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280052
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Lang Hames [Tue, 30 Aug 2016 01:57:06 +0000 (01:57 +0000)]
[ORC][RPC] Reword 'async' to 'non-blocking' to better reflect call primitive
behaviors, and add a callB (blacking call) primitive.
callB is a blocking call primitive for threaded code where the RPC responses are
being processed on a separate thread. (For single threaded code callST should
continue to be used instead).
No unit test yet: Last time I commited a threaded unit test it deadlocked on
one of the s390x builders. I'll try to re-enable that test first, and add a new
test if I can sort out the deadlock issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280051
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Hal Finkel [Tue, 30 Aug 2016 01:43:38 +0000 (01:43 +0000)]
[PowerPC] Force entry alignment in .got2
Implement Bill's suggested fix for 32-bit targets for PR22711 (for the
alignment of each entry). As pointed out in the bug report, we could just force
the section alignment, since we only add pointer-sized things currently, but
this fix is somewhat more future-proof.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280049
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Sanjoy Das [Tue, 30 Aug 2016 01:38:59 +0000 (01:38 +0000)]
Fix coding style; NFC
Avoid variables starting with lowercase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280048
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Duncan P. N. Exon Smith [Tue, 30 Aug 2016 01:37:58 +0000 (01:37 +0000)]
ADT: Explode include/llvm/ADT/{ilist,ilist_node}.h, NFC
I'm working on a lower-level intrusive list that can be used
stand-alone, and splitting the files up a bit will make the code easier
to organize. Explode the ilist headers in advance to improve blame
lists in the future.
- Move ilist_node_base from ilist_node.h to ilist_node_base.h.
- Move ilist_base from ilist.h to ilist_base.h.
- Move ilist_iterator from ilist.h to ilist_iterator.h.
- Move ilist_node_access from ilist.h to ilist_node.h to support
ilist_iterator.
- Update unit tests to #include smaller headers.
- Clang-format the moved things.
I noticed in transit that there is a simplify_type specialization for
ilist_iterator. Since there is no longer an implicit conversion from
ilist<T>::iterator to T*, this doesn't make sense (effectively it's a
form of implicit conversion). For now I've added a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280047
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Kostya Serebryany [Tue, 30 Aug 2016 01:30:14 +0000 (01:30 +0000)]
[libFuzzer] use trace-div and trace-gep for guided fuzzing, add tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280046
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Kostya Serebryany [Tue, 30 Aug 2016 01:12:10 +0000 (01:12 +0000)]
[sanitizer-coverage] add two more modes of instrumentation: trace-div and trace-gep, mostly usaful for value-profile-based fuzzing; llvm part
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280043
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Hal Finkel [Tue, 30 Aug 2016 00:59:23 +0000 (00:59 +0000)]
[PowerPC] Add support for -mlongcall
The "long call" option forces the use of the indirect calling sequence for all
calls (even those that don't really need it). GCC provides this option; This is
helpful, under certain circumstances, for building very-large binaries, and
some other specialized use cases.
Fixes PR19098.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280040
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Piotr Padlewski [Tue, 30 Aug 2016 00:46:26 +0000 (00:46 +0000)]
NFC: add early exit in ModuleSummaryAnalysis
Summary:
Changed this code because it was not very readable.
The one question that I got after changing it is, should we
count calls to intrinsics? We don't add them to caller summary,
so maybe we shouldn't also count them?
Reviewers: tejohnson, eraman, mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23949
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280036
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Hal Finkel [Tue, 30 Aug 2016 00:22:22 +0000 (00:22 +0000)]
[PowerPC] Add triple to test/CodeGen/PowerPC/atomic-2.ll for ppc64le
Otherwise, running the test on Darwin systems will not work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280034
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Duncan P. N. Exon Smith [Tue, 30 Aug 2016 00:18:43 +0000 (00:18 +0000)]
Rename unittests/ADT/ilistTestTemp.cpp => IListTest.cpp
And rename the tests inside from ilistTest to IListTest. This makes the
file sort properly in the CMakeLists.txt (previously, sorting would
throw it down to the end of the list) and is consistent with the tests
I've added more recently.
Why use IListNodeBaseTest.cpp (and a test name of IListNodeBaseTest)?
- ilist_node_base_test is the obvious thing, since this is testing
ilist_node_base. However, gtest disallows underscores in test names.
- ilist_node_baseTest fails for the same reason.
- ilistNodeBaseTest is weird, because it isn't in our usual
TitleCaseTest form that we use for tests, and it also doesn't have the
name of the tested class in it.
- IlistNodeBaseTest matches TitleCaseTest, but "Ilist" is hard to read,
and really "ilist" is an abbreviation for "IntrusiveList" so the
lowercase "list" is strange.
- That left IListNodeBaseTest.
Note: I made this move in two stages, with a temporary filename of
ilistTestTemp in between in r279524. This was in the hopes of avoiding
problems on Git and SVN clients on case-insensitive filesystems,
particularly on buildbots with incremental checkouts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280033
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Duncan P. N. Exon Smith [Tue, 30 Aug 2016 00:13:12 +0000 (00:13 +0000)]
ADT: Give ilist<T>::reverse_iterator a handle to the current node
Reverse iterators to doubly-linked lists can be simpler (and cheaper)
than std::reverse_iterator. Make it so.
In particular, change ilist<T>::reverse_iterator so that it is *never*
invalidated unless the node it references is deleted. This matches the
guarantees of ilist<T>::iterator.
(Note: MachineBasicBlock::iterator is *not* an ilist iterator, but a
MachineInstrBundleIterator<MachineInstr>. This commit does not change
MachineBasicBlock::reverse_iterator, but it does update
MachineBasicBlock::reverse_instr_iterator. See note at end of commit
message for details on bundle iterators.)
Given the list (with the Sentinel showing twice for simplicity):
[Sentinel] <-> A <-> B <-> [Sentinel]
the following is now true:
1. begin() represents A.
2. begin() holds the pointer for A.
3. end() represents [Sentinel].
4. end() holds the poitner for [Sentinel].
5. rbegin() represents B.
6. rbegin() holds the pointer for B.
7. rend() represents [Sentinel].
8. rend() holds the pointer for [Sentinel].
The changes are #6 and #8. Here are some properties from the old
scheme (which used std::reverse_iterator):
- rbegin() held the pointer for [Sentinel] and rend() held the pointer
for A;
- operator*() cost two dereferences instead of one;
- converting from a valid iterator to its valid reverse_iterator
involved a confusing increment; and
- "RI++->erase()" left RI invalid. The unintuitive replacement was
"RI->erase(), RE = end()".
With vector-like data structures these properties are hard to avoid
(since past-the-beginning is not a valid pointer), and don't impose a
real cost (since there's still only one dereference, and all iterators
are invalidated on erase). But with lists, this was a poor design.
Specifically, the following code (which obviously works with normal
iterators) now works with ilist::reverse_iterator as well:
for (auto RI = L.rbegin(), RE = L.rend(); RI != RE;)
fooThatMightRemoveArgFromList(*RI++);
Converting between iterator and reverse_iterator for the same node uses
the getReverse() function.
reverse_iterator iterator::getReverse();
iterator reverse_iterator::getReverse();
Why doesn't iterator <=> reverse_iterator conversion use constructors?
In order to catch and update old code, reverse_iterator does not even
have an explicit conversion from iterator. It wouldn't be safe because
there would be no reasonable way to catch all the bugs from the changed
semantic (see the changes at call sites that are part of this patch).
Old code used this API:
std::reverse_iterator::reverse_iterator(iterator);
iterator std::reverse_iterator::base();
Here's how to update from old code to new (that incorporates the
semantic change), assuming I is an ilist<>::iterator and RI is an
ilist<>::reverse_iterator:
[Old] ==> [New]
reverse_iterator(I) (--I).getReverse()
reverse_iterator(I) ++I.getReverse()
--reverse_iterator(I) I.getReverse()
reverse_iterator(++I) I.getReverse()
RI.base() (--RI).getReverse()
RI.base() ++RI.getReverse()
--RI.base() RI.getReverse()
(++RI).base() RI.getReverse()
delete &*RI, RE = end() delete &*RI++
RI->erase(), RE = end() RI++->erase()
=======================================
Note: bundle iterators are out of scope
=======================================
MachineBasicBlock::iterator, also known as
MachineInstrBundleIterator<MachineInstr>, is a wrapper to represent
MachineInstr bundles. The idea is that each operator++ takes you to the
beginning of the next bundle. Implementing a sane reverse iterator for
this is harder than ilist. Here are the options:
- Use std::reverse_iterator<MBB::i>. Store a handle to the beginning of
the next bundle. A call to operator*() runs a loop (usually
operator--() will be called 1 time, for unbundled instructions).
Increment/decrement just works. This is the status quo.
- Store a handle to the final node in the bundle. A call to operator*()
still runs a loop, but it iterates one time fewer (usually
operator--() will be called 0 times, for unbundled instructions).
Increment/decrement just works.
- Make the ilist_sentinel<MachineInstr> *always* store that it's the
sentinel (instead of just in asserts mode). Then the bundle iterator
can sniff the sentinel bit in operator++().
I initially tried implementing the end() option as part of this commit,
but updating iterator/reverse_iterator conversion call sites was
error-prone. I have a WIP series of patches that implements the final
option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280032
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Jan Vesely [Mon, 29 Aug 2016 23:21:46 +0000 (23:21 +0000)]
AMDGPU/R600: Cleanup DAGCombine
Move SDLoc initialization to comon place.
fall back to AMDGPU version in one place
Differential Revision: https://reviews.llvm.org/D23900
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280030
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Lang Hames [Mon, 29 Aug 2016 23:10:20 +0000 (23:10 +0000)]
[ORC] Fix unit-test breakage from r280016.
Void functions returning error now boolean convert to 'false' if they succeed.
Unit tests updated to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280027
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Michael Kuperstein [Mon, 29 Aug 2016 22:49:05 +0000 (22:49 +0000)]
Fix typo in comment. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280025
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Teresa Johnson [Mon, 29 Aug 2016 22:46:56 +0000 (22:46 +0000)]
[ThinLTO] Indirect call promotion fixes for promoted local functions
Summary:
Fix a couple issues limiting the application of indirect call promotion
in ThinLTO mode:
- Invoke indirect call promotion before globalopt, since it may
eliminate imported functions which appear unreferenced.
- Invoke indirect call promotion with InLTO=true so that the PGOFuncName
metadata is used to get the name for locals which would have been
renamed during promotion.
Reviewers: davidxl, mehdi_amini
Subscribers: Prazek, llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D24004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280024
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Hal Finkel [Mon, 29 Aug 2016 22:25:36 +0000 (22:25 +0000)]
[PowerPC] Fix i8/i16 atomics for little-Endian targets without partword atomics
For little-Endian PowerPC, we generally target only P8 and later by default.
However, generic (older) 64-bit configurations are still an option, and in that
case, partword atomics are not available (e.g. stbcx.). To lower i8/i16 atomics
without true i8/i16 atomic operations, we emulate using i32 atomics in
combination with a bunch of shifting and masking, etc. The amount by which to
shift in little-Endian mode is different from the amount in big-Endian mode (it
is inverted -- meaning we can leave off the xor when computing the amount).
Fixes PR22923.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280022
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Chad Rosier [Mon, 29 Aug 2016 22:09:51 +0000 (22:09 +0000)]
[SLP] Return a boolean value for these static helpers. NFC.
Differential Revision: https://reviews.llvm.org/D24008
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280020
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Jan Vesely [Mon, 29 Aug 2016 22:05:06 +0000 (22:05 +0000)]
AMDGPU/R600: Remove MergeVectorStores from legalization
This is handled by DAGCombiner in a more generic way
Differential Revision: https://reviews.llvm.org/D23970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280019
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Lang Hames [Mon, 29 Aug 2016 21:57:52 +0000 (21:57 +0000)]
[ORC][RPC] Fix typo in RPC comments: call primitives on void functions return
future<Error>, not future<bool>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280017
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Lang Hames [Mon, 29 Aug 2016 21:56:30 +0000 (21:56 +0000)]
[ORC][RPC] Make the future type of an Orc RPC call Error/Expected rather than
Optional.
For void functions the return type of a nonblocking call changes from
Expected<future<Optional<bool>>> to Expected<future<Error>>, and for functions
returning T the return type changes from Expected<future<Optional<T>>> to
Expected<future<Expected<T>>>.
Inner results need to be checked (since the RPC connection may have dropped
out before a result came back) and Error/Expected provide stronger checking
requirements. It also allows us drop the crufty 'optionalToError' function and
just collapse Errors in the single-threaded call primitives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280016
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Chris Bieneman [Mon, 29 Aug 2016 21:26:32 +0000 (21:26 +0000)]
[CMake] Make LLVMConfig.cmake variable names match in-tree names
With the runtimes build we're trying to use LLVMConfig.cmake as a way of providing LLVM_* variables that are needed to behave as if the project is building in tree. To make this work we need to rename two variables by dropping the "S" from the end. This makes the variables match the in-tree names.
This renames:
LLVM_INCLUDE_DIRS -> LLVM_INCLUDE_DIR
LLVM_LIBRARY_DIRS -> LLVM_LIBRARY_DIR
The versions ending in S are not used in-tree anywhere. This also cleans up LLVM_LIBRARY_DIR being set to the same value with and without the "S".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280013
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Tim Northover [Mon, 29 Aug 2016 21:00:00 +0000 (21:00 +0000)]
GlobalISel: use multi-dimensional arrays for legalize actions.
Instead of putting all possible requests into a single table, we can perform
the extremely dense lookup based on opcode and type-index in constant time
using multi-dimensional array-like things.
This roughly halves the time spent doing legalization, which was dominated by
queries against the Actions table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280011
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Easwaran Raman [Mon, 29 Aug 2016 20:45:51 +0000 (20:45 +0000)]
Fix a thinko in r278189.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280008
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Saleem Abdulrasool [Mon, 29 Aug 2016 20:42:07 +0000 (20:42 +0000)]
AMDGPU: fix mismatch tags, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280006
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Saleem Abdulrasool [Mon, 29 Aug 2016 20:42:03 +0000 (20:42 +0000)]
ExecutionEngine: fix a bug in the movt/movw relocator
According to the arm arm specifications, 4 bytes are needed for a shift instead
of 8, this was causing the movt instruction to write to a different register
sometimes.
Patch by Walter Erquinigo!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280005
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Chris Bieneman [Mon, 29 Aug 2016 20:18:52 +0000 (20:18 +0000)]
[CMake] Builtins build needs LLVM_*_OUTPUT_INTDIR variables
This allows the builtins archives to build into the correct subdirectory under the binary dir. Addresses the issue discussed in D24001.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280002
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Matthew Simpson [Mon, 29 Aug 2016 20:14:04 +0000 (20:14 +0000)]
[LV] Move insertelement sequence after scalar definitions
After r279649 when getting a vector value from VectorLoopValueMap, we create an
insertelement sequence on-demand if the value has been scalarized instead of
vectorized. We previously inserted this insertelement sequence before the
value's first vector user. However, this insert location is problematic if that
user is the phi node of a first-order recurrence. With this patch, we move the
insertelement sequence after the last scalar instruction we created when
scalarizing the value. Thus, the value's vector definition in the new loop will
immediately follow its scalar definitions. This should fix PR30183.
Reference: https://llvm.org/bugs/show_bug.cgi?id=30183
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280001
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Krzysztof Parzyszek [Mon, 29 Aug 2016 19:50:15 +0000 (19:50 +0000)]
Propagate TBAA info in SelectionDAG::getIndexedLoad
Patch by Pranav Bhandarkar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279998
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Douglas Katzman [Mon, 29 Aug 2016 19:42:57 +0000 (19:42 +0000)]
[Myriad]: add missing 'mcpu' values
Should have been done with r276646.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279996
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Tom Stellard [Mon, 29 Aug 2016 19:42:52 +0000 (19:42 +0000)]
AMDGPU/SI: Implement a custom MachineSchedStrategy
Summary:
GCNSchedStrategy re-uses most of GenericScheduler, it's just uses
a different method to compute the excess and critical register
pressure limits.
It's not enabled by default, to enable it you need to pass -misched=gcn
to llc.
Shader DB stats:
32464 shaders in 17874 tests
Totals:
SGPRS:
1542846 ->
1643125 (6.50 %)
VGPRS:
1005595 -> 904653 (-10.04 %)
Spilled SGPRs: 29929 -> 27745 (-7.30 %)
Spilled VGPRs: 334 -> 352 (5.39 %)
Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread
Code Size:
36688188 ->
37034900 (0.95 %) bytes
LDS: 1913 -> 1913 (0.00 %) blocks
Max Waves: 254101 -> 265125 (4.34 %)
Wait states: 0 -> 0 (0.00 %)
Totals from affected shaders:
SGPRS:
1338220 ->
1438499 (7.49 %)
VGPRS: 886221 -> 785279 (-11.39 %)
Spilled SGPRs: 29869 -> 27685 (-7.31 %)
Spilled VGPRs: 334 -> 352 (5.39 %)
Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread
Code Size:
34315716 ->
34662428 (1.01 %) bytes
LDS: 1551 -> 1551 (0.00 %) blocks
Max Waves: 188127 -> 199151 (5.86 %)
Wait states: 0 -> 0 (0.00 %)
Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrick
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: https://reviews.llvm.org/D23688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279995
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Vitaly Buka [Mon, 29 Aug 2016 19:28:34 +0000 (19:28 +0000)]
[asan] Enable new stack poisoning with store instruction by default
Reviewers: eugenis
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279993
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Tim Northover [Mon, 29 Aug 2016 19:27:20 +0000 (19:27 +0000)]
GlobalISel: switch to SmallVector for pending legalizations.
std::queue was doing far to many heap allocations to be healthy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279992
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Tom Stellard [Mon, 29 Aug 2016 19:15:22 +0000 (19:15 +0000)]
AMDGPU/SI: Improve SILoadStoreOptimizer and run it before the scheduler
Summary:
The SILoadStoreOptimizer can now look ahead more then one instruction when
looking for instructions to merge, which greatly improves the number of
loads/stores that we are able to merge.
Moving the pass before scheduling avoids increasing register pressure after
the scheduler, so that the scheduler's register pressure estimates will be
more accurate. It also gives more consistent results, since it is no longer
affected by minor scheduling changes.
Reviewers: arsenm
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: https://reviews.llvm.org/D23814
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279991
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Tim Northover [Mon, 29 Aug 2016 19:12:20 +0000 (19:12 +0000)]
ASan: remove variable only used in assertions build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279990
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Tim Northover [Mon, 29 Aug 2016 19:07:16 +0000 (19:07 +0000)]
GlobalISel: legalize frem to a libcall on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279988
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Tim Northover [Mon, 29 Aug 2016 19:07:08 +0000 (19:07 +0000)]
GlobalISel: rework CallLowering so that it can be used for libcalls too.
There should be no functional change here, I'm just making the implementation
of "frem" (to libcall) legalization easier for a followup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279987
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Matt Arsenault [Mon, 29 Aug 2016 19:01:48 +0000 (19:01 +0000)]
AMDGPU/R600: Fix fixups used for constant arrays
Fixes bug 29289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279986
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Kyle Butt [Mon, 29 Aug 2016 18:27:12 +0000 (18:27 +0000)]
IfConversion: Fix branch predication bug.
This bug shows up with diamonds that share unpredicable, unanalyzable branches.
There's an included test case from Hexagon. What was happening was that we were
attempting to predicate the branch instruction despite the fact that it was
checked to be the same. Now for unanalyzable branches we skip over the branch
instructions when predicating the block.
Differential Revision: https://reviews.llvm.org/D23939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279985
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Vitaly Buka [Mon, 29 Aug 2016 18:17:21 +0000 (18:17 +0000)]
Use store operation to poison allocas for lifetime analysis.
Summary:
Calling __asan_poison_stack_memory and __asan_unpoison_stack_memory for small
variables is too expensive.
Code is disabled by default and can be enabled by -asan-experimental-poisoning.
PR27453
Reviewers: eugenis
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279984
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Vitaly Buka [Mon, 29 Aug 2016 17:41:29 +0000 (17:41 +0000)]
[asan] Separate calculation of ShadowBytes from calculating ASanStackFrameLayout
Summary: No functional changes, just refactoring to make D23947 simpler.
Reviewers: eugenis
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279982
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David Majnemer [Mon, 29 Aug 2016 17:14:08 +0000 (17:14 +0000)]
[SimplifyCFG] Hoisting invalidates metadata
We forgot to remove optimization metadata when performing hosting during
FoldTwoEntryPHINode.
This fixes PR29163.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279980
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Reid Kleckner [Mon, 29 Aug 2016 16:35:43 +0000 (16:35 +0000)]
Make vec_fabs.ll pass with MSVC 2013
We should revert this change once we drop support for MSVC 2013.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279979
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Teresa Johnson [Mon, 29 Aug 2016 16:22:23 +0000 (16:22 +0000)]
[gold] Fix test accidentally regressed for newer gold
With r279911 I accidentally regressed the gold/X86/start-lib-common.ll
test for newer golds (v1.12+) that honor the --start-lib/--end-lib.
Remove the alignment which should not be there to make this work with
both old and new gold linkers.
Additionally, now that we have a subdirectory for v1.12+ gold tests,
copy this test there and check specifically for the v1.12+ behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279977
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Evandro Menezes [Mon, 29 Aug 2016 16:04:37 +0000 (16:04 +0000)]
[AArch64] Adjust the scheduling model for Exynos M1.
Further refine the model for loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279976
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Anna Thomas [Mon, 29 Aug 2016 15:41:59 +0000 (15:41 +0000)]
[StatepointsForGC] Rematerialize in the presence of PHIs
Summary:
While walking the use chain for identifying rematerializable values in RS4GC,
add the case where the current value and base value are the same PHI nodes.
This will aid rematerialization of geps and casts instead of relocating.
Reviewers: sanjoy, reames, igor
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279975
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Teresa Johnson [Mon, 29 Aug 2016 15:33:01 +0000 (15:33 +0000)]
[LTO] Remove extraneous output
Remove some debugging output to stderr that snuck in with r279576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279974
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Sanjay Patel [Mon, 29 Aug 2016 15:27:17 +0000 (15:27 +0000)]
[Constant] remove fdiv and frem from canTrap()
Assuming the default FP env, we should not treat fdiv and frem any differently in terms of
trapping behavior than any other FP op. Ie, FP ops do not trap with the default FP env.
This matches how we treat the fdiv/frem in IR with isSafeToSpeculativelyExecute() and in
the backend after:
https://reviews.llvm.org/rL279970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279973
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Sanjay Patel [Mon, 29 Aug 2016 14:57:53 +0000 (14:57 +0000)]
[SimplifyCFG] rename test file, regenerate checks, and add test
The fdiv test shows a problem similar to:
https://reviews.llvm.org/rL279970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279972
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Gor Nishanov [Mon, 29 Aug 2016 14:34:12 +0000 (14:34 +0000)]
[Coroutines] Part 9: Add cleanup subfunction.
Summary:
[Coroutines] Part 9: Add cleanup subfunction.
This patch completes coroutine heap allocation elision. Now, the heap elision example from docs\Coroutines.rst compiles and produces expected result (see test/Transform/Coroutines/ex3.ll)
Intrinsic Changes:
* coro.free gets a token parameter tying it to coro.id to allow reliably discovering all coro.frees associated with a particular coroutine.
* coro.id gets an extra parameter that points back to a coroutine function. This allows to check whether a coro.id describes the enclosing function or it belongs to a different function that was later inlined.
CoroSplit now creates three subfunctions:
# f$resume - resume logic
# f$destroy - cleanup logic, followed by a deallocation code
# f$cleanup - just the cleanup code
CoroElide pass during devirtualization replaces coro.destroy with either f$destroy or f$cleanup depending whether heap elision is performed or not.
Other fixes, improvements:
* Fixed buglet in Shape::buildFrame that was not creating coro.save properly if coroutine has more than one suspend point.
* Switched to using variable width suspend index field (no longer limited to 32 bit index field can be as little as i1 or as large as i<whatever-size_t-is>)
Reviewers: majnemer
Subscribers: llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D23844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279971
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Sanjay Patel [Mon, 29 Aug 2016 13:32:41 +0000 (13:32 +0000)]
[TargetLowering] remove fdiv and frem from canOpTrap() (PR29114)
Assuming the default FP env, we should not treat fdiv and frem any differently in terms of
trapping behavior than any other FP op. Ie, FP ops do not trap with the default FP env.
This matches how we treat these ops in IR with isSafeToSpeculativelyExecute(). There's a
similar bug in Constant::canTrap().
This bug manifests in PR29114:
https://llvm.org/bugs/show_bug.cgi?id=29114
...as a sequence of scalar divisions instead of a vector division on x86 for a <3 x float>
type.
Differential Revision: https://reviews.llvm.org/D23974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279970
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Krzysztof Parzyszek [Mon, 29 Aug 2016 13:15:35 +0000 (13:15 +0000)]
Do not use MRI::getMaxLaneMaskForVReg as a mask covering whole register
MRI::getMaxLaneMaskForVReg does not always cover the whole register.
For example, on X86 the upper 16 bits of EAX cannot be accessed via
any subregister. Consequently, there is no lane mask that only covers
that part of EAX. The getMaxLaneMaskForVReg will return the union of
the lane masks for all subregisters, and in case of EAX, that union
will not cover the upper 16 bits.
This fixes https://llvm.org/bugs/show_bug.cgi?id=29132
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279969
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Tom Stellard [Mon, 29 Aug 2016 13:06:10 +0000 (13:06 +0000)]
AMDGPU/SI: Improve register allocation hints for sopk instructions
Summary:
For shrinking SOPK instructions, we were creating a hint to tell the
register allocator to use the register allocated for src0 for the dst
operand as well. However, this seems to not work sometimes depending
on the order virtual registers are assigned physical registers.
To fix this, I've added a second allocation hint which does the reverse,
asks that the register allocated for dst is used for src0.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: https://reviews.llvm.org/D23862
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279968
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Rafael Espindola [Mon, 29 Aug 2016 12:47:22 +0000 (12:47 +0000)]
Use the correct ctor/dtor section for dynamic-no-pic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279967
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Benjamin Kramer [Mon, 29 Aug 2016 12:41:32 +0000 (12:41 +0000)]
Mark test as XFAIL instead of disabling it everywhere.
There is no lit feature 'X86' so this test is just disabled completely.
Make it XFAIL until a solution is found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279966
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Rafael Espindola [Mon, 29 Aug 2016 12:33:42 +0000 (12:33 +0000)]
Move code only used by codegen out of MC. NFC.
MC itself never needs to know about these sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279965
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Haojian Wu [Mon, 29 Aug 2016 12:26:33 +0000 (12:26 +0000)]
Fix -Wunused-but-set-variable warning.
Summary: A follow-up fix on r279958.
Reviewers: bkramer
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D23989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279964
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Tom Stellard [Mon, 29 Aug 2016 12:05:32 +0000 (12:05 +0000)]
AMDGPU/SI: Query AA, if available, in areMemAccessesTriviallyDisjoint()
Summary:
The SILoadStoreOptimizer will need to use AliasAnalysis here in order to
move it before scheduling.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: https://reviews.llvm.org/D23813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279963
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Igor Breger [Mon, 29 Aug 2016 09:12:31 +0000 (09:12 +0000)]
Fixed a bug in type legalizer for masked gather.
The problem occurs when the Node doesn't updated in place , UpdateNodeOperation() return the node that already exist.
In this case assert fail in PromoteIntegerOperand() , N have 2 results ( val + chain).
Differential Revision: http://reviews.llvm.org/D23756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279961
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Igor Breger [Mon, 29 Aug 2016 08:52:52 +0000 (08:52 +0000)]
[AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST sequence.
Differential Revision: http://reviews.llvm.org/D23490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279960
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Haojian Wu [Mon, 29 Aug 2016 08:48:15 +0000 (08:48 +0000)]
[InstructionSelect] NumBlocks isn't defined in DEBUG build.
Summary: A follow-up fixing on http://llvm.org/viewvc/llvm-project?view=revision&revision=279905.
Reviewers: bkramer
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D23985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279959
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Craig Topper [Mon, 29 Aug 2016 04:49:31 +0000 (04:49 +0000)]
[X86] Don't lower FABS/FNEG masking directly to a ConstantPool load. Just create a ConstantFPSDNode and let that be lowered.
This allows broadcast loads to used when available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279958
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Craig Topper [Mon, 29 Aug 2016 04:49:27 +0000 (04:49 +0000)]
[AVX-512] Always use v8i64 when converting 512-bit FAND/FOR/FXOR/FANDN to integer operations when DQI isn't supported. This is consistent with the recent changes to promote logical operations to i64 vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279957
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Craig Topper [Mon, 29 Aug 2016 04:49:24 +0000 (04:49 +0000)]
[AVX-512] Add 512-bit fabs tests with and without AVX512DQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279956
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Lang Hames [Mon, 29 Aug 2016 00:54:29 +0000 (00:54 +0000)]
[Orc] Simplify LogicalDylib and move it back inside CompileOnDemandLayer. Also
switch to using one indirect stub manager per logical dylib rather than one per
input module.
LogicalDylib is a helper class used by the CompileOnDemandLayer to manage
symbol resolution between modules during lazy compilation. In particular, it
ensures that internal symbols resolve correctly even in the case where multiple
input modules contain the same internal symbol name (which must to be promoted
to external hidden linkage so that functions in any given module can be split
out by lazy compilation). LogicalDylib's resolution scheme (before this commit)
required one stub-manager per input module. This made recompilation of functions
(by adding a module containing a new definition) difficult, as the stub manager
for any given symbol was bound to the module that supplied the original
definition. By using one stubs manager for the whole logical dylib symbols can
be more easily replaced, although support for doing this is not included in this
patch (it will be implemented in a follow up).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279952
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Craig Topper [Sun, 28 Aug 2016 22:20:51 +0000 (22:20 +0000)]
[AVX-512] Add support for selecting 512-bit VPABSB/VPABSW when BWI is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279951
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Craig Topper [Sun, 28 Aug 2016 22:20:48 +0000 (22:20 +0000)]
[AVX-512] Add patterns for selecting 128/256-bit EVEX VPABS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279950
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Craig Topper [Sun, 28 Aug 2016 22:20:45 +0000 (22:20 +0000)]
[AVX-512] Add testcases showing that we don't emit 512-bit vpabsb/vpabsw. Will be fixed in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279949
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Sylvestre Ledru [Sun, 28 Aug 2016 20:29:18 +0000 (20:29 +0000)]
Fix some typos in the doc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279943
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Sanjay Patel [Sun, 28 Aug 2016 18:31:32 +0000 (18:31 +0000)]
[x86] add tests for <3 x N> vector types (PR29114)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279939
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Sanjay Patel [Sun, 28 Aug 2016 18:18:00 +0000 (18:18 +0000)]
[InstCombine] use m_APInt to allow icmp (and X, Y), C folds for splat constant vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279937
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Simon Pilgrim [Sun, 28 Aug 2016 17:27:14 +0000 (17:27 +0000)]
[X86][AVX512] Only combine EVEX targets shuffles to shuffles of the same number of vector elements
Over eager combing prevents the correct folding of writemasks.
At the moment this occurs for ALL EVEX shuffles, in the future we need to check that the user of the root shuffle is a VSELECT that can fold to a writemask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279934
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Hal Finkel [Sun, 28 Aug 2016 16:17:58 +0000 (16:17 +0000)]
[PowerPC] Implement lowering for atomicrmw min/max/umin/umax
Implement lowering for atomicrmw min/max/umin/umax. Fixes PR28818.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279933
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Elena Demikhovsky [Sun, 28 Aug 2016 08:53:53 +0000 (08:53 +0000)]
[Loop Vectorizer] Fixed memory confilict checks.
Fixed a bug in run-time checks for possible memory conflicts inside loop.
The bug is in Low <-> High boundaries calculation. The High boundary should be calculated as "last memory access pointer + element size".
Differential revision: https://reviews.llvm.org/D23176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279930
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Craig Topper [Sun, 28 Aug 2016 06:06:28 +0000 (06:06 +0000)]
[AVX-512] Promote AND/OR/XOR to v2i64/v4i64/v8i64 even when we have AVX512F/AVX512VL.
Previously we weren't creating masked logical operations if bitcasts appeared between the logic operation and the select. The IR optimizers can move bitcasts across logic operations and create these cases. To minimize the number of cases we need to handle, this change promotes all logic ops to an i64 vector type just like when only SSE or AVX is available.
Unfortunately, this also has the consequence of making it difficult to select unmasked VPANDD/VPORD/VPXORD in all the cases it was previously used. This is the cause of most of the test change. This shouldn't result in any functional change though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279929
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Craig Topper [Sun, 28 Aug 2016 06:06:24 +0000 (06:06 +0000)]
[AVX-512] Add tests to show that we don't select masked logic ops if there are bitcasts between the logic op and the select.
This is taken from optimized IR of clang test cases for masked logic ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279928
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Craig Topper [Sun, 28 Aug 2016 06:06:21 +0000 (06:06 +0000)]
[X86] Rename PABSB/D/W instructions to be consistent with SSE/AVX instructions instead of ending 128/256. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279927
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Jan Vesely [Sat, 27 Aug 2016 19:09:43 +0000 (19:09 +0000)]
AMDGPU/R600: Enable Load combine
Fix and improve tests
Differential Revision: https://reviews.llvm.org/D23899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279925
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Craig Topper [Sat, 27 Aug 2016 17:13:43 +0000 (17:13 +0000)]
[X86] Rename predicate function that detects if requires one of the REX.B, REX.X or REX.R bits. It's old name conflicted with a function in X8II namespace that doesnt' quite do the same thing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279924
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Craig Topper [Sat, 27 Aug 2016 17:13:41 +0000 (17:13 +0000)]
[X86] Keep looping over operands looking for byte registers even if we already found a register that requires a REX prefix. Otherwise we don't error if a high byte register is used after SPL/BPL/DIL/SIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279923
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Craig Topper [Sat, 27 Aug 2016 17:13:37 +0000 (17:13 +0000)]
[X86] Include XMM/YMM/ZMM16-23 in X86II::isX86_64ExtendedReg. This feels more consistent with its name and simplifies assembler code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279922
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Craig Topper [Sat, 27 Aug 2016 17:13:34 +0000 (17:13 +0000)]
[X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test for CR8-CR15.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279921
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Craig Topper [Sat, 27 Aug 2016 05:26:54 +0000 (05:26 +0000)]
[X86] Remove stale comment about FixupBWInsts pass being off by default. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279915
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Craig Topper [Sat, 27 Aug 2016 05:22:15 +0000 (05:22 +0000)]
[AVX-512] Allow EVEX encoding unordered/ordered/equal/notequal VCMPPS/PD/SS/SD to be commuted just like the SSE and AVX counterparts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279914
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Craig Topper [Sat, 27 Aug 2016 05:22:12 +0000 (05:22 +0000)]
[X86] Enable FR32/FR64 cmpeq/cmpne/cmpunord/cmpord to be commuted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279913
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Craig Topper [Sat, 27 Aug 2016 05:22:08 +0000 (05:22 +0000)]
[AVX-512] Add load folding for EVEX vcmpps/pd/ss/sd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279912
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Teresa Johnson [Sat, 27 Aug 2016 04:41:22 +0000 (04:41 +0000)]
[LTO] Don't create a new common unless merged has different size
Summary:
This addresses a regression in common handling from the new LTO
API in r278338. Only create a new common if the size is different.
The type comparison against an array type fails when the size is
different but not an array. GlobalMerge does not handle the
array types as well and we lose some global merging opportunities.
Reviewers: mehdi_amini
Subscribers: junbuml, llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D23955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279911
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Matt Arsenault [Sat, 27 Aug 2016 03:39:27 +0000 (03:39 +0000)]
AMDGPU: Mark sched model complete
Fixes bug 26800
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279910
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Matt Arsenault [Sat, 27 Aug 2016 03:00:51 +0000 (03:00 +0000)]
AMDGPU: Remove unneeded implicit exec uses/defs
SI_BREAK, SI_IF_BREAK, and SI_ELSE_BREAK do not def exec.
SI_IF_BREAK and SI_ELSE_BREAK do not read it either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279909
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Lang Hames [Sat, 27 Aug 2016 02:59:24 +0000 (02:59 +0000)]
[Orc] Explicitly specify type for assignment.
This should fix the MSVC errors in
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/15120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279908
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Sebastian Pop [Sat, 27 Aug 2016 02:48:41 +0000 (02:48 +0000)]
GVN-hoist: invalidate MD cache (PR29144)
Without invalidating the entries in the MD cache we would try to access instructions
that were removed in previous iterations of hoisting.
Differential Revision: https://reviews.llvm.org/D23927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279907
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Quentin Colombet [Sat, 27 Aug 2016 02:38:27 +0000 (02:38 +0000)]
[RegBankSelect] Do not abort when the target wants to fall back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279906
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Quentin Colombet [Sat, 27 Aug 2016 02:38:24 +0000 (02:38 +0000)]
[InstructionSelect] Do not abort when the target wants to fall back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279905
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Quentin Colombet [Sat, 27 Aug 2016 02:38:21 +0000 (02:38 +0000)]
[MachineLegalize] Do not abort when the target wants to fall back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279904
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Matt Arsenault [Sat, 27 Aug 2016 01:32:27 +0000 (01:32 +0000)]
AMDGPU: Select mulhi 24-bit instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279902
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