OSDN Git Service
Lang Hames [Mon, 18 Jun 2018 18:01:43 +0000 (18:01 +0000)]
[ORC] Add an initial implementation of a replacement CompileOnDemandLayer.
CompileOnDemandLayer2 is a replacement for CompileOnDemandLayer built on the ORC
Core APIs. Functions in added modules are extracted and compiled lazily.
CompileOnDemandLayer2 supports multithreaded JIT'd code, and compilation on
multiple threads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334967
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Lang Hames [Mon, 18 Jun 2018 18:01:41 +0000 (18:01 +0000)]
[ORC] Keep weak flag on VSO symbol tables during materialization, but treat
materializing weak symbols as strong.
This removes some elaborate flag tweaking and plays nicer with RuntimeDyld,
which relies of weak/common flags to determine whether it should emit a given
weak definition. (Switching to strong up-front makes it appear as if there is
already an overriding definition, which would require an extra back-channel to
override).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334966
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Krzysztof Parzyszek [Mon, 18 Jun 2018 17:16:39 +0000 (17:16 +0000)]
Shrink interval after moving copy in removePartialRedundancy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334963
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Andrea Di Biagio [Mon, 18 Jun 2018 17:04:56 +0000 (17:04 +0000)]
[llvm-mca] Use an ordered map to collect hardware statistics. NFC.
Histogram entries are now ordered by key. This should improves their
readability when statistics are printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334961
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Nirav Dave [Mon, 18 Jun 2018 16:26:11 +0000 (16:26 +0000)]
Fix typoed cast to avoid assertion in MCFragment::dump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334959
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Simon Pilgrim [Mon, 18 Jun 2018 16:25:01 +0000 (16:25 +0000)]
[SLPVectorizer] Tidyup isShuffle helper
Ensure we keep track of the input vectors in all cases instead of just for SK_Select.
Ideally we'd reuse the shuffle mask pattern matching in TargetTransformInfo::getInstructionThroughput here to easily add support for all TargetTransformInfo::ShuffleKind without mass code duplication, I've added a TODO for now but D48236 should help us here.
Differential Revision: https://reviews.llvm.org/D48023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334958
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Craig Topper [Mon, 18 Jun 2018 16:17:46 +0000 (16:17 +0000)]
[TableGen] Make TiedAsmOperandTable in the AsmMatcher 'static' since its at file scope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334957
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Craig Topper [Mon, 18 Jun 2018 16:17:45 +0000 (16:17 +0000)]
[TableGen] Remove unused member variable.
I think this became unused after r324196.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334956
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Florian Hahn [Mon, 18 Jun 2018 15:18:48 +0000 (15:18 +0000)]
[VPlanRecipeBase] Add eraseFromParent().
Reviewers: dcaballe, hsaito, mkuper, hfinkel
Reviewed By: dcaballe
Differential Revision: https://reviews.llvm.org/D48081
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334951
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Sander de Smalen [Mon, 18 Jun 2018 14:47:52 +0000 (14:47 +0000)]
[AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions.
Summary:
The variants added by this patch are:
- SQINC (signed increment)
- UQINC (unsigned increment)
- SQDEC (signed decrement)
- UQDEC (unsigned decrement)
For example:
uqincw x0, all, mul #4
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Differential Revision: https://reviews.llvm.org/D47715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334948
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Simon Pilgrim [Mon, 18 Jun 2018 14:31:14 +0000 (14:31 +0000)]
[X86][BtVer2] Flag AVX2+ scheduler classes as unsupported
Jaguar only supports up to AVX1
Differential Revision: https://reviews.llvm.org/D48274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334947
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Andrea Di Biagio [Mon, 18 Jun 2018 14:00:30 +0000 (14:00 +0000)]
[llvm-mca] Add tests for XOP and AVX512 instructions that implicitly clear the upper portion of a super-register.
When the destination register of a XOP instruction is an XMM register, bits
[255:128] of the corresponding YMM register are cleared.
When the destination register of a EVEX encoded instruction is an XMM/YMM
register, the upper bits of the corresponding ZMM are cleared.
On processors that feature AVX512, a write to an XMM registers always clears the
upper portion of the corresponding ZMM register if the instruction is VEX or
EVEX encoded.
These new tests show some interesting cases which aren't correctly analyzed by
llvm-mca. The lack of knowledge related to the implicit update on the
super-registers is addressed by D48225.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334945
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Florian Hahn [Mon, 18 Jun 2018 13:51:28 +0000 (13:51 +0000)]
[VPlan] Fix sanitizer problem with insertBefore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334943
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Sander de Smalen [Mon, 18 Jun 2018 13:39:29 +0000 (13:39 +0000)]
[TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases.
Allow a tied operand of a different operand class in InstAliases,
so that the operand can be printed (and added to the MC instruction)
as the appropriate register. For example, 'GPR64as32', which would
be printed/parsed as a 32bit register and should match a tied 64bit
register operand, where the former is a sub-register of the latter.
This patch also generalizes the constraint checking to an overrideable
method in MCTargetAsmParser, so that target asmparsers can specify
whether a given operand satisfies the tied register constraint.
Reviewers: olista01, rengolin, fhahn, SjoerdMeijer, samparker, dsanders, craig.topper
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47714
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334942
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Paul Robinson [Mon, 18 Jun 2018 12:22:17 +0000 (12:22 +0000)]
Update copyright year to 2018.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334936
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Simon Pilgrim [Mon, 18 Jun 2018 11:35:36 +0000 (11:35 +0000)]
[SLPVectorizer] Avoid calling const VL.size() repeatedly in for-loop. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334934
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Florian Hahn [Mon, 18 Jun 2018 11:34:17 +0000 (11:34 +0000)]
[VPlanRecipeBase] Add insertBefore helper.
Reviewers: dcaballe, mkuper, hfinkel, hsaito, mssimpso
Reviewed By: dcaballe
Differential Revision: https://reviews.llvm.org/D48080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334933
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Clement Courbet [Mon, 18 Jun 2018 11:27:47 +0000 (11:27 +0000)]
[llvm-exegesis] Optionally ignore instructions without a sched class.
Summary: See PR37602.
Reviewers: RKSimon
Subscribers: llvm-commits, tschuett
Differential Revision: https://reviews.llvm.org/D48267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334932
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Sander de Smalen [Mon, 18 Jun 2018 10:59:19 +0000 (10:59 +0000)]
[AArch64][SVE] Asm: Support for vector element compares.
This patch adds instructions for comparing elements from two vectors, e.g.
cmpgt p0.s, p0/z, z0.s, z1.s
and also adds support for comparing to a 64-bit wide element vector, e.g.
cmpgt p0.s, p0/z, z0.s, z1.d
The patch also contains aliases for certain comparisons, e.g.:
cmple p0.s, p0/z, z0.s, z1.s => cmpge p0.s, p0/z, z1.s, z0.s
cmplo p0.s, p0/z, z0.s, z1.s => cmphi p0.s, p0/z, z1.s, z0.s
cmpls p0.s, p0/z, z0.s, z1.s => cmphs p0.s, p0/z, z1.s, z0.s
cmplt p0.s, p0/z, z0.s, z1.s => cmpgt p0.s, p0/z, z1.s, z0.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334931
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Clement Courbet [Mon, 18 Jun 2018 06:48:22 +0000 (06:48 +0000)]
[X86] Fix NOOP sched overrides on BDW/HSW/SKL.
Summary: Noop certainly does not use resources.
Reviewers: RKSimon, craig.topper, andreadb
Subscribers: gbedwell, llvm-commits, gchatelet
Differential Revision: https://reviews.llvm.org/D48028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334927
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Craig Topper [Mon, 18 Jun 2018 06:32:22 +0000 (06:32 +0000)]
[X86] Create X86InstrFMA3Group objects fully in a static table instead of on the heap. NFCI
Previously we heap allocated the X86InstrFMA3Group objects which were created by passing them small register/memory opcode arrays that existed as individual static tables.
Rather than a bunch of small static arrays we now have one large static table of X86InstrFMA3Group objects. Rather than storing a pointer to the opcode arrays in the X86InstrFMA3Group object, we now store have a register and memory array as part of the object. If a group doesn't have memory or register opcodes, the array entries will be 0.
This greatly simplifies the destruction of the X86InstrFMA3Info object. We no longer need to delete the X86InstrFMA3Group objects as we destruct the DenseMap. And we don't need to keep track of which ones we already deleted.
This reduces the llc binary size on my local machine by ~50k. I can only assume that's really due to the fact that we had something like 512 small static arrays that we passed to the init functions either one at a time or in pairs. So there were between 256 and 512 distinct calls to the init functions in the initOnceImpl method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334925
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Craig Topper [Mon, 18 Jun 2018 05:00:50 +0000 (05:00 +0000)]
[X86] Add '.s' aliases to the assembler for the various redundant move encodings to match gas and our EVEX instructions.
We already have these aliases for EVEX enocded instructions, but not for the GPR, MMX, SSE, and VEX versions.
Also remove the vpextrw.s EVEX alias. That's not something gas implements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334922
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Craig Topper [Mon, 18 Jun 2018 01:28:05 +0000 (01:28 +0000)]
[X86] Move the 'vmovq.s' and similar assembly strings for EVEX vector moves with reversed operands to InstAliases.
The .s assembly strings allow the reversed forms to be targeted from assembly which matches gas behavior. But when printing the instructions we should print them without the .s to match other tooling like objdump. By using InstAliases we can use the normal string in the instruction and just hide it from the assembly parser.
Ideally we'd add the .s versions to the legacy SSE and VEX versions as well for full compatibility with gas. Not sure how we got to state where only EVEX was supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334920
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Craig Topper [Mon, 18 Jun 2018 01:28:01 +0000 (01:28 +0000)]
[TableGen] Prevent double flattening of InstAlias asm strings in the asm matcher emitter.
Unlike CodeGenInstruction, CodeGenInstAlias was flatting asm strings in its constructor. For instructions it was the users responsibility to flatten the string.
AsmMatcherEmitter didn't know this and treated them the same. This caused double flattening of InstAliases. This is mostly harmless unless the desired assembly string contains curly braces. The second flattening wouldn't know to ignore these and would remove the curly braces. And for variant 1 it would remove the contents of them as well.
To mitigate this, this patch makes removes the flattening from the CodeGenIntAlias constructor and modifies AsmWriterEmitter to account for the flattening not having been done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334919
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Lang Hames [Sun, 17 Jun 2018 23:54:58 +0000 (23:54 +0000)]
[ORC] Remove redundant condition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334918
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Lang Hames [Sun, 17 Jun 2018 18:59:01 +0000 (18:59 +0000)]
[ORC] Only notify queries that they are resolved/ready when the query state
changes.
This guards against redundant notifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334916
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Craig Topper [Sun, 17 Jun 2018 18:00:16 +0000 (18:00 +0000)]
[X86] Add all the FMA instructions direclty to the load folding table instead of proxying through X86InstrFMA3Info.
These increases the size of the static tables, but is closer to what we would get if used the autogenerated table directly. This reduces the remaining large deltas between what's in the manual table and what's in the autogenerated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334915
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Lang Hames [Sun, 17 Jun 2018 17:18:12 +0000 (17:18 +0000)]
[ORC] Suppress an unused variable warning for a debug-mode only use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334911
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Lang Hames [Sun, 17 Jun 2018 16:59:53 +0000 (16:59 +0000)]
[ORC] Erase empty dependence sets when adding new symbol dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334910
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Lang Hames [Sun, 17 Jun 2018 16:59:52 +0000 (16:59 +0000)]
[ORC] In MaterializationResponsibility, only maintain the Materializing flag on
symbols in debug mode.
The MaterializationResponsibility class hijacks the Materializing flag to track
symbols that have not yet been resolved in order to guard against redundant
resolution. Since this is an API contract check and only enforced in debug mode
there is no reason to maintain the flag state in release mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334909
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Craig Topper [Sun, 17 Jun 2018 16:29:46 +0000 (16:29 +0000)]
[X86] Pass the parent SDNode to X86DAGToDAGISel::selectScalarSSELoad to simplify the hasSingleUseFromRoot handling.
Some of the calls to hasSingleUseFromRoot were passing the load itself. If the load's chain result has a user this would count against that. By getting the true parent of the match and ensuring any intermediate between the match and the load have a single use we can avoid this case. isLegalToFold will take care of checking users of the load's data output.
This fixed at least fma-scalar-memfold.ll to succed without the peephole pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334908
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Simon Pilgrim [Sun, 17 Jun 2018 16:25:48 +0000 (16:25 +0000)]
[llvm-mca][X86] Add some avx512f/avx512vl resource test placeholders
There are a lot of instructions to add under these ISAs (and the other AVX512 variants) but this should demonstrate how to test for the EVEX instructions with different maskings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334907
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Sander de Smalen [Sun, 17 Jun 2018 10:48:21 +0000 (10:48 +0000)]
[AArch64][SVE] Asm: Support for bitwise operations on predicate vectors.
This patch adds support for instructions performing bitwise operations
on predicate vectors, including AND, BIC, EOR, NAND, NOR, ORN, ORR, and
their status flag setting variants ANDS, BICS, EORS, NANDS, ORNS, ORRS.
This patch also adds several aliases:
orr p0.b, p1/z, p1.b, p1.b => mov p0.b, p1.b
orrs p0.b, p1/z, p1.b, p1.b => movs p0.b, p1.b
and p0.b, p1/z, p2.b, p2.b => mov p0.b, p1/z, p2.b
ands p0.b, p1/z, p2.b, p2.b => movs p0.b, p1/z, p2.b
eor p0.b, p1/z, p2.b, p1.b => not p0.b, p1/z, p2.b
eors p0.b, p1/z, p2.b, p1.b => nots p0.b, p1/z, p2.b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334906
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Sander de Smalen [Sun, 17 Jun 2018 10:11:04 +0000 (10:11 +0000)]
[AArch64][SVE] Asm: Support for SEL (vector/predicate) instructions.
Support for SVE's predicated select instructions to select elements
from either vector, both in a data-vector and a predicate-vector
variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334905
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Jonas Hahnfeld [Sun, 17 Jun 2018 09:55:20 +0000 (09:55 +0000)]
[NVPTX] Ignore target-cpu and -features for inlining
We don't want to prevent inlining because of target-cpu and -features
attributes that were added to newer versions of LLVM/Clang: There are
no incompatible functions in PTX, ptxas will throw errors in such cases.
Differential Revision: https://reviews.llvm.org/D47691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334904
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Heejin Ahn [Sun, 17 Jun 2018 00:37:56 +0000 (00:37 +0000)]
[WebAssembly] Simple comment fix. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334899
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Craig Topper [Sat, 16 Jun 2018 23:25:50 +0000 (23:25 +0000)]
[X86] More additions to the load folding tables based on the autogenerated tables.
Including more additions for NotMemoryFoldable to remove some entries from the autogenerated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334898
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Craig Topper [Sat, 16 Jun 2018 23:25:48 +0000 (23:25 +0000)]
[X86] Hide POP16/32/64rmr and PUSH16/32/64rmr instructions from the assembly parser.
These all have a short form encoding that the assembler already prefers. Though that preference seems to only be based on order in the .td fie. Hiding the long form saves space in the table and prevents us from breaking the implicit order based priority.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334897
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Craig Topper [Sat, 16 Jun 2018 23:25:47 +0000 (23:25 +0000)]
[X86] Fix an inconsistency between AVX512 and AVX/SSE version on a couple instructions.
VMOVPQIto64Zmr is not a 64-bit mode only instruction. But I don't know how to test this because VMOVPQIto64mr should always have priority over it in 32-bit mode since its only advantage is XMM16-XMM31 which aren't usable in 32-bit mode.
VMOVPQIto64Zrr is a 64-bit mode only instruction, but we don't need to explicitly mark it as such because it uses a GR64 register which won't parse in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334896
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Michael Zolotukhin [Sat, 16 Jun 2018 18:57:31 +0000 (18:57 +0000)]
CorrelatedValuePropagation: Preserve DT.
Summary:
We only modify CFG in a couple of places, and we can preserve DT there
with a little effort.
Reviewers: davide, vsk
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48059
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334895
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Florian Hahn [Sat, 16 Jun 2018 14:47:05 +0000 (14:47 +0000)]
[Dominators] Change getNode parameter type to const NodeT * (NFC).
DominatorTreeBase::getNode does not modify its parameter and this change
allows callers that only have access to const pointers to use it without
casting.
Reviewers: kuhar, dblaikie, chandlerc
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D48231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334892
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Benjamin Kramer [Sat, 16 Jun 2018 13:37:52 +0000 (13:37 +0000)]
Fix namespaces. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334890
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Florian Hahn [Sat, 16 Jun 2018 13:00:33 +0000 (13:00 +0000)]
Revert r334887, as GCC 4.8 does not have is_trivially_copy_constructible & co
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334889
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Florian Hahn [Sat, 16 Jun 2018 12:50:32 +0000 (12:50 +0000)]
[SmallSet] Avoid using is_trivially_XXX<>::value which is C++17
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334888
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Florian Hahn [Sat, 16 Jun 2018 12:36:19 +0000 (12:36 +0000)]
[SmallSet] Add SmallSetIterator.
This patch adds a simple const_iterator implementation for SmallSet by
delegating to either a SmallVector::const_iterator or
std::set::const_iterator, depending on which storage is used by the
SmallSet.
Reviewers: dblaikie, craig.topper
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D47942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334887
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Stanislav Mekhanoshin [Sat, 16 Jun 2018 03:46:59 +0000 (03:46 +0000)]
[AMDGPU] setcc (select cc, CT, CF), CF, eq | ne -> xor cc, -1 | cc
This is the common case in the BE when we serialize condition and then
rematerialize it. Use either original or inverted condition.
Differential Revision: https://reviews.llvm.org/D48246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334882
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Nirav Dave [Sat, 16 Jun 2018 02:51:29 +0000 (02:51 +0000)]
Avoid needing to walk out legalization tables. NFCI.
Relanding after fixing expensive check from modifying tables.
To avoid redundant work, during DAG legalization we keep tables
mapping pre-legalized SDValues to post-legalized SDValues and a
SDValue-to-SDValue map to enable fast node replacements. However, as
the keys are nodes which may be reused it is possible that an entry in
a table refers to a now deleted node N (that should have been renamed
by the value replacement map) while a new node N' exists. If N' is
then replaced that entry would be wrong. Previously we avoided this by
when potentially violating this property, walking every table and
updating all node pointers. This is very expensive but hopefully rare
occurance.
This patch assigns each instance of a SDValue used in legalization a
unique id and uses these ids in the legalization tables. This avoids
any such aliasing issue, avoiding the full table search and allowing
more aggressive incremental table pruning.
In some cases this is a 1000x speedup to compilation.
Reviewers: jyknight, echristo, bogner, tra
Reviewed By: bogner
Subscribers: dberris, grandinj, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D47959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334880
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Justin Lebar [Sat, 16 Jun 2018 00:14:10 +0000 (00:14 +0000)]
Revert "[SCEV] Use LLVM_MARK_AS_BITMASK_ENUM in SCEV." -- breaks MSVC builds.
This reverts D48237.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334878
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Justin Lebar [Sat, 16 Jun 2018 00:13:57 +0000 (00:13 +0000)]
Revert "[SCEV] Simplify some flags expressions." -- dependent revision breaks MSVC builds.
This reverts D48238.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334877
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Michael Berg [Sat, 16 Jun 2018 00:03:06 +0000 (00:03 +0000)]
Utilize new SDNode flag functionality to expand current support for fma
Summary: This patch originated from D47388 and is a proper subset of the originating changes, containing only the fmf optimization guard extensions.
Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar, rampitec, nhaehnle, nemanjai
Reviewed By: rampitec, nhaehnle
Subscribers: tpr, nemanjai, wdng
Differential Revision: https://reviews.llvm.org/D47918
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334876
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Justin Lebar [Fri, 15 Jun 2018 23:52:11 +0000 (23:52 +0000)]
[SCEV] Simplify some flags expressions.
Summary:
Sending for presubmit review out of an abundance of caution; it would be
bad to mess this up.
Reviewers: sanjoy
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334875
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Justin Lebar [Fri, 15 Jun 2018 23:51:57 +0000 (23:51 +0000)]
[SCEV] Use LLVM_MARK_AS_BITMASK_ENUM in SCEV.
Summary:
Obviates the need for mask/clear/setFlags helpers.
There are some expressions here which can be simplified, but to keep
this easy to review, I have not simplified them in this patch.
No functional change.
Reviewers: sanjoy
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334874
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Daniel Sanders [Fri, 15 Jun 2018 23:13:43 +0000 (23:13 +0000)]
[globalisel][tablegen] Add support for C++ predicates on PatFrags and use it to support BFC on ARM.
So far, we've only handled special cases of PatFrag like ImmLeaf. This patch
adds support for the remaining cases using similar mechanisms.
Like most C++ code from SelectionDAG, GISel and DAGISel expect to operate on
different types and representations and as such the code is not compatible
between the two. It's therefore necessary to add an alternative implementation
in the GISelPredicateCode field.
The target test for this feature could easily be done with IntImmLeaf and this
would save on a little boilerplate. The reason I've chosen to implement this
using PatFrag.GISelPredicateCode and not IntImmLeaf is because I was unable to
find a rule that was blocked solely by lack of support for PatFrag predicates. I
found that the ones I investigated as being likely candidates for the test
were further blocked by other things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334871
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Francis Visoiu Mistrih [Fri, 15 Jun 2018 23:05:41 +0000 (23:05 +0000)]
Revert r334729 "[DAG] Avoid needing to walk out legalization tables. NFCI."
This reverts commit r334729.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334869
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Francis Visoiu Mistrih [Fri, 15 Jun 2018 23:05:40 +0000 (23:05 +0000)]
Revert r334731 "Avoid unused variable in non-assert builds."
This reverts commit r334731.
It breaks EXPENSIVE_CHECKS bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334868
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Craig Topper [Fri, 15 Jun 2018 22:25:04 +0000 (22:25 +0000)]
[X86] Add more instructions to the hasUndefRegUpdate list.
Not sure any of these matter today because I don't think we ever produce them with IMPLICIT_DEF as an input. But by listing them we don't be suprised in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334867
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Benjamin Kramer [Fri, 15 Jun 2018 21:06:43 +0000 (21:06 +0000)]
[BPI] Remove unnecessary std::list
vector is sufficient here. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334865
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Cameron McInally [Fri, 15 Jun 2018 20:57:55 +0000 (20:57 +0000)]
[FPEnv] Expand constrained FP POWI
Modify ExpandStrictFPOp(...) to handle nodes that have scalar
operands.
Also, add a Strict FMA test and do some other light cleanup in the
Strict FP code.
Differential Revision: https://reviews.llvm.org/D48149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334863
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Michael Berg [Fri, 15 Jun 2018 20:44:55 +0000 (20:44 +0000)]
Utilize new SDNode flag functionality to expand current support for fdiv
Summary: This patch originated from D46562 and is a proper subset, with some issues addressed.
Reviewers: spatel, hfinkel, wristow, arsenm
Reviewed By: spatel
Subscribers: wdng, nhaehnle
Differential Revision: https://reviews.llvm.org/D47954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334862
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Matt Morehouse [Fri, 15 Jun 2018 20:12:58 +0000 (20:12 +0000)]
[SanitizerCoverage] Add associated metadata to pc-tables.
Summary:
Using associated metadata rather than llvm.used allows linkers to
perform dead stripping with -fsanitize-coverage=pc-table. Unfortunately
in my local tests, LLD was the only linker that made use of this metadata.
Partially addresses https://bugs.llvm.org/show_bug.cgi?id=34636 and fixes
https://github.com/google/sanitizers/issues/971.
Reviewers: eugenis
Reviewed By: eugenis
Subscribers: Dor1s, hiraditya, llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D48203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334858
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Geoff Berry [Fri, 15 Jun 2018 20:02:11 +0000 (20:02 +0000)]
Update my information in the CREDITS file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334857
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Sean Fertile [Fri, 15 Jun 2018 19:47:16 +0000 (19:47 +0000)]
[PowerPC] Add support for high and higha symbol modifiers on tls modifers.
Enables using the high and high-adjusted symbol modifiers on thread local
storage modifers in powerpc assembly. Needed to be able to support 64 bit
thread-pointer and dynamic-thread-pointer access sequences.
Differential Revision: https://reviews.llvm.org/D47754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334856
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Sean Fertile [Fri, 15 Jun 2018 19:47:11 +0000 (19:47 +0000)]
[PPC64] Support "symbol@high" and "symbol@higha" symbol modifers.
Add support for the "@high" and "@higha" symbol modifiers in powerpc64 assembly.
The modifiers represent accessing the segment consiting of bits 16-31 of a
64-bit address/offset.
Differential Revision: https://reviews.llvm.org/D47729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334855
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Diego Caballero [Fri, 15 Jun 2018 18:46:03 +0000 (18:46 +0000)]
Move redundant-vf2-cost.ll test to X86 directory
redundant-vf2-cost.ll is X86 specific. Moved from
test/Transforms/LoopVectorize/redundant-vf2-cost.ll to
test/Transforms/LoopVectorize/X86/redundant-vf2-cost.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334854
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Simon Pilgrim [Fri, 15 Jun 2018 18:35:25 +0000 (18:35 +0000)]
[llvm-mca][x86] Add Generic cpu resource tests
Added a Generic x86 cpu set of resource tests to allow us to check all ISAs.
We currently use SandyBridge as our generic CPU model, but it's better if we actually duplicate these tests for if/when we change the model, it also means we don't end up polluting the SandyBridge folder with tests for ISAs it doesn't support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334853
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Tomasz Krupa [Fri, 15 Jun 2018 18:05:24 +0000 (18:05 +0000)]
[X86] Lowering sqrt intrinsics to native IR
Summary: Complementary patch to lowering sqrt intrinsics in Clang.
Reviewers: craig.topper, spatel, RKSimon, DavidKreitzer, uriel.k
Reviewed By: craig.topper
Subscribers: tkrupa, mike.dvoretsky, llvm-commits
Differential Revision: https://reviews.llvm.org/D41599
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334849
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Craig Topper [Fri, 15 Jun 2018 17:56:17 +0000 (17:56 +0000)]
[X86] Prevent folding stack reloads into instructions in hasUndefRegUpdate.
An earlier commit prevented folds from the peephole pass by checking for IMPLICIT_DEF. But later in the pipeline IMPLICIT_DEF just becomes and Undef flag on the input register so we need to check for that case too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334848
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Krzysztof Parzyszek [Fri, 15 Jun 2018 16:58:22 +0000 (16:58 +0000)]
Remove <undef> from rematerialized full register
When coalescing a small register into a subregister of a larger register,
if the larger register is rematerialized, the function updateRegDefUses
can add an <undef> flag to the rematerialized definition (since it's
treating it as only definining the coalesced subregister). While with that
assumption doing so is not incorrect, make sure to remove the flag later
on after the call to updateRegDefUses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334845
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Joseph Tremoulet [Fri, 15 Jun 2018 16:52:40 +0000 (16:52 +0000)]
[InstCombine] Avoid iteration/mutation conflict
Summary:
When iterating users of a multiply in processUMulZExtIdiom, the
call to setOperand in the truncation case may replace the use
being visited; make sure the iterator has been advanced before
doing that replacement.
Reviewers: majnemer, davide
Reviewed By: davide
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334844
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Sander de Smalen [Fri, 15 Jun 2018 16:39:46 +0000 (16:39 +0000)]
[AArch64][SVE] Asm: Support for CPY SIMD/FP and GPR instructions.
Predicated splat/copy of SIMD/FP register or general purpose
register to SVE vector, along with MOV-aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334842
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Jordan Rose [Fri, 15 Jun 2018 16:35:31 +0000 (16:35 +0000)]
Avoid copying PrettyStackTrace messages an extra time on Apple OSs
We were unnecessarily going from SmallString to std::string just to
get a null-terminated C string. So just...don't do that. Crash
slightly faster!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334841
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Diego Caballero [Fri, 15 Jun 2018 16:21:35 +0000 (16:21 +0000)]
[LV] Prevent LV to run cost model twice for VF=2
This is a minor fix for LV cost model, where the cost for VF=2 was
computed twice when the vectorization of the loop was forced without
specifying a VF.
Reviewers: xusx595, hsaito, fhahn, mkuper
Reviewed By: hsaito, xusx595
Differential Revision: https://reviews.llvm.org/D48048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334840
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Sander de Smalen [Fri, 15 Jun 2018 15:47:44 +0000 (15:47 +0000)]
[AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions.
Increment/decrement scalar register by (scaled) element count given by
predicate pattern, e.g. 'incw x0, all, mul #4'.
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47713
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334838
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Matt Arsenault [Fri, 15 Jun 2018 15:31:36 +0000 (15:31 +0000)]
AMDGPU: Add combine for short vector extract_vector_elts
Try to access pieces 4 bytes at a time. This helps
various hasOneUse extract_vector_elt combines, such
as load width reductions.
Avoids test regressions in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334836
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Matt Arsenault [Fri, 15 Jun 2018 15:15:46 +0000 (15:15 +0000)]
AMDGPU: Make v4i16/v4f16 legal
Some image loads return these, and it's awkward working
around them not being legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334835
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Paul Semel [Fri, 15 Jun 2018 14:15:02 +0000 (14:15 +0000)]
[llvm-readobj] Add -string-dump (-p) option
This option prints the section content as a string.
Differential Revision: https://reviews.llvm.org/D47989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334834
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Roman Lebedev [Fri, 15 Jun 2018 14:01:43 +0000 (14:01 +0000)]
[MCA] Add -summary-view option
Summary:
While that is indeed a quite interesting summary stat,
there are cases where it does not really add anything
other than consuming extra lines.
Declutters the output of D48190.
Reviewers: RKSimon, andreadb, courbet, craig.topper
Reviewed By: andreadb
Subscribers: javed.absar, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334833
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Roman Lebedev [Fri, 15 Jun 2018 14:01:35 +0000 (14:01 +0000)]
[MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats
Summary:
There does not seem to be any other tests for this.
Split off from D47676.
Reviewers: RKSimon, craig.topper, courbet, andreadb
Reviewed By: andreadb
Subscribers: javed.absar, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48190
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334832
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Sander de Smalen [Fri, 15 Jun 2018 13:57:51 +0000 (13:57 +0000)]
[AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions.
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: javed.absar
Differential Revision: https://reviews.llvm.org/D47712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334831
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Bjorn Pettersson [Fri, 15 Jun 2018 13:48:55 +0000 (13:48 +0000)]
Re-apply "[DebugInfo] Check size of variable in ConvertDebugDeclareToDebugValue"
This is r334704 (which was reverted in r334732) with a fix for
types like x86_fp80. We need to use getTypeAllocSizeInBits and
not getTypeStoreSizeInBits to avoid dropping debug info for
such types.
Original commit msg:
> Summary:
> Do not convert a DbgDeclare to DbgValue if the store
> instruction only refer to a fragment of the variable
> described by the DbgDeclare.
>
> Problem was seen when for example having an alloca for an
> array or struct, and there were stores to individual elements.
> In the past we inserted a DbgValue intrinsics for each store,
> just as if the store wrote the whole variable.
>
> When handling store instructions we insert a DbgValue that
> indicates that the variable is "undefined", as we do not know
> which part of the variable that is updated by the store.
>
> When ConvertDebugDeclareToDebugValue is used with a load/phi
> instruction we assert that the referenced value is large enough
> to cover the whole variable. Afaict this should be true for all
> scenarios where those methods are used on trunk. If the assert
> blows in the future I guess we could simply skip to insert a
> dbg.value instruction.
>
> In the future I think we should examine which part of the variable
> that is accessed, and add a DbgValue instrinsic with an appropriate
> DW_OP_LLVM_fragment expression.
>
> Reviewers: dblaikie, aprantl, rnk
>
> Reviewed By: aprantl
>
> Subscribers: JDevlieghere, llvm-commits
>
> Tags: #debug-info
>
> Differential Revision: https://reviews.llvm.org/D48024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334830
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Simon Dardis [Fri, 15 Jun 2018 13:29:35 +0000 (13:29 +0000)]
[mips] Add licensing information of the microMIPS tablegen files. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334827
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Sander de Smalen [Fri, 15 Jun 2018 13:11:49 +0000 (13:11 +0000)]
[AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates.
Some instructions require of a limited set of FP immediates as operands,
for example '#0.5 or #1.0' for SVE's FADD instruction.
This patch adds support for parsing and printing such FP immediates as
exact values (e.g. #0.499999 is not accepted for #0.5).
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47711
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334826
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Roman Lebedev [Fri, 15 Jun 2018 12:41:50 +0000 (12:41 +0000)]
[NFC] chmod +x utils/update_analyze_test_checks.py
Looks like a simple oversight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334825
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Matt Arsenault [Fri, 15 Jun 2018 12:09:15 +0000 (12:09 +0000)]
DAG: Fix creating concat_vectors with illegal type
Test passes as is, but fails with future patch to make v4i16/v4f16
legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334823
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Simon Pilgrim [Fri, 15 Jun 2018 10:29:37 +0000 (10:29 +0000)]
[SLP][X86] Add AVX2 run to POW2 SDIV Tests
Non-uniform pow2 tests are only make sense on targets with fast (low cost) non-uniform shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334821
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Simon Pilgrim [Fri, 15 Jun 2018 10:07:03 +0000 (10:07 +0000)]
[SLP][X86] Regenerate POW2 SDIV Tests
Added non-uniform pow2 test as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334819
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Roman Lebedev [Fri, 15 Jun 2018 09:56:52 +0000 (09:56 +0000)]
[InstCombine] Recommit: Fold (x << y) >> y -> x & (-1 >> y)
Summary:
We already do it for splat constants, but not just values.
Also, undef cases are mostly non-functional.
The original commit was reverted because
it broke tests for amdgpu backend, which i didn't check.
Now, the backed was updated to recognize these new
patterns, so we are good.
https://bugs.llvm.org/show_bug.cgi?id=37603
https://rise4fun.com/Alive/cplX
Reviewers: spatel, craig.topper, mareko, bogner, rampitec, nhaehnle, arsenm
Reviewed By: spatel, rampitec, nhaehnle
Subscribers: wdng, nhaehnle, llvm-commits
Differential Revision: https://reviews.llvm.org/D47980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334818
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Roman Lebedev [Fri, 15 Jun 2018 09:56:45 +0000 (09:56 +0000)]
[AMDGPU] Recognize x & ~(-1 << y) pattern.
Summary: The same pattern as D48010, but this one is IR-canonical as of D47428.
Reviewers: nhaehnle, bogner, tstellar, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #amdgpu
Differential Revision: https://reviews.llvm.org/D48012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334817
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Roman Lebedev [Fri, 15 Jun 2018 09:56:39 +0000 (09:56 +0000)]
[AMDGPU] Recognize x & ((1 << y) - 1) pattern.
Summary:
As a followup for D48007.
Since we already handle `x << (bitwidth - y) >> (bitwidth - y)` pattern,
which does not have ub for both the edge cases (`y == 0`, `y == bitwidth`),
i think also handling a pattern that is ub for `y == bitwidth` should be fine.
Reviewers: nhaehnle, bogner, tstellar, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #amdgpu
Differential Revision: https://reviews.llvm.org/D48010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334816
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Roman Lebedev [Fri, 15 Jun 2018 09:56:31 +0000 (09:56 +0000)]
[AMDGPU] Recognize x & (-1 >> (32 - y)) pattern.
Summary:
D47980 will canonicalize the `x << (32 - y) >> (32 - y)`,
which is the pattern the AMDGPU expects to `x & (-1 >> (32 - y))`,
which is not recognized by AMDGPU.
Thus, it needs to be recognized, too.
Reviewers: nhaehnle, bogner, tstellar, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #amdgpu
Differential Revision: https://reviews.llvm.org/D48007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334815
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Peter Smith [Fri, 15 Jun 2018 09:48:18 +0000 (09:48 +0000)]
[MC] Move bundling and MCSubtargetInfo to MCEncodedFragment [NFC]
Instruction bundling is only supported on descendants of the
MCEncodedFragment type. By moving the bundling functionality and
MCSubtargetInfo to this class it makes it easier to set and extract the
MCSubtargetInfo when it is necessary.
This is a refactoring change that will make it easier to pass the
MCSubtargetInfo through to writeNops when nop padding is required.
Differential Revision: https://reviews.llvm.org/D45959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334814
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Clement Courbet [Fri, 15 Jun 2018 09:46:57 +0000 (09:46 +0000)]
[llvm-exegesis][NFC] Remove dead variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334813
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Clement Courbet [Fri, 15 Jun 2018 09:27:12 +0000 (09:27 +0000)]
[llvm-exegesis][NFC] Add more comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334811
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QingShan Zhang [Fri, 15 Jun 2018 08:34:41 +0000 (08:34 +0000)]
add myself to the CREDITS.TXT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334808
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Mikhail Dvoretckii [Fri, 15 Jun 2018 07:59:29 +0000 (07:59 +0000)]
NFC: Regenerating x86-sse41.ll test for InstCombine
Test regenerated to reduce noise in further patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334806
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Clement Courbet [Fri, 15 Jun 2018 07:30:45 +0000 (07:30 +0000)]
[llvm-exegesis] Print the whole snippet in analysis.
Summary:
On hover, the whole asm snippet is displayed, including operands.
This requires the actual assembly output instead of just the MCInsts:
This is because some pseudo-instructions get lowered to actual target
instructions during codegen (e.g. ABS_Fp32 -> SSE or X87).
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334805
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Craig Topper [Fri, 15 Jun 2018 06:15:26 +0000 (06:15 +0000)]
Revert r334802 "[X86] Prevent folding stack reloads with instructions that have an undefined register update."
There's a typo causing the build to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334803
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Craig Topper [Fri, 15 Jun 2018 06:11:36 +0000 (06:11 +0000)]
[X86] Prevent folding stack reloads with instructions that have an undefined register update.
We want to keep the load unfolded so we can use the same register for both sources to avoid a false dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334802
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Craig Topper [Fri, 15 Jun 2018 05:49:19 +0000 (05:49 +0000)]
[X86] Add more instructions to the memory folding tables using the autogenerated table as a guide.
I think this covers most of the unmasked vector instructions. We're still missing a lot of the masked instructions.
There are some test changes here because of the new folding support. I don't think these particular cases should be folded because it creates an undef register dependency. I think the changes introduced in r334175 are not handling stack folding. They're only blocking the peephole pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334800
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Hiroshi Inoue [Fri, 15 Jun 2018 05:10:09 +0000 (05:10 +0000)]
[NFC] fix trivial typos in documents
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334799
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