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Sean Eveson [Wed, 4 Oct 2017 08:54:37 +0000 (08:54 +0000)]
[llvm-cov] Fix showing title when filtering and not outputting to a directory
Differential Revision: https://reviews.llvm.org/D38507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314885
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George Rimar [Wed, 4 Oct 2017 08:50:08 +0000 (08:50 +0000)]
[MC] - Don't assert when non-english characters are used.
I found that llvm-mc does not like non-english characters even in comments,
which it tries to tokenize.
Problem happens because of functions like isdigit(), isalnum() which takes
int argument and expects it is not negative.
But at the same time MCParser uses char* to store input buffer poiner, char has signed value,
so it is possible to pass negative value to one of functions from above and
that triggers an assert.
Testcase for demonstration is provided.
To fix the issue helper functions were introduced in StringExtras.h
Differential revision: https://reviews.llvm.org/D38461
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314883
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Mikael Holmen [Wed, 4 Oct 2017 07:42:45 +0000 (07:42 +0000)]
Recommit [UnreachableBlockElim] Use COPY if PHI input is undef
This time invoking llc with "-march=x86-64" in the testcase, so we don't assume
the default target is x86.
Summary:
If we have
%vreg0<def> = PHI %vreg2<undef>, <BB#0>, %vreg3, <BB#2>; GR32:%vreg0,%vreg2,%vreg3
%vreg3<def,tied1> = ADD32ri8 %vreg0<kill,tied0>, 1, %EFLAGS<imp-def>; GR32:%vreg3,%vreg0
then we can't just change %vreg0 into %vreg3, since %vreg2 is actually
undef. We would have to also copy the undef flag to be able to change the
register.
Instead we deal with this case like other cases where we can't just
replace the register: we insert a COPY. The code creating the COPY already
copied all flags from the PHI input, so the undef flag will be transferred
as it should.
Reviewers: kparzysz
Reviewed By: kparzysz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314882
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Max Kazantsev [Wed, 4 Oct 2017 06:53:22 +0000 (06:53 +0000)]
[IRCE] Temporarily disable unsigned latch conditions by default
We have found some corner cases connected to range intersection where IRCE makes
a bad thing when the latch condition is unsigned. The fix for that will go as a follow up.
This patch temporarily disables IRCE for unsigned latch conditions until the issue is fixed.
The unsigned latch conditions were introduced to IRCE by rL310027.
Differential Revision: https://reviews.llvm.org/D38529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314881
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Mikael Holmen [Wed, 4 Oct 2017 06:39:22 +0000 (06:39 +0000)]
Revert r314879 "[UnreachableBlockElim] Use COPY if PHI input is undef"
Build-bots broke on the new testcase. I'll investigate and fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314880
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Mikael Holmen [Wed, 4 Oct 2017 06:06:31 +0000 (06:06 +0000)]
[UnreachableBlockElim] Use COPY if PHI input is undef
Summary:
If we have
%vreg0<def> = PHI %vreg2<undef>, <BB#0>, %vreg3, <BB#2>; GR32:%vreg0,%vreg2,%vreg3
%vreg3<def,tied1> = ADD32ri8 %vreg0<kill,tied0>, 1, %EFLAGS<imp-def>; GR32:%vreg3,%vreg0
then we can't just change %vreg0 into %vreg3, since %vreg2 is actually
undef. We would have to also copy the undef flag to be able to change the
register.
Instead we deal with this case like other cases where we can't just
replace the register: we insert a COPY. The code creating the COPY already
copied all flags from the PHI input, so the undef flag will be transferred
as it should.
Reviewers: kparzysz
Reviewed By: kparzysz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314879
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Martin Storsjo [Wed, 4 Oct 2017 05:12:10 +0000 (05:12 +0000)]
[X86] Fix using the SJLJ jump table on x86_64
The previous version didn't work if the jump table base address didn't
fit in 32 bit, since it was encoded as an immediate offset. And in case
the jump table is encoded as 32 bit label differences, we need to
load and add them to the table base first.
This solves the first half of the issues mentioned in PR34720.
Also fix some of the errors pointed out by -verify-machineinstrs, by
using GR32_NOSPRegClass.
Differential Revision: https://reviews.llvm.org/D38333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314876
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Adam Nemet [Wed, 4 Oct 2017 04:26:23 +0000 (04:26 +0000)]
Move verbosity check for remarks to the diag handler
Test needs some slight adjustment because we no longer check the existence of
BFI but rather that the actual hotness is set on the remark. If entry_count
is not set getBlockProfileCount returns None.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314874
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Tim Shen [Wed, 4 Oct 2017 01:05:34 +0000 (01:05 +0000)]
[FuzzerUtil] Partially revert D38481 on FuzzerUtil
This is because lib/Fuzzer doesn't really depend on llvm infrastucture.
It's not easy to access the llvm hardware_concurrency here.
Differential Reivision: https://reviews.llvm.org/D38481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314870
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Adrian Prantl [Tue, 3 Oct 2017 23:46:57 +0000 (23:46 +0000)]
Add a manpage for llvm-dwarfdump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314863
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Rui Ueyama [Tue, 3 Oct 2017 23:12:01 +0000 (23:12 +0000)]
Simplify multikey_qsort function.
This function implements the three-way radix quicksort algorithm.
This patch simplifies the implementation by using MutableArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314858
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Balaram Makam [Tue, 3 Oct 2017 22:39:24 +0000 (22:39 +0000)]
[AArch64] Use LateSimplifyCFG after expanding atomic operations.
Summary:
After r308422 we defer optimizations that can destroy loop canonical forms to
LateSimplifyCFG. Running LateSimplifyCFG after expanding atomic operations
can exploit more control-flow opportunities.
Reviewers: mcrosier, t.p.northover, efriedma
Reviewed By: efriedma
Subscribers: aemerson, rengolin, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D38262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314857
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Adrian Prantl [Tue, 3 Oct 2017 22:08:22 +0000 (22:08 +0000)]
llvm-dwarfdump: implement the --regex option in combination with --name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314855
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Konstantin Zhuravlyov [Tue, 3 Oct 2017 21:45:01 +0000 (21:45 +0000)]
AMDGPU: Expand setcc for v2f32 and v4f32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314853
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Konstantin Zhuravlyov [Tue, 3 Oct 2017 21:31:24 +0000 (21:31 +0000)]
AMDGPU: Expand setcc for v2i32 and v4i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314852
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Konstantin Zhuravlyov [Tue, 3 Oct 2017 21:18:03 +0000 (21:18 +0000)]
AMDGPU/Docs: Follow up on review feedback in https://reviews.llvm.org/D38387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314848
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Jakub Kuderski [Tue, 3 Oct 2017 21:17:48 +0000 (21:17 +0000)]
[Dominators] Make eraseNode invalidate DFS numbers
This patch makes DT::eraseNode mark DFSInfo as invalid.
Not marking it as invalid leads to DFS numbers getting corrupted
and failing VerifyDFSNumbers check.
This patch also makes children iterator const (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314847
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Konstantin Zhuravlyov [Tue, 3 Oct 2017 21:14:14 +0000 (21:14 +0000)]
AMDGPU: Add ELFOSABI_AMDGPU_MESA3D
Differential Revision: https://reviews.llvm.org/D38387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314846
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Reid Kleckner [Tue, 3 Oct 2017 21:12:18 +0000 (21:12 +0000)]
[X86] Remove dead declaration convertArgMovsToPushes, NFC
This was dead when it landed in r252578. We have this functionality, if
not for stack probe calls, but for regular calls in
X86CallFrameOptimization.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314845
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Rafael Espindola [Tue, 3 Oct 2017 20:59:43 +0000 (20:59 +0000)]
Pre-compute the tail of the archive
An archive looks like
<header>
<symbol table>
<tail>
The symbol table refers to offsets in the tail. A complication is that
we would like to support symbol tables that use 64 bit offsets if it
turns out that any of the offsets is too big.
This patch changes the archive writer to first compute the tail. We
cannot just compute one big StringRef since that would require reading
every member upfront, but we can represent it as a series of
StringRefs.
Having done that it is much easier to compute the symbol table and all
offsets are computed before it is written. With this if there is an
accounting problem it will show up with a regular symbol table, not
just when a 64 bit one is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314844
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Konstantin Zhuravlyov [Tue, 3 Oct 2017 20:54:07 +0000 (20:54 +0000)]
AMDGPU: Add ELFOSABI_AMDGPU_PAL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314843
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Reid Kleckner [Tue, 3 Oct 2017 20:36:40 +0000 (20:36 +0000)]
Refactor DIBuilder dbg intrinsic insertion, NFC
Both dbg.declare and dbg.value insertion had duplicate code for the two
overloads with different insertion point conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314839
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Sanjay Patel [Tue, 3 Oct 2017 20:34:20 +0000 (20:34 +0000)]
[InstCombine] add tests for icmp gt/lt (shr X, C1), C2; NFC
Surprisingly, we have zero coverage for these patterns.
Many of these are handled in InstSimplify, but it's not obvious
what the rule for folding each case should be, so I've just
stamped out everything.
It should be possible to fold every case, but currently, we
miss these:
int ashr_slt(int x) {
return (x >> 1) < 1;
}
int ashr_sgt(int x) {
return (x >> 1) > 0;
}
https://godbolt.org/g/aB2hLE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314837
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Jessica Paquette [Tue, 3 Oct 2017 20:32:55 +0000 (20:32 +0000)]
[MachineOutliner] Fix off-by-one in cost model
This commit does two things. Firstly, it cleans up some of the benefit
calculation wrt outlined functions and candidates. Secondly, it fixes an
off-by-one bug in the cost model which was caused by the benefit value of
an OutlinedFunction and Candidate differing by 1. It updates the remarks test
to reflect this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314836
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Stefan Pintilie [Tue, 3 Oct 2017 20:27:30 +0000 (20:27 +0000)]
[PowerPC] Revert P9 scheduling model to incomplete
Partially revert a previous change from commit: https://llvm.org/svn/llvm-project/llvm/trunk@314026
The previous change caused regressions on Power 9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314835
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Craig Topper [Tue, 3 Oct 2017 19:14:23 +0000 (19:14 +0000)]
[InstCombine] Use isSignBitCheck to simplify an if statement. Directly create new sign bit compares instead of manipulating the constant. NFCI
Since we no longer had the direct constant compares, manipulating the constant seemeded less clear.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314830
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Tim Renouf [Tue, 3 Oct 2017 19:03:52 +0000 (19:03 +0000)]
[AMDGPU] implemented pal metadata
Summary:
For the amdpal OS type:
We write an AMDGPU_PAL_METADATA record in the .note section in the ELF
(or as an assembler directive). It contains key=value pairs of 32 bit
ints. It is a merge of metadata from codegen of the shaders, and
metadata provided by the frontend as _amdgpu_pal_metadata IR metadata.
Where both sources have a key=value with the same key, the two values
are ORed together.
This .note record is part of the amdpal ABI and will be documented in
docs/AMDGPUUsage.rst in a future commit.
Eventually the amdpal OS type will stop generating the .AMDGPU.config
section once the frontend has safely moved over to using the .note
records above instead of .AMDGPU.config.
Reviewers: arsenm, nhaehnle, dstuttard
Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D37753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314829
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Alexander Timofeev [Tue, 3 Oct 2017 18:55:36 +0000 (18:55 +0000)]
[AMDGPU] Avoid predicated execution of the basic blocks containing scalar
instructions.
Differential revision: https://reviews.llvm.org/D38293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314828
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Hans Wennborg [Tue, 3 Oct 2017 18:44:12 +0000 (18:44 +0000)]
Fix -Wcovered-switch-default warnings from r314821
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314826
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Hans Wennborg [Tue, 3 Oct 2017 18:39:13 +0000 (18:39 +0000)]
Revert r314817 "[dwarfdump] Add -lookup option"
The test fails on Linux; see follow-up email on the llvm-commits list.
> Add the option to lookup an address in the debug information and print
> out the file, function, block and line table details.
>
> Differential revision: https://reviews.llvm.org/D38409
This also reverts the follow-up r314818:
> [test] Fix llvm-dwarfdump/cmdline.test
>
> Fixes test/tools/llvm-dwarfdump/cmdline.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314825
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Hans Wennborg [Tue, 3 Oct 2017 18:32:29 +0000 (18:32 +0000)]
Revert r314806 "[SLP] Vectorize jumbled memory loads."
All the buildbots are red, e.g.
http://lab.llvm.org:8011/builders/clang-cmake-aarch64-lld/builds/2436/
> Summary:
> This patch tries to vectorize loads of consecutive memory accesses, accessed
> in non-consecutive or jumbled way. An earlier attempt was made with patch D26905
> which was reverted back due to some basic issue with representing the 'use mask' of
> jumbled accesses.
>
> This patch fixes the mask representation by recording the 'use mask' in the usertree entry.
>
> Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df
>
> Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh
>
> Reviewed By: Ayal
>
> Subscribers: hans, mzolotukhin
>
> Differential Revision: https://reviews.llvm.org/D36130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314824
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Reid Kleckner [Tue, 3 Oct 2017 18:30:38 +0000 (18:30 +0000)]
Fix expectations in MC wasm init-fini-array test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314823
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Reid Kleckner [Tue, 3 Oct 2017 18:30:11 +0000 (18:30 +0000)]
Implement David Blaikie's suggestion for comparison operators
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314822
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Hans Wennborg [Tue, 3 Oct 2017 18:27:22 +0000 (18:27 +0000)]
CodeView: Provide a .def file with the register ids
The list of register ids was previously written out in a couple of dirrent
places. This puts it in a .def file and also adds a few more registers (e.g.
the x87 regs) which should lead to more readable dumps, but I didn't include
the whole list since that seems unnecessary.
X86_MC::initLLVMToSEHAndCVRegMapping is pretty ugly, but at least it's not
relying on magic constants anymore. The TODO of using tablegen still stands.
Differential revision: https://reviews.llvm.org/D38480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314821
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Reid Kleckner [Tue, 3 Oct 2017 17:59:02 +0000 (17:59 +0000)]
[DebugInfo] Correctly coalesce DBG_VALUEs that mix direct and indirect values
Summary:
This should fix a regression introduced by r313786, which switched from
MachineInstr::isIndirectDebugValue() to checking if operand 1 is an
immediate. I didn't have a test case for it until now.
A single UserValue, which approximates a user variable, may have many
DBG_VALUE instructions that disagree about whether the variable is in
memory or in a virtual register. This will become much more common once
we have llvm.dbg.addr, but you can construct such a test case manually
today with llvm.dbg.value.
Before this change, we would get two UserValues: one for direct and one
for indirect DBG_VALUE instructions describing the same variable. If we
build separate interval maps for direct and indirect locations, we will
end up accidentally coalescing identical DBG_VALUE intervals that need
to remain separate because they are broken up by intervals of the
opposite direct-ness.
Reviewers: aprantl
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D37932
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314819
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Jonas Devlieghere [Tue, 3 Oct 2017 17:28:37 +0000 (17:28 +0000)]
[test] Fix llvm-dwarfdump/cmdline.test
Fixes test/tools/llvm-dwarfdump/cmdline.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314818
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Jonas Devlieghere [Tue, 3 Oct 2017 17:10:21 +0000 (17:10 +0000)]
[dwarfdump] Add -lookup option
Add the option to lookup an address in the debug information and print
out the file, function, block and line table details.
Differential revision: https://reviews.llvm.org/D38409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314817
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Simon Pilgrim [Tue, 3 Oct 2017 17:04:36 +0000 (17:04 +0000)]
[X86] Add non-SSE tests for PR15215 as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314815
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Geoff Berry [Tue, 3 Oct 2017 16:59:13 +0000 (16:59 +0000)]
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
This reverts commit r314729.
Another bug has been encountered in an out-of-tree target reported by Quentin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314814
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Simon Pilgrim [Tue, 3 Oct 2017 16:56:57 +0000 (16:56 +0000)]
[X86][SSE] Add bool vector extraction test cases from PR15215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314813
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Rafael Espindola [Tue, 3 Oct 2017 16:25:15 +0000 (16:25 +0000)]
Use sched_getaffinity instead of std::thread::hardware_concurrency.
The issue with std::thread::hardware_concurrency is that it forwards
to libc and some implementations (like glibc) don't take thread
affinity into consideration.
With this change a llvm program that can execute in only 2 cores will
use 2 threads, even if the machine has 32 cores.
This makes benchmarking a lot easier, but should also help if someone
doesn't want to use all cores for compilation for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314809
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Dehao Chen [Tue, 3 Oct 2017 15:50:42 +0000 (15:50 +0000)]
Revert the change that accidentally went in r314806.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314807
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Mohammad Shahid [Tue, 3 Oct 2017 15:28:48 +0000 (15:28 +0000)]
[SLP] Vectorize jumbled memory loads.
Summary:
This patch tries to vectorize loads of consecutive memory accesses, accessed
in non-consecutive or jumbled way. An earlier attempt was made with patch D26905
which was reverted back due to some basic issue with representing the 'use mask' of
jumbled accesses.
This patch fixes the mask representation by recording the 'use mask' in the usertree entry.
Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df
Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh
Reviewed By: Ayal
Subscribers: hans, mzolotukhin
Differential Revision: https://reviews.llvm.org/D36130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314806
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Jakub Kuderski [Tue, 3 Oct 2017 14:51:31 +0000 (14:51 +0000)]
[Dominators] Don't use default parameter in lambda
... to make GCC buildbots happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314805
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Oliver Stannard [Tue, 3 Oct 2017 14:38:52 +0000 (14:38 +0000)]
[ARM] Use table-gen'd assembly operand diags in ARM asm parser
This switches the ARM AsmParser to use assembly operand diagnostics from
tablegen, rather than a switch statement on the ARMMatchResultTy. It
moves the existing diagnostic strings to tablegen, but adds no new ones,
so this is NFC except for one diagnostic string that had an off-by-1 error
in the hand-written switch statement.
Differential revision: https://reviews.llvm.org/D31607
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314804
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Oliver Stannard [Tue, 3 Oct 2017 14:34:57 +0000 (14:34 +0000)]
[AsmParser] Add DiagnosticString to AsmOperands in tablegen
This adds a DiagnosticString member to the AsmOperand tablegen class, so
that the diagnostic text to be used when an assembly operand is
incorrect can be stored in the tablegen description of the operand,
rather than in a separate switch statement in the AsmParser.
If DiagnosticString is used for any operands, tablegen will emit a
getMatchKindDiag function, to map from diagnostic enums to strings.
Differential revision: https://reviews.llvm.org/D31606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314803
91177308-0d34-0410-b5e6-
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Jakub Kuderski [Tue, 3 Oct 2017 14:33:41 +0000 (14:33 +0000)]
[Dominators] Add DFS number verification
Summary:
This patch teaches the DominatorTree verifier to check DFS In/Out numbers which are used to answer dominance queries.
DFS number verification is done in O(nlogn), so it shouldn't add much overhead on top of the O(n^3) sibling property verification.
This check should detect errors like the one spotted in PR34466 and related bug reports.
The patch also cleans up the DFS calculation a bit, as all constructed trees should have a single root now.
I see 2 new test failures when running check-all after this change:
```
Failing Tests (2):
Polly :: Isl/CodeGen/OpenMP/reference-argument-from-non-affine-region.ll
Polly :: Isl/CodeGen/OpenMP/two-parallel-loops-reference-outer-indvar.ll
```
which seem to happen just after `Create LLVM-IR from SCoPs` -- I XFAILed them in r314800.
Reviewers: dberlin, grosser, davide, zhendongsu, bollu
Reviewed By: dberlin
Subscribers: nandini12396, bollu, Meinersbur, brzycki, llvm-commits
Differential Revision: https://reviews.llvm.org/D38331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314801
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Tue, 3 Oct 2017 14:30:58 +0000 (14:30 +0000)]
[ARM, Asm] Use correct source location for register tokens
tryParseRegister advances the lexer, so we need to take copies of the start and
end locations of the register operand before calling it.
Previously, the caret in the diagnostic pointer to the comma after the r0
operand in the test, rather than the start of the operand.
Differential revision: https://reviews.llvm.org/D31537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314799
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Dardis [Tue, 3 Oct 2017 13:45:49 +0000 (13:45 +0000)]
[mips] Enable spilling and reloading of the dsp register set.
The dsp register class is an alias of the gpr register class, so
we have to define instructions for spilling and reloading.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D38038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314798
91177308-0d34-0410-b5e6-
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John Brawn [Tue, 3 Oct 2017 13:08:22 +0000 (13:08 +0000)]
[CGP] Make optimizeMemoryInst capable of handling multiple AddrModes
Currently optimizeMemoryInst requires that all of the AddrModes it sees are
identical. This patch makes it capable of tracking multiple AddrModes, so long
as they differ in at most one field.
This patch does nothing by itself, but later patches will make use of it to
insert or reuse phi or select instructions for the differing fields.
Differential Revision: https://reviews.llvm.org/D38278
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314795
91177308-0d34-0410-b5e6-
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John Brawn [Tue, 3 Oct 2017 13:04:15 +0000 (13:04 +0000)]
[CGP] In optimizeMemoryInst handle select similarly to phi
This lets us optimize away selects that perform the same address computation in
two different ways and is also the first step towards being able to handle
selects between two different, but compatible, address computations.
Differential Revision: https://reviews.llvm.org/D38242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314794
91177308-0d34-0410-b5e6-
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Oliver Stannard [Tue, 3 Oct 2017 12:45:18 +0000 (12:45 +0000)]
[ARM, Asm] Fix ubsan failure caused by out-of-range enum value
In this code, we use ~0U as a sentinel value for any operand class that doesn't
have a user-friendly error message, but this value isn't in range of the
MatchClassKind enum, so we need to ensure it does not get passed to isSubclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314793
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 3 Oct 2017 12:41:39 +0000 (12:41 +0000)]
[X86][SSE] Add support for decoding PACKSS/PACKUS shuffles masks with UNDEF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314792
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Tue, 3 Oct 2017 12:28:28 +0000 (12:28 +0000)]
[ARM, Asm] Remove dead code causing MSan failure.
r314779 caused ErrorInfo to be red uninitialised, but also made this code dead,
so it can just be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314791
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 3 Oct 2017 12:01:31 +0000 (12:01 +0000)]
[X86][SSE] Add support for lowering shuffles to PACKSS/PACKUS
If the upper bits of a truncation shuffle patterns have at least the minimum number of sign/zero bits on their inputs then we can safely use PACKSS/PACKUS as shuffles.
Partial fix for https://bugs.llvm.org/show_bug.cgi?id=34773
Differential Revision: https://reviews.llvm.org/D38472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314788
91177308-0d34-0410-b5e6-
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Evgeny Astigeevich [Tue, 3 Oct 2017 12:00:40 +0000 (12:00 +0000)]
[InlineCost, NFC] Extract code dealing with inbounds GEPs from visitGetElementPtr into a function
The code responsible for analysis of inbounds GEPs is extracted into a separate
function: CallAnalyzer::canFoldInboundsGEP. With the patch SROA
enabling/disabling code is localized at one place instead of spreading across
the code of CallAnalyzer::visitGetElementPtr.
Differential Revision: https://reviews.llvm.org/D38233
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314787
91177308-0d34-0410-b5e6-
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Sam Clegg [Tue, 3 Oct 2017 11:20:28 +0000 (11:20 +0000)]
[WebAssembly] MC: Support for init_array and fini_array
Differential Revision: https://reviews.llvm.org/D37757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314783
91177308-0d34-0410-b5e6-
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Sean Eveson [Tue, 3 Oct 2017 11:05:28 +0000 (11:05 +0000)]
[llvm-cov] Hide files with no coverage from the index when filtering by name
Differential Revision: https://reviews.llvm.org/D38457
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314782
91177308-0d34-0410-b5e6-
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Bjorn Pettersson [Tue, 3 Oct 2017 11:03:02 +0000 (11:03 +0000)]
[DebugInfo] Handle endianness when moving debug info for split integer values (reapplied)
Summary:
Take the target's endianness into account when splitting the
debug information in DAGTypeLegalizer::SetExpandedInteger.
This patch fixes so that, for big-endian targets, the fragment
expression corresponding to the high part of a split integer
value is placed at offset 0, in order to correctly represent
the memory address order.
I have attached a PPC32 reproducer where the resulting DWARF
pieces for a 64-bit integer were incorrectly reversed.
Original patch was reverted due to using -stop-after=isel in
the test case (but that is only working when AMDGPU target
is included in the llc build). The test case has now been
updated to use -stop-before=expand-isel-pseudos instead.
Patch by: dstenb
Reviewers: JDevlieghere, aprantl, dblaikie
Reviewed By: JDevlieghere, aprantl, dblaikie
Subscribers: nemanjai
Differential Revision: https://reviews.llvm.org/D38172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314781
91177308-0d34-0410-b5e6-
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Oliver Stannard [Tue, 3 Oct 2017 10:26:11 +0000 (10:26 +0000)]
[ARM] Use new assembler diags for ARM
This converts the ARM AsmParser to use the new assembly matcher error
reporting mechanism, which allows errors to be reported for multiple
instruction encodings when it is ambiguous which one the user intended
to use.
By itself this doesn't improve many error messages, because we don't have
diagnostic text for most operand types, but as we add that then this will allow
more of those diagnostic strings to be used when they are relevant.
Differential revision: https://reviews.llvm.org/D31530
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314779
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 3 Oct 2017 10:01:02 +0000 (10:01 +0000)]
Remove unused variable. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314778
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 3 Oct 2017 09:54:03 +0000 (09:54 +0000)]
[X86][SSE] Add support for shuffle combining from PACKSS/PACKUS
Mentioned in D38472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314777
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 3 Oct 2017 09:41:00 +0000 (09:41 +0000)]
[X86][SSE] Add support for PACKSS/PACKUS constant folding
Pulled out of D38472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314776
91177308-0d34-0410-b5e6-
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Javed Absar [Tue, 3 Oct 2017 09:35:04 +0000 (09:35 +0000)]
[MiSched] - Simplify ProcResEntry access
Reviewed by: @MatzeB
Differential Revision: https://reviews.llvm.org/D38447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314775
91177308-0d34-0410-b5e6-
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Oliver Stannard [Tue, 3 Oct 2017 09:33:12 +0000 (09:33 +0000)]
[Assembler] Report multiple near misses for invalid instructions
The current table-generated assembly instruction matcher returns a
64-bit error code when matching fails. Since multiple instruction
encodings with the same mnemonic can fail for different reasons, it uses
some heuristics to decide which message is important.
This heuristic does not work well for targets that have many encodings
with the same mnemonic but different operands, or which have different
versions of instructions controlled by subtarget features, as it is hard
to know which encoding the user was intending to use.
Instead of trying to improve the heuristic in the table-generated
matcher, this patch changes it to report a list of near-miss encodings.
This list contains an entry for each encoding with the correct mnemonic,
but with exactly one thing preventing it from being valid. This thing
could be a single invalid operand, a missing target feature or a failed
target-specific validation function.
The target-specific assembly parser can then report an error message
giving multiple options for instruction variants that the user may have
been trying to use. For example, I am working on a patch to use this for
ARM, which can give this error for an invalid instruction for ARMv6-M:
<stdin>:8:3: error: invalid instruction, multiple near-miss encodings found
adds r0, r1, #0x8
^
<stdin>:8:3: note: for one encoding: instruction requires: thumb2
adds r0, r1, #0x8
^
<stdin>:8:16: note: for one encoding: expected an integer in range [0, 7]
adds r0, r1, #0x8
^
<stdin>:8:16: note: for one encoding: expected a register in range [r0, r7]
adds r0, r1, #0x8
^
This also allows the target-specific assembly parser to apply its own
heuristics to suppress some errors. For example, the error "instruction
requires: arm-mode" is never going to be useful when targeting an
M-profile architecture (which does not have ARM mode).
This patch just adds the target-independent mechanism for doing this,
all targets still use the old mechanism. I've added a bit in the
AsmParser tablegen class to allow targets to switch to this new
mechanism. To use this, the target-specific assembly parser will have to
be modified for the change in signature of MatchInstructionImpl, and to
report errors based on the list of near-misses.
Differential revision: https://reviews.llvm.org/D27620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314774
91177308-0d34-0410-b5e6-
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Sjoerd Meijer [Tue, 3 Oct 2017 08:54:15 +0000 (08:54 +0000)]
ISel type legalization: add debug messages. NFCI.
This adds some more debug messages to the type legalizer and functions
like PromoteNode, ExpandNode, ExpandLibCall in an attempt to make
the debug messages a little bit more informative and useful.
Differential Revision: https://reviews.llvm.org/D38450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314773
91177308-0d34-0410-b5e6-
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Alex Bradbury [Tue, 3 Oct 2017 08:41:59 +0000 (08:41 +0000)]
[llvm-readobj][RISCV] Pretty-print RISCV e_flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314772
91177308-0d34-0410-b5e6-
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Alex Bradbury [Tue, 3 Oct 2017 08:03:14 +0000 (08:03 +0000)]
[RISCV] Add missed test case for r314770
Differential Revision: https://reviews.llvm.org/D38311
Patch by https://reviews.llvm.org/D38311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314771
91177308-0d34-0410-b5e6-
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Alex Bradbury [Tue, 3 Oct 2017 08:00:47 +0000 (08:00 +0000)]
[RISCV] Parse RISC-V eflags in ObjectYAML
Differential Revision: https://reviews.llvm.org/D38311
Patch by Chih-Mao Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314770
91177308-0d34-0410-b5e6-
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Hiroshi Inoue [Tue, 3 Oct 2017 07:28:58 +0000 (07:28 +0000)]
[trivial] fix format, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314769
91177308-0d34-0410-b5e6-
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Shoaib Meenai [Tue, 3 Oct 2017 06:35:55 +0000 (06:35 +0000)]
[ObjectYAML] Handle SHF_COMPRESSED
This was previously being silently dropped by obj2yaml and caused
parsing errors with yaml2obj.
Differential Revision: https://reviews.llvm.org/D38490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314768
91177308-0d34-0410-b5e6-
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Martin Storsjo [Tue, 3 Oct 2017 06:29:58 +0000 (06:29 +0000)]
[X86] Provide the LSDA pointer with RIP relative addressing if necessary
This makes sure the LSDA pointer isn't truncated to 32 bit.
Make LowerINTRINSIC_WO_CHAIN a member function instead of a static
function, so that it can use the getGlobalWrapperKind method.
This solves the second half of the issues mentioned in PR34720.
Differential Revision: https://reviews.llvm.org/D38343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314767
91177308-0d34-0410-b5e6-
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Mikael Holmen [Tue, 3 Oct 2017 06:03:49 +0000 (06:03 +0000)]
[Lint] Avoid failed assertion by fetching the proper pointer type
Summary:
When checking if a constant expression is a noop cast we fetched the
IntPtrType by doing DL->getIntPtrType(V->getType())). However, there can
be cases where V doesn't return a pointer, and then getIntPtrType()
triggers an assertion.
Now we pass DataLayout to isNoopCast so the method itself can determine
what the IntPtrType is.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D37894
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314763
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 3 Oct 2017 05:31:07 +0000 (05:31 +0000)]
[InstCombine] Change a bunch of methods to take APInts by reference instead of pointer.
This allows us to remove a bunch of dereferences and only have a few dereferences at the call sites.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314762
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 3 Oct 2017 04:55:04 +0000 (04:55 +0000)]
[InstCombine] Replace an equality compare of two APInt pointers with a compare of the APInts themselves.
Apparently this works by virtue of the fact that the pointers are pointers to the APInts stored inside of the ConstantInt objects. But I really don't think we should be relying on that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314761
91177308-0d34-0410-b5e6-
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Quentin Colombet [Tue, 3 Oct 2017 04:53:56 +0000 (04:53 +0000)]
[Legalizer] Add support for G_OR NarrowScalar.
Legalize bitwise OR:
A = BinOp<Ty> B, C
into:
B1, ..., BN = G_UNMERGE_VALUES B
C1, ..., CN = G_UNMERGE_VALUES C
A1 = BinOp<Ty/N> B1, C2
...
AN = BinOp<Ty/N> BN, CN
A = G_MERGE_VALUES A1, ..., AN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314760
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 3 Oct 2017 03:47:34 +0000 (03:47 +0000)]
[X86] Add AVX512 check lines to the cost model truncate test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314758
91177308-0d34-0410-b5e6-
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Rui Ueyama [Tue, 3 Oct 2017 03:09:05 +0000 (03:09 +0000)]
Rewrite a function so that it doesn't use pointers to pointers. NFC.
Previous code was a bit puzzling because of its use of pointers.
In this patch, we pass a vector and its offsets, instead of pointers to
vector elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314756
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Tue, 3 Oct 2017 00:44:21 +0000 (00:44 +0000)]
LTO: Improve error reporting when adding a cache entry.
Move error handling code next to the code that returns the error,
and change the error message in order to distinguish it from a similar
error message elsewhere in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314745
91177308-0d34-0410-b5e6-
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Daniel Berlin [Tue, 3 Oct 2017 00:26:21 +0000 (00:26 +0000)]
SparseSolver: Rename getOrInitValueState to getValueState, matching what SCCP calls it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314744
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 3 Oct 2017 00:06:41 +0000 (00:06 +0000)]
AMDGPU: Remove global isGCN predicates
These are problematic because they apply to everything,
and can easily clobber whatever more specific predicate
you are trying to add to a function.
Currently instructions use SubtargetPredicate/PredicateControl
to apply this to patterns applied to an instruction definition,
but not to free standing Pats. Add a wrapper around Pat
so the special PredicateControls requirements can be appended
to the final predicate list like how Mips does it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314742
91177308-0d34-0410-b5e6-
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Haicheng Wu [Mon, 2 Oct 2017 23:43:52 +0000 (23:43 +0000)]
[InstSimplify] teach SimplifySelectInst() to fold more vector selects
Call ConstantFoldSelectInstruction() to fold cases like below
select <2 x i1><i1 true, i1 false>, <2 x i8> <i8 0, i8 1>, <2 x i8> <i8 2, i8 3>
All operands are constants and the condition has mixed true and false conditions.
Differential Revision: https://reviews.llvm.org/D38369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314741
91177308-0d34-0410-b5e6-
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Davide Italiano [Mon, 2 Oct 2017 23:39:20 +0000 (23:39 +0000)]
[PassManager] Retire cl::opt that have been set for a while. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314740
91177308-0d34-0410-b5e6-
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Tim Shen [Mon, 2 Oct 2017 23:20:06 +0000 (23:20 +0000)]
[PowerPC] Revert r314666.
See https://reviews.llvm.org/D38172.
I tried to XFAIL it, but sometimes XPASS triggers the bot. Simply
revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314739
91177308-0d34-0410-b5e6-
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Daniel Berlin [Mon, 2 Oct 2017 22:49:49 +0000 (22:49 +0000)]
Template the sparse propagation solver instead of using void pointers
Summary:
This avoids using void * as the type of the lattice value and ugly casts needed to make that happen.
(If folks want to use references, etc, they can use a reference_wrapper).
Reviewers: davide, mssimpso
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D38476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314734
91177308-0d34-0410-b5e6-
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Tim Shen [Mon, 2 Oct 2017 22:40:32 +0000 (22:40 +0000)]
[PowerPC] Temporarily disable the test introduced by r314666
See https://reviews.llvm.org/D38172 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314732
91177308-0d34-0410-b5e6-
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Geoff Berry [Mon, 2 Oct 2017 22:01:37 +0000 (22:01 +0000)]
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
Issues addressed since original review:
- Avoid bug in regalloc greedy/machine verifier when forwarding to use
in an instruction that re-defines the same virtual register.
- Fixed bug when forwarding to use in EarlyClobber instruction slot.
- Fixed incorrect forwarding to register definitions that showed up in
explicit_uses() iterator (e.g. in INLINEASM).
- Moved removal of dead instructions found by
LiveIntervals::shrinkToUses() outside of loop iterating over
instructions to avoid instructions being deleted while pointed to by
iterator.
- Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907.
- The pass no longer forwards COPYs to physical register uses, since
doing so can break code that implicitly relies on the physical
register number of the use.
- The pass no longer forwards COPYs to undef uses, since doing so
can break the machine verifier by creating LiveRanges that don't
end on a use (since the undef operand is not considered a use).
[MachineCopyPropagation] Extend pass to do COPY source forwarding
This change extends MachineCopyPropagation to do COPY source forwarding.
This change also extends the MachineCopyPropagation pass to be able to
be run during register allocation, after physical registers have been
assigned, but before the virtual registers have been re-written, which
allows it to remove virtual register COPY LiveIntervals that become dead
through the forwarding of all of their uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314729
91177308-0d34-0410-b5e6-
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Michael Liao [Mon, 2 Oct 2017 21:54:38 +0000 (21:54 +0000)]
Remove trailing whitespace to trigger re-cmaking
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314728
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 2 Oct 2017 21:46:58 +0000 (21:46 +0000)]
[X86] Run dos2unix on two disassembler tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314727
91177308-0d34-0410-b5e6-
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Amjad Aboud [Mon, 2 Oct 2017 21:46:37 +0000 (21:46 +0000)]
[X86][NFC] Add X86CmovConverterPass to the pass registry.
Differential Revision: https://reviews.llvm.org/D38355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314726
91177308-0d34-0410-b5e6-
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Adrian Prantl [Mon, 2 Oct 2017 21:21:09 +0000 (21:21 +0000)]
llvm-dwarfdump: support the --ignore-case option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314723
91177308-0d34-0410-b5e6-
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Michael Liao [Mon, 2 Oct 2017 21:00:52 +0000 (21:00 +0000)]
Remove dead file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314720
91177308-0d34-0410-b5e6-
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Konstantin Zhuravlyov [Mon, 2 Oct 2017 20:49:58 +0000 (20:49 +0000)]
Add ELFOSABI_FIRST_ARCH, ELFOSABI_LAST_ARCH and start using those in llvm-readobj
Differential Revision: https://reviews.llvm.org/D38418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314717
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Matt Arsenault [Mon, 2 Oct 2017 20:31:18 +0000 (20:31 +0000)]
AMDGPU: Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314715
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Matt Arsenault [Mon, 2 Oct 2017 20:31:16 +0000 (20:31 +0000)]
AMDGPU: Fix potentially incorrectly matching check lines
These check lines are supposed to make sure the new d16
load instructions aren't used, but the expected instruction
name is a prefix of the incorrect instruction name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314714
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Sanjay Patel [Mon, 2 Oct 2017 20:16:59 +0000 (20:16 +0000)]
[InstCombine] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314712
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Sanjay Patel [Mon, 2 Oct 2017 20:07:15 +0000 (20:07 +0000)]
[InstCombine] add icmp (shr X, Y), 0 test; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314710
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Hans Wennborg [Mon, 2 Oct 2017 19:48:28 +0000 (19:48 +0000)]
Fix two header comments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314709
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Walter Lee [Mon, 2 Oct 2017 18:50:48 +0000 (18:50 +0000)]
Add support for Myriad ma2x8x series of CPUs
Summary: Also add support for some older Myriad CPUs that were missing.
Reviewers: jyknight
Subscribers: fedor.sergeev
Differential Revision: https://reviews.llvm.org/D37552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314705
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Adrian Prantl [Mon, 2 Oct 2017 18:31:29 +0000 (18:31 +0000)]
Move the stripping of invalid debug info from the Verifier to AutoUpgrade.
This came out of a recent discussion on llvm-dev
(https://reviews.llvm.org/D38042). Currently the Verifier will strip
the debug info metadata from a module if it finds the dbeug info to be
malformed. This feature is very valuable since it allows us to improve
the Verifier by making it stricter without breaking bcompatibility,
but arguable the Verifier pass should not be modifying the IR. This
patch moves the stripping of broken debug info into AutoUpgrade
(UpgradeDebugInfo to be precise), which is a much better location for
this since the stripping of malformed (i.e., produced by older, buggy
versions of Clang) is a (harsh) form of AutoUpgrade.
This change is mostly NFC in nature, the one big difference is the
behavior when LLVM module passes are introducing malformed debug
info. Prior to this patch, a NoAsserts build would have printed a
warning and stripped the debug info, after this patch the Verifier
will report a fatal error. I believe this behavior is actually more
desirable anyway.
Differential Revision: https://reviews.llvm.org/D38184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314699
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