OSDN Git Service
Reid Kleckner [Thu, 10 Apr 2014 00:52:14 +0000 (00:52 +0000)]
Revert "For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported."
It doesn't build with MSVC 2012, because MSVC doesn't allow union
members that have non-trivial default constructors. This change added
'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor
non-trivial.
This reverts commit r205930.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205944
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Jim Grosbach [Thu, 10 Apr 2014 00:27:45 +0000 (00:27 +0000)]
Fix to support properly cleaning up failed address sinking against constants
As it turns out the source of the sunkaddr can be a constant, in which case
there is not an instruction to delete, causing the cleanup code introduced in
r204833 to crash. This patch adds a dynamic check to ensure the deleted value is
in fact an instruction and not a constant.
Patch by Louis Gerbarg <lgg@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205941
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Jim Grosbach [Thu, 10 Apr 2014 00:27:43 +0000 (00:27 +0000)]
X86: Tighten up test.
llc CPU autodection bites again. Speculative fix for bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205940
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Jim Grosbach [Wed, 9 Apr 2014 23:39:25 +0000 (23:39 +0000)]
Add support for load folding of avx1 logical instructions
AVX supports logical operations using an operand from memory. Unfortunately
because integer operations were not added until AVX2 the AVX1 logical
operation's types were preventing the isel from folding the loads. In a limited
number of cases the peephole optimizer would fold the loads, but most were
missed. This patch adds explicit patterns with appropriate casts in order for
these loads to be folded.
The included test cases run on reduced examples and disable the peephole
optimizer to ensure the folds are being pattern matched.
Patch by Louis Gerbarg <lgg@apple.com>
rdar://
16355124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205938
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Jim Grosbach [Wed, 9 Apr 2014 23:28:11 +0000 (23:28 +0000)]
SelectionDAG: Don't constant fold target-specific nodes.
FoldConstantArithmetic() only knows how to deal with a few target independent
ISD opcodes. Bail early if it sees a target-specific ISD node. These node do
funny things with operand types which may break the assumptions of the code
that follows, and there's no actual folding that can be done anyway. For example,
non-constant 256 bit vector shifts on X86 have a shift-amount operand that's a
128-bit v4i32 vector regardless of what the first operand type is and that breaks
the assumption that the operand types must match.
rdar://
16530923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205937
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Kevin Enderby [Wed, 9 Apr 2014 21:32:59 +0000 (21:32 +0000)]
For the ARM integrated assembler add checking of the
alignments on vld/vst instructions. And report errors for
alignments that are not supported.
While this is a large diff and an big test case, the changes
are very straight forward. But pretty much had to touch
all vld/vst instructions changing the addrmode to one of the
new ones that where added will do the proper checking for
the specific instruction.
rdar://
11312406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205930
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Chad Rosier [Wed, 9 Apr 2014 20:51:21 +0000 (20:51 +0000)]
[AArch64] Implement the isZExtFree APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205926
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Chad Rosier [Wed, 9 Apr 2014 20:43:40 +0000 (20:43 +0000)]
[AArch64] Implement the isTruncateFree API.
In AArch64 i64 to i32 truncate operation is a subregister access.
This allows more opportunities for LSR optmization to eliminate
variables of different types (i32 and i64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205925
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Quentin Colombet [Wed, 9 Apr 2014 20:03:05 +0000 (20:03 +0000)]
[DAGCombiner] DAG combine does not know how to combine indexed loads with
sign/zero/any extensions. However a few places were not checking properly the
property of the load and were turning an indexed load into a regular extended
load. Therefore the indexed value was lost during the process and this was
triggering an assertion.
<rdar://problem/
16389332>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205923
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Bob Wilson [Wed, 9 Apr 2014 18:34:45 +0000 (18:34 +0000)]
Simple fix for build failures resulting from r205867.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205918
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David Majnemer [Wed, 9 Apr 2014 17:04:27 +0000 (17:04 +0000)]
Revert "Revert "YAMLIO: Encode ambiguous hex strings explicitly""
Don't quote octal compatible strings if they are only two wide, they
aren't ambiguous.
This reverts commit r205857 which reverted r205857.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205914
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David Majnemer [Wed, 9 Apr 2014 16:38:15 +0000 (16:38 +0000)]
obj2yaml: Don't crash if the characteristics field is zero
obj2yaml would fail when seeing a Weak External auxiliary record with a
characteristics field holding zero instead of one of
IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY, IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY,
or IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205911
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Justin Holewinski [Wed, 9 Apr 2014 15:39:15 +0000 (15:39 +0000)]
[NVPTX] Add preliminary intrinsics and codegen support for textures/surfaces
This commit adds intrinsics and codegen support for the surface read/write and texture read instructions that take an explicit sampler parameter. Codegen operates on image handles at the PTX level, but falls back to direct replacement of handles with kernel arguments if image handles are not enabled. Note that image handles are explicitly disabled for all target architectures in this change (to be enabled later).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205907
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Justin Holewinski [Wed, 9 Apr 2014 15:39:11 +0000 (15:39 +0000)]
[NVPTX] Add support for addrspacecast in global variable initializers, including emitting generic() when casting to address space 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205906
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Justin Holewinski [Wed, 9 Apr 2014 15:38:52 +0000 (15:38 +0000)]
[NVPTX] Add query support for read-write images and managed variables
This also fixes a bug in the annotation cache where the cache will not be cleared between modules if multiple modules are compiled in the same process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205905
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Alp Toker [Wed, 9 Apr 2014 14:47:27 +0000 (14:47 +0000)]
Fix some doc and comment typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205899
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Bradley Smith [Wed, 9 Apr 2014 14:44:58 +0000 (14:44 +0000)]
[ARM64] Change SYS without a register to an alias to make disassembling more consistant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205898
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Bradley Smith [Wed, 9 Apr 2014 14:44:54 +0000 (14:44 +0000)]
[ARM64] Correctly disassemble ISB operand as ISB not DBarrier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205897
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Bradley Smith [Wed, 9 Apr 2014 14:44:49 +0000 (14:44 +0000)]
[ARM64] Properly support both apple and standard syntax for FMOV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205896
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Bradley Smith [Wed, 9 Apr 2014 14:44:44 +0000 (14:44 +0000)]
[ARM64] Flag setting logical/add/sub immediate instructions don't use SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205895
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Bradley Smith [Wed, 9 Apr 2014 14:44:39 +0000 (14:44 +0000)]
[ARM64] Conditional branches must always print their condition code, even AL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205894
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Bradley Smith [Wed, 9 Apr 2014 14:44:36 +0000 (14:44 +0000)]
[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893
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Bradley Smith [Wed, 9 Apr 2014 14:44:31 +0000 (14:44 +0000)]
[ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205892
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Bradley Smith [Wed, 9 Apr 2014 14:44:26 +0000 (14:44 +0000)]
[ARM64] Add missing shifted register MVN alias to ORN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205891
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Bradley Smith [Wed, 9 Apr 2014 14:44:22 +0000 (14:44 +0000)]
[ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205890
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Bradley Smith [Wed, 9 Apr 2014 14:44:18 +0000 (14:44 +0000)]
[ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205889
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Bradley Smith [Wed, 9 Apr 2014 14:44:12 +0000 (14:44 +0000)]
[ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205888
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Bradley Smith [Wed, 9 Apr 2014 14:44:07 +0000 (14:44 +0000)]
[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887
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Bradley Smith [Wed, 9 Apr 2014 14:44:03 +0000 (14:44 +0000)]
[ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205886
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Bradley Smith [Wed, 9 Apr 2014 14:43:59 +0000 (14:43 +0000)]
[ARM64] Rename LR to the UAL-compliant 'X30'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205885
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Bradley Smith [Wed, 9 Apr 2014 14:43:50 +0000 (14:43 +0000)]
[ARM64] Rename FP to the UAL-compliant 'X29'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205884
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Bradley Smith [Wed, 9 Apr 2014 14:43:40 +0000 (14:43 +0000)]
[ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883
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Bradley Smith [Wed, 9 Apr 2014 14:43:35 +0000 (14:43 +0000)]
[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882
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Bradley Smith [Wed, 9 Apr 2014 14:43:31 +0000 (14:43 +0000)]
[ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205881
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Bradley Smith [Wed, 9 Apr 2014 14:43:27 +0000 (14:43 +0000)]
[ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205880
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Bradley Smith [Wed, 9 Apr 2014 14:43:24 +0000 (14:43 +0000)]
[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205879
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Bradley Smith [Wed, 9 Apr 2014 14:43:20 +0000 (14:43 +0000)]
[ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205878
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Bradley Smith [Wed, 9 Apr 2014 14:43:15 +0000 (14:43 +0000)]
[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205877
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Bradley Smith [Wed, 9 Apr 2014 14:43:11 +0000 (14:43 +0000)]
[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205876
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Bradley Smith [Wed, 9 Apr 2014 14:43:06 +0000 (14:43 +0000)]
[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875
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Bradley Smith [Wed, 9 Apr 2014 14:43:01 +0000 (14:43 +0000)]
[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874
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Bradley Smith [Wed, 9 Apr 2014 14:42:56 +0000 (14:42 +0000)]
[ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205873
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Bradley Smith [Wed, 9 Apr 2014 14:42:53 +0000 (14:42 +0000)]
[ARM64] Remove PrefetchOp and use ARM64PRFM instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205872
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Bradley Smith [Wed, 9 Apr 2014 14:42:49 +0000 (14:42 +0000)]
[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205871
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Bradley Smith [Wed, 9 Apr 2014 14:42:45 +0000 (14:42 +0000)]
[ARM64] Remove ARM64SYS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205870
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Bradley Smith [Wed, 9 Apr 2014 14:42:42 +0000 (14:42 +0000)]
[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205869
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Bradley Smith [Wed, 9 Apr 2014 14:42:36 +0000 (14:42 +0000)]
[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868
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Bradley Smith [Wed, 9 Apr 2014 14:42:27 +0000 (14:42 +0000)]
[ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205867
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Bradley Smith [Wed, 9 Apr 2014 14:42:16 +0000 (14:42 +0000)]
[ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205866
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Bradley Smith [Wed, 9 Apr 2014 14:42:11 +0000 (14:42 +0000)]
[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865
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Bradley Smith [Wed, 9 Apr 2014 14:42:07 +0000 (14:42 +0000)]
[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205864
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Bradley Smith [Wed, 9 Apr 2014 14:42:01 +0000 (14:42 +0000)]
[ARM64] Add missing 1Q -> 1q vector kind alias
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205863
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Bradley Smith [Wed, 9 Apr 2014 14:41:58 +0000 (14:41 +0000)]
[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205862
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Bradley Smith [Wed, 9 Apr 2014 14:41:53 +0000 (14:41 +0000)]
[ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205861
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Bradley Smith [Wed, 9 Apr 2014 14:41:49 +0000 (14:41 +0000)]
[ARM64] STRHro and STRBro were not being decoded at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205860
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Bradley Smith [Wed, 9 Apr 2014 14:41:45 +0000 (14:41 +0000)]
[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205859
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Bradley Smith [Wed, 9 Apr 2014 14:41:38 +0000 (14:41 +0000)]
[ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205858
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Filipe Cabecinhas [Wed, 9 Apr 2014 14:35:17 +0000 (14:35 +0000)]
Revert "YAMLIO: Encode ambiguous hex strings explicitly"
This reverts commit r205839.
It broke several tests in lld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205857
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Arnold Schwaighofer [Wed, 9 Apr 2014 14:20:47 +0000 (14:20 +0000)]
SLPVectorizer: Only vectorize intrinsics whose operands are widened equally
The vectorizer only knows how to vectorize intrinics by widening all operands by
the same factor.
Patch by Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205855
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Elena Demikhovsky [Wed, 9 Apr 2014 12:37:50 +0000 (12:37 +0000)]
AVX-512: insert element to mask vector; store i1 data
Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205850
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Viktor Kutuzov [Wed, 9 Apr 2014 11:43:34 +0000 (11:43 +0000)]
Add support for building LLVM on FreeBSD 9.2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205847
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Daniel Sanders [Wed, 9 Apr 2014 09:56:43 +0000 (09:56 +0000)]
Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math
Summary:
They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies).
nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008.
Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly.
Reviewers: matheusalmeida
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205844
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David Majnemer [Wed, 9 Apr 2014 07:56:27 +0000 (07:56 +0000)]
YAMLIO: Encode ambiguous hex strings explicitly
YAMLIO would turn a BinaryRef into the string
0000000004000000.
However, the leading zero causes parsers to interpret it as being an
octal number instead of a hexadecimal one.
Instead, escape such strings as needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205839
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Tobias Grosser [Wed, 9 Apr 2014 07:53:49 +0000 (07:53 +0000)]
Delinearize: Extend informationin -analyze output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205838
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Matt Arsenault [Wed, 9 Apr 2014 07:16:16 +0000 (07:16 +0000)]
R600/SI: Match not instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205837
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Tim Northover [Wed, 9 Apr 2014 07:07:02 +0000 (07:07 +0000)]
ARM64: scalarize v1i64 mul operation
This is the second part of fixing PR19367.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205836
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Tim Northover [Wed, 9 Apr 2014 06:55:39 +0000 (06:55 +0000)]
ARM64: add pattern for <1 x i64> custom not node.
This should fix PR19367.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205835
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Saleem Abdulrasool [Wed, 9 Apr 2014 06:18:28 +0000 (06:18 +0000)]
Object: add type names for ARM/COFF relocations
Add type name mappings for the ARM COFF relocations. This allows for objdump to
provide a more useful description of relocations in disassembly inline form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205834
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Saleem Abdulrasool [Wed, 9 Apr 2014 06:18:26 +0000 (06:18 +0000)]
ARM MC: 80 column
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205833
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Saleem Abdulrasool [Wed, 9 Apr 2014 06:18:23 +0000 (06:18 +0000)]
ARM MC: sort source files in CMakeLists
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205832
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Craig Topper [Wed, 9 Apr 2014 06:08:46 +0000 (06:08 +0000)]
[C++11] More 'nullptr' conversion or in some cases just using a boolean check instead of comparing to nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205831
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Craig Topper [Wed, 9 Apr 2014 04:50:04 +0000 (04:50 +0000)]
[C++11] Make use of 'nullptr' in TableGen library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205830
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Craig Topper [Wed, 9 Apr 2014 04:20:00 +0000 (04:20 +0000)]
[C++11] Replace some comparisons with 'nullptr' with simple boolean checks to reduce verbosity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205829
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David Majnemer [Tue, 8 Apr 2014 22:33:40 +0000 (22:33 +0000)]
WinCOFF: Emit common symbols as specified in the COFF spec
Summary:
Local common symbols were properly inserted into the .bss section.
However, putting external common symbols in the .bss section would give
them a strong definition.
Instead, encode them as undefined, external symbols who's symbol value
is equivalent to their size.
Reviewers: Bigcheese, rafael, rnk
CC: llvm-commits
Differential Revision: http://reviews.llvm.org/D3324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205811
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Matt Arsenault [Tue, 8 Apr 2014 21:40:37 +0000 (21:40 +0000)]
Bug 19348: Check for legal ExtLoad operation before folding
(aext (zextload x)) -> (aext (truncate (*extload x)))
Patch by Stanislav Mekhanoshin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205805
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Sebastian Pop [Tue, 8 Apr 2014 21:21:13 +0000 (21:21 +0000)]
divide by the result of the gcd
used to fail with 'Step should divide Start with no remainder.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205802
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Sebastian Pop [Tue, 8 Apr 2014 21:21:10 +0000 (21:21 +0000)]
handle special cases when findGCD returns 1
used to fail with 'Step should divide Start with no remainder.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205801
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Sebastian Pop [Tue, 8 Apr 2014 21:21:05 +0000 (21:21 +0000)]
in findGCD of multiply expr return the gcd
we used to return 1 instead of the gcd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205800
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Sean Silva [Tue, 8 Apr 2014 21:12:56 +0000 (21:12 +0000)]
[docs] VCS contains a record of authorship
No need to explicitly mention the author in the document.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205793
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Sean Silva [Tue, 8 Apr 2014 21:06:22 +0000 (21:06 +0000)]
[docs] Fix up some links to the preferred style.
:doc:`...` and :ref:`...` links help Sphinx keep track the dependencies
between documents and ensure that they are not pointing to nowhere.
Raw HTML links work just fine and are easier for people less familiar
with reST/Sphinx. They are easy to change over to the :doc:/:ref: style
after the fact so this is not a problem.
This commit doesn't fix all of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205792
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Juergen Ributzka [Tue, 8 Apr 2014 20:39:59 +0000 (20:39 +0000)]
[Constant Hoisting][ARM64] Enable constant hoisting for ARM64.
This implements the target-hooks for ARM64 to enable constant hoisting.
This fixes <rdar://problem/
14774662> and <rdar://problem/
16381500>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205791
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Duncan P. N. Exon Smith [Tue, 8 Apr 2014 19:18:56 +0000 (19:18 +0000)]
RegAlloc: Account for a variable entry block frequency
Until r197284, the entry frequency was constant -- i.e., set to 2^14.
Although current ToT still has a constant entry frequency, since r197284
that has been an implementation detail (which is soon going to change).
- r204690 made the wrong assumption for the CSRCost metric. Adjust
callee-saved register cost based on entry frequency.
- r185393 made the wrong assumption (although it was valid at the
time). Update SpillPlacement.cpp::Threshold to be relative to the
entry frequency.
Since ToT still has 2^14 entry frequency, this should have no observable
functionality change.
<rdar://problem/
14292693>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205789
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Hal Finkel [Tue, 8 Apr 2014 19:00:27 +0000 (19:00 +0000)]
[PowerPC] Don't return false from PPC::isVSLDOIShuffleMask
PPC::isVSLDOIShuffleMask should return -1, not false, when the shuffle
predicate should be false.
Noticed by inspection; no test case (yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205787
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Kevin Enderby [Tue, 8 Apr 2014 18:00:52 +0000 (18:00 +0000)]
Fix the ARM VLD3 (single 3-element structure to all lanes)
size 16 double-spaced registers instruction printing.
This:
vld3.16 {d0[], d2[], d4[]}, [r4]!
was being printed as:
vld3.16 {d0[], d1[], d2[]}, [r4]!
rdar://
16531387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205779
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Duncan P. N. Exon Smith [Tue, 8 Apr 2014 17:07:44 +0000 (17:07 +0000)]
Verifier: Give the right message for bad atomic loads
Talk about load (not store) on an invalid atomic load.
<rdar://problem/
16287567>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205777
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Diego Novillo [Tue, 8 Apr 2014 16:42:38 +0000 (16:42 +0000)]
Add -pass-remarks flag to 'opt'.
Summary:
This adds support in 'opt' to filter pass remarks emitted by
optimization passes. A new flag -pass-remarks specifies which
passes should emit a diagnostic when LLVMContext::emitOptimizationRemark
is invoked.
This will allow the front end to simply pass along the regular
expression from its own -Rpass flag when launching the backend.
Depends on D3227.
Reviewers: qcolombet
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D3291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205775
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Diego Novillo [Tue, 8 Apr 2014 16:42:34 +0000 (16:42 +0000)]
Add support for optimization reports.
Summary:
This patch adds backend support for -Rpass=, which indicates the name
of the optimization pass that should emit remarks stating when it
made a transformation to the code.
Pass names are taken from their DEBUG_NAME definitions.
When emitting an optimization report diagnostic, the lack of debug
information causes the diagnostic to use "<unknown>:0:0" as the
location string.
This is the back end counterpart for
http://llvm-reviews.chandlerc.com/D3226
Reviewers: qcolombet
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D3227
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205774
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NAKAMURA Takumi [Tue, 8 Apr 2014 15:28:50 +0000 (15:28 +0000)]
X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused DW_LNE_set_address was misemitted on x64.
FIXME: I haven't investigate whether CalleeSaveStackSlotSize should be 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205772
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Tim Northover [Tue, 8 Apr 2014 12:23:51 +0000 (12:23 +0000)]
ARM64: fix fmsub patterns which assumed accum operand was first
Confusingly, the NEON fmla instructions put the accumulator first but the
scalar versions put it at the end (like the fma lib function & LLVM's
intrinsic).
This should fix PR19345, assuming there's only one issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205758
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Richard Smith [Tue, 8 Apr 2014 10:47:04 +0000 (10:47 +0000)]
The LLVM C API shouldn't be including a file from the C++ API. Especially not a
file that it doesn't use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205755
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Elena Demikhovsky [Tue, 8 Apr 2014 07:24:02 +0000 (07:24 +0000)]
AVX-512: Added fp_to_uint and uint_to_fp patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205754
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Andrew Trick [Tue, 8 Apr 2014 03:40:34 +0000 (03:40 +0000)]
Fix a (legacy) PassManager crash that occurs when a ModulePass
indirectly requires a function analysis.
This bug was reported by Jason Kim. He included a test case here:
http://reviews.llvm.org/D3312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205753
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David Majnemer [Tue, 8 Apr 2014 02:15:13 +0000 (02:15 +0000)]
X86: Split the relocation selection up
Before, we would have conditional operators where one side of the
operator would be of type RelocationTypeAMD64 and the other is of type
RelocationTypeI386. GCC would noisly warn with -Wenum-compare
diagnostic.
Instead, refactor the code so it is more like the X86 ELF object writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205752
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Jim Grosbach [Mon, 7 Apr 2014 23:47:23 +0000 (23:47 +0000)]
Tidy up comments a bit.
Punctuation, grammar, formatting, etc..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205749
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Jim Grosbach [Mon, 7 Apr 2014 23:47:21 +0000 (23:47 +0000)]
ARM64: Range based for loop in ARM64PromoteConstant pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205748
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Jim Grosbach [Mon, 7 Apr 2014 23:14:38 +0000 (23:14 +0000)]
ARM64: Clean up file header comment a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205747
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David Majnemer [Mon, 7 Apr 2014 23:12:20 +0000 (23:12 +0000)]
obj2yaml: Use the correct relocation type for different machine types
The IO normalizer would essentially lump I386 and AMD64 relocations
together. Relocation types with the same numeric value would then get
mapped in appropriately.
For example:
IMAGE_REL_AMD64_ADDR64 and IMAGE_REL_I386_DIR16 both have a numeric
value of one. We would see IMAGE_REL_I386_DIR16 in obj2yaml conversions
of object files with a machine type of IMAGE_FILE_MACHINE_AMD64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205746
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Sean Silva [Mon, 7 Apr 2014 22:46:40 +0000 (22:46 +0000)]
[docs] Fix some links
The TableGen docs have changed structure
Patch by Tay Ray Chuan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205744
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Sean Silva [Mon, 7 Apr 2014 22:42:53 +0000 (22:42 +0000)]
[docs] Update link title
docs/TableGen/ is not really just "fundamentals" anymore, but rather
more of a portal for all things TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205743
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Sean Silva [Mon, 7 Apr 2014 22:29:53 +0000 (22:29 +0000)]
[docs] Fix some Sphinx warnings that have crept in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205742
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