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Timothy Arceri [Fri, 16 Nov 2018 03:57:11 +0000 (14:57 +1100)]
nir: add a new nir_cf_list_clone_and_reinsert() helper
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Tue, 20 Nov 2018 00:35:37 +0000 (11:35 +1100)]
nir: clarify some nit_loop_info member names
Following commits will introduce additional fields such as
guessed_trip_count. Renaming these will help avoid confusion
as our unrolling feature set grows.
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Thu, 15 Nov 2018 09:40:08 +0000 (20:40 +1100)]
nir: small tidy ups for nir_loop_analyze()
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Fri, 7 Dec 2018 21:01:07 +0000 (13:01 -0800)]
i965: Flip arguments to load_register_reg helpers.
load_register_imm and load_register_mem take the destination as the
first argument, so I'd like load_register_reg to do the same the sake
of consistency. Otherwise, reading sequences of mixed LRI/LRM/LRR is
needlessly confusing.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Sat, 8 Dec 2018 02:41:19 +0000 (18:41 -0800)]
i965: Delete dead brw_meta_resolve_color prototype.
Dead since commit
09e041d61d367ff3a9e8492521606090050255d4 (May 2016).
Karol Herbst [Fri, 7 Dec 2018 08:44:55 +0000 (09:44 +0100)]
nv50/ir: fix use-after-free in ConstantFolding::visit
opnd() might delete the passed in instruction, but it's used through
i->srcExists() later in visit
v2: use continue instead return
v3: use brackets for the outer if/else chain
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Karol Herbst [Fri, 7 Dec 2018 19:10:50 +0000 (20:10 +0100)]
nouveau: use atomic operations for driver statistics
multiple threads can write to those at the same time
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Karol Herbst [Fri, 7 Dec 2018 08:47:05 +0000 (09:47 +0100)]
nv50/ir: initialize relDegree staticly
this race condition is pretty harmless, but also pretty trivial to fix
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Eric Anholt [Sat, 8 Dec 2018 00:51:12 +0000 (16:51 -0800)]
shader-packing
Eric Anholt [Sat, 8 Dec 2018 00:49:41 +0000 (16:49 -0800)]
tfu
Eric Anholt [Fri, 7 Dec 2018 18:34:40 +0000 (10:34 -0800)]
v3d: Fix a leak of the disassembled instruction string during debug dumps.
Fixes:
ade416d02369 ("broadcom: Add VC5 NIR compiler.")
Eric Anholt [Fri, 7 Dec 2018 18:31:27 +0000 (10:31 -0800)]
vc4: Fix a leak of the transfer helper on screen destroy.
Fixes:
d009463a6549 ("vc4: Switch to using u_transfer_helper for MSAA maps.")
Eric Anholt [Fri, 7 Dec 2018 18:30:09 +0000 (10:30 -0800)]
v3d: Fix a leak of the transfer helper on screen destroy.
Fixes:
7a30517cce8f ("broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.")
Eric Anholt [Tue, 4 Dec 2018 23:03:15 +0000 (15:03 -0800)]
v3d: Add VIR dumping of TMU config p0/p1.
I had a bit of it for V3D 3.x, but didn't update it for 4.x.
Eric Anholt [Tue, 4 Dec 2018 23:01:58 +0000 (15:01 -0800)]
v3d: Simplify VIR uniform dumping using a temporary.
Eric Anholt [Mon, 3 Dec 2018 16:52:36 +0000 (08:52 -0800)]
v3d: Garbage collect unused uniforms code.
Eric Anholt [Tue, 4 Dec 2018 22:25:22 +0000 (14:25 -0800)]
v3d: Split most of TEXTURE_SHADER_STATE setup out of sampler views.
For shader image load/store, we want most of this logic to be shared.
Eric Anholt [Tue, 4 Dec 2018 22:32:27 +0000 (14:32 -0800)]
v3d: Avoid confusing auto-indenting in TEXTURE_SHADER_STATE packing
Having "v3dx_pack() {" under each #if branch would confuse emacs's
indenter.
Eric Anholt [Tue, 4 Dec 2018 22:18:45 +0000 (14:18 -0800)]
v3d: Fix handling of texture first_layer offsets for 3D textures.
I think this bug predated adding v3d_layer_offset(). Noticed during an
unrelated refactor.
Eric Anholt [Mon, 3 Dec 2018 16:51:29 +0000 (08:51 -0800)]
v3d: Return the right gl_SampleMaskIn[] value.
It's supposed to be the dispatched sample mask for this pixel, not the GL
state's sample mask.
Eric Anholt [Mon, 3 Dec 2018 16:43:46 +0000 (08:43 -0800)]
v3d: Fix a comment typo
Eric Anholt [Mon, 3 Dec 2018 16:35:50 +0000 (08:35 -0800)]
v3d: Convert to using nir_src_as_uint() from const_value derefs.
Follows
16870de8a0aa ("nir: Use nir_src_is_const and nir_src_as_* in core
code") to clean up v3d.
Eric Anholt [Thu, 6 Dec 2018 01:10:15 +0000 (17:10 -0800)]
v3d: Don't forget to flush writes to UBOs.
If someone did TF into a UBO, we might have left the TF job un-flushed at
the point of reading.
Eric Anholt [Tue, 4 Dec 2018 21:48:10 +0000 (13:48 -0800)]
v3d: Make an array for frag/vert texture state in the context.
This simplifies a bunch of our texture handling, while introducing the
slots necessary for adding new shader stages.
Eric Anholt [Tue, 4 Dec 2018 21:36:48 +0000 (13:36 -0800)]
v3d: Re-use the wrap mode uniform on V3D 3.3.
Eric Anholt [Fri, 7 Dec 2018 20:36:55 +0000 (12:36 -0800)]
v3d: Put default vertex attribute values into the state uploader as well.
The default attributes are long-lived (the state struct is cached), and
only 256 bytes each.
Eric Anholt [Fri, 7 Dec 2018 20:18:34 +0000 (12:18 -0800)]
v3d: Create a state uploader for packing our shaders together.
Shaders are usually quite short, and are private to the context. We can
save memory and reduce the work the kernel needs to do at exec time by
packing them together in a stream uploader for long-lived state.
Eric Anholt [Fri, 7 Dec 2018 19:34:30 +0000 (11:34 -0800)]
v3d: Update simulator cache flushing code to match the kernel better.
We were missing the invalidate between bin and render (possibly relevant
for SSBOs), and still trying to flush the nonexistent L2C on 3.3+.
Eric Anholt [Fri, 2 Nov 2018 18:31:42 +0000 (11:31 -0700)]
v3d: Use the TFU to do generatemipmap.
This is a separate, dedicated hardware unit for texture layout conversions
and mipmap generation.
Eric Anholt [Thu, 1 Nov 2018 23:10:01 +0000 (16:10 -0700)]
v3d: Add the V3D TFU submit interface to the simulator.
The TFU lets us format raster and SAND images into formats that can be
read by the texture engine, and do mipmap generation.
The UAPI comes from drm-next
e69aa5f9b97f ("Merge tag
'drm-misc-next-2018-12-06' of git://anongit.freedesktop.org/drm/drm-misc
into drm-next")
Eric Anholt [Mon, 10 Sep 2018 15:19:48 +0000 (08:19 -0700)]
v3d: Use combined input/output segments.
The HW apparently has some issues (or at least a much more complicated VCM
calculation) with non-combined segments, and the closed source driver also
uses combined I/O. Until I get the last CTS failure resolved (which does
look plausibly like some VPM stomping), let's use combined I/O too.
Eric Anholt [Fri, 7 Dec 2018 21:03:29 +0000 (13:03 -0800)]
v3d: Add missing OES_half_float_linear support.
We were exposing ARB_texture_float, but apparently not the OES subset
flag. Fixes regression from GLES3 support to GLES2.
Fixes:
fcf9fcee3c8a ("mesa/main: do not require float-texture filtering
for es3")
Eric Anholt [Fri, 7 Dec 2018 20:53:16 +0000 (12:53 -0800)]
v3d: Add support for RGBA_SRGB along with BGRA_SRGB.
This is the actual native format for the hardware, without swizzling.
Noticed while debugging why GLES3 disappeared.
Kenneth Graunke [Sat, 21 Apr 2018 07:06:29 +0000 (00:06 -0700)]
intel/blorp: Expand blorp_address::offset to be 64 bits.
In the softpin world, surface state base address may be a fixed 64-bit
address (with no associated BO). It makes sense to store this in the
offset field. But it needs to be the full size.
We also update the clear color address to be consistently uint64_t
everywhere so we can continue passing intel_miptree_get_clear_color
a pointer to the blorp_address's offset field without type mismatches.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Rob Clark [Fri, 7 Dec 2018 19:11:01 +0000 (14:11 -0500)]
freedreno/drm: fix memory leak
Fix an emberrasing memory leak with the non-softpin submit/rb
implementation.
Fixes:
f3cc0d27475 freedreno: import libdrm_freedreno + redesign submit
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 5 Dec 2018 15:51:16 +0000 (10:51 -0500)]
freedreno/ir3: track max flow control depth for a5xx/a6xx
Rather than just hard-coding BRANCHSTACK size.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 8 Nov 2018 19:50:56 +0000 (14:50 -0500)]
freedreno/ir3: code-motion
Split up ir3_compiler_nir.c a bit before starting to add new stuff for
a6xx SSBO/image instructions.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 7 Nov 2018 18:22:12 +0000 (13:22 -0500)]
freedreno/ir3: sync instr/disasm
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 4 Dec 2018 14:52:14 +0000 (09:52 -0500)]
freedreno/ir3: don't fetch unused tex components
Detect when a component of an (for example) texture fetch is unused and
propagate the updated wrmask back to the parent instruction.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 3 Dec 2018 15:27:32 +0000 (10:27 -0500)]
freedreno/a6xx: blitter fixes
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 5 Dec 2018 15:17:20 +0000 (10:17 -0500)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 28 Nov 2018 15:35:32 +0000 (10:35 -0500)]
freedreno/drm: fix relocs in nested stateobjs
If we have an reloc from stateobjA to stateobjB, we would previously
leave stateobjB's bos out of the submit's bos table. Handle this case
by copying into stateobjA's reloc_bos table.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 30 Nov 2018 13:26:56 +0000 (08:26 -0500)]
freedreno/a5xx+a6xx: remove unused fs/vs pvt mem
copy/pasta from older gens
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 27 Nov 2018 20:19:16 +0000 (15:19 -0500)]
gallium: fix typo
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 1 Nov 2018 19:07:46 +0000 (15:07 -0400)]
freedreno: remove unused fd_surface fields
Signed-off-by: Rob Clark <robdclark@gmail.com>
Nicolai Hähnle [Wed, 5 Dec 2018 12:28:03 +0000 (13:28 +0100)]
meson: link LLVM 'native' component when LLVM is available
Linking against LLVM built with BUILD_SHARED_LIBS fails otherwise,
as the component is required for the draw module.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Connor Abbott [Fri, 7 Dec 2018 09:48:22 +0000 (10:48 +0100)]
nir: Fixup algebraic test for variable-sized conversions
b2i can now take any size boolean in preparation for 1-bit booleans, so
the error message printed is slightly different.
Fixes:
dca6cd9ce65 ("nir: Make boolean conversions sized just like the others")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108961
Cc: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Pitoiset [Fri, 7 Dec 2018 09:08:38 +0000 (10:08 +0100)]
gallium: add missing PIPE_CAP_SURFACE_SAMPLE_COUNT default value
Fixes:
2710c40e3c8 ("gallium: Add new PIPE_CAP_SURFACE_SAMPLE_COUNT")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Emil Velikov [Fri, 7 Dec 2018 11:50:12 +0000 (11:50 +0000)]
docs: update calendar, add news item and link release notes for 18.3.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 7 Dec 2018 11:27:49 +0000 (11:27 +0000)]
docs: add sha256 checksums for 18.3.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
d81beab96afb403915805435fd4b810a00291b99)
Emil Velikov [Fri, 7 Dec 2018 11:20:00 +0000 (11:20 +0000)]
docs: update 18.3.0 release notes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
d603cd9d84c8293c22407030c7664ac775ffb97f)
Kristian H. Kristensen [Tue, 6 Nov 2018 05:23:27 +0000 (21:23 -0800)]
freedreno: Add support for EXT_multisampled_render_to_texture
There is not much to do in freedreno - tile layout and multisample
state for gmem renderings is programmed based on the pfb sample count,
while resolve blits take the destination sample count from the resource.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Rob Clark [Mon, 29 Oct 2018 19:44:13 +0000 (15:44 -0400)]
freedreno/a6xx: MSAA
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Kristian H. Kristensen [Tue, 6 Nov 2018 05:22:44 +0000 (21:22 -0800)]
st/mesa: Add support for EXT_multisampled_render_to_texture
In gallium, we model the attachment sample count as a new nr_samples
field in pipe_surface. A driver can indicate support for the extension
using the new pipe cap, PIPE_CAP_MULTISAMPLED_RENDER_TO_TEXTURE.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Tue, 6 Nov 2018 21:08:32 +0000 (13:08 -0800)]
gallium: Add new PIPE_CAP_SURFACE_SAMPLE_COUNT
This new pipe cap and the new nr_samples field in pipe_surface lets a
state tracker bind a render target with a different sample count than
the resource. This allows for implementing
EXT_multisampled_render_to_texture and
EXT_multisampled_render_to_texture2.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Tue, 6 Nov 2018 05:19:21 +0000 (21:19 -0800)]
mesa: Add core support for EXT_multisampled_render_to_texture{,2}
This also turns on EXT_multisampled_render_to_texture which is a
subset of EXT_multisampled_render_to_texture2, allowing only
COLOR_ATTACHMENT0.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Vinson Lee [Thu, 6 Dec 2018 19:42:04 +0000 (11:42 -0800)]
nir/algebraic: Make algebraic_parser_test.sh executable.
Fixes make check permission error.
../../bin/test-driver: line 107: ./nir/tests/algebraic_parser_test.sh: Permission denied
FAIL nir/tests/algebraic_parser_test.sh (exit status: 126)
Fixes:
a0ae12ca91a4 ("nir/algebraic: Add unit tests for bitsize validation")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Samuel Pitoiset [Fri, 2 Nov 2018 08:50:32 +0000 (09:50 +0100)]
amd: remove support for LLVM 6.0
User are encouraged to switch to LLVM 7.0 released in September 2018.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kristian H. Kristensen [Tue, 4 Dec 2018 18:19:13 +0000 (10:19 -0800)]
gallium: Android build fixes
A couple of simple fixes for building on Android with autotools.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Jason Ekstrand [Wed, 7 Nov 2018 19:43:40 +0000 (13:43 -0600)]
nir: Make boolean conversions sized just like the others
Instead of a single i2b and b2i, we now have i2b32 and b2iN where N is
one if 8, 16, 32, or 64. This leads to having a few more opcodes but
now everything is consistent and booleans aren't a weird special case
anymore.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Fri, 9 Nov 2018 00:08:37 +0000 (18:08 -0600)]
nir/opt_algebraic: Add 32-bit specifiers to a bunch of booleans
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 7 Nov 2018 23:32:32 +0000 (17:32 -0600)]
nir/opt_algebraic: Drop bit-size suffixes from conversions
Suffixes are dropped from a bunch of conversion opcodes when it makes
sense to do so. Others are kept if we really do want the bit-size
restriction.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 7 Nov 2018 22:25:31 +0000 (16:25 -0600)]
nir/opt_algebraic: Simplify an optimization using the new search ops
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 7 Nov 2018 21:40:02 +0000 (15:40 -0600)]
nir/algebraic: Add support for unsized conversion opcodes
All conversion opcodes require a destination size but this makes
constructing certain algebraic expressions rather cumbersome. This
commit adds support to nir_search and nir_algebraic for writing
conversion opcodes without a size. These meta-opcodes match any
conversion of that type regardless of destination size and the size gets
inferred from the sizes of the things being matched or from other
opcodes in the expression.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 7 Nov 2018 20:32:19 +0000 (14:32 -0600)]
nir/algebraic: Refactor codegen a bit
Instead of using an OrderedDict, just have a (necessarily sorted) array
of transforms and a set of opcodes.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Thu, 8 Nov 2018 20:00:07 +0000 (14:00 -0600)]
nir/algebraic: Clean up some __str__ cruft
Both of these things are already handled in the Value base class so we
don't need to handle them explicitly in Constant.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 7 Nov 2018 18:19:36 +0000 (12:19 -0600)]
nir/opcodes: Rename tbool to tbool32
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 7 Nov 2018 18:15:22 +0000 (12:15 -0600)]
nir/opcodes: Pull in the type helpers from constant_expressions
While we're at it, we rework them a bit to all use regular expressions
and assert more.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Connor Abbott [Thu, 29 Nov 2018 16:46:59 +0000 (17:46 +0100)]
nir/algebraic: Add unit tests for bitsize validation
The non-failure path can be tested by just compiling mesa and then
testing it, but the failure paths won't be hit unless you make a mistake,
so it's best to test them with some unit tests.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Connor Abbott [Fri, 23 Nov 2018 16:34:19 +0000 (17:34 +0100)]
nir/algebraic: Rewrite bit-size inference
Before this commit, there were two copies of the algorithm: one in C,
that we would use to figure out what bit-size to give the replacement
expression, and one in Python, that emulated the C one and tried to
prove that the C algorithm would never fail to correctly assign
bit-sizes. That seemed pretty fragile, and likely to fall over if we
make any changes. Furthermore, the C code was really just recomputing
more-or-less the same thing as the Python code every time. Instead, we
can just store the results of the Python algorithm in the C
datastructure, and consult it to compute the bitsize of each value,
moving the "brains" entirely into Python. Since the Python algorithm no
longer has to match C, it's also a lot easier to change it to something
more closely approximating an actual type-inference algorithm. The
algorithm used is based on Hindley-Milner, although deliberately
weakened a little. It's a few more lines than the old one, judging by
the diffstat, but I think it's easier to verify that it's correct while
being as general as possible.
We could split this up into two changes, first making the C code use the
results of the Python code and then rewriting the Python algorithm, but
since the old algorithm never tracked which variable each equivalence
class, it would mean we'd have to add some non-trivial code which would
then get thrown away. I think it's better to see the final state all at
once, although I could also try splitting it up.
v2:
- Replace instances of "== None" and "!= None" with "is None" and
"is not None".
- Rename first_src to first_unsized_src
- Only merge the destination with the first unsized source, since the
sources have already been merged.
- Add a comment explaining what nir_search_value::bit_size now means.
v3:
- Fix one last instance to use "is not" instead of !=
- Don't try to be so clever when choosing which error message to print
based on whether we're in the search or replace expression.
- Fix trailing whitespace.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Samuel Pitoiset [Wed, 5 Dec 2018 12:48:36 +0000 (13:48 +0100)]
radv: expose VK_EXT_scalar_block_layout
Nothing to do, the compiler already handles that.
All new dEQP.VK.ubo.* and dEQP.VK.ssbo.* pass, except some
16-bit tests that are quite related to fdo bug #108114.
Only enable the extension on CIK+ because it might not work on SI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 5 Dec 2018 13:28:28 +0000 (14:28 +0100)]
spirv: add SpvCapabilityInt64Atomics
Required for VK_KHR_shader_atomic_int64.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Michal Srb [Fri, 23 Nov 2018 16:03:53 +0000 (17:03 +0100)]
drisw: Use separate drisw_loader_funcs for shm
The original code was modifying the global drisw_lf variable, which is bad
when there are multiple contexts in single process, each initialized with
different loader. One may support put_image_shm and the other not.
Since there are currently only two possible combinations, lets create two
global tables, one for each. Lets make them const, since we won't change them
and they can be shared.
This fixes crash in VLC. It used two GL contexts (each in different thread), one
was initialized by its Qt GUI, the other by its video output plugin. The first
one set the put_image_shm=drisw_put_image_shm, the second did not, but
since the same structure was used, the drisw_put_image_shm was used too. Then
it crashed because the second loader did not have putImageShm set.
Downstream bug:
https://bugzilla.opensuse.org/show_bug.cgi?id=
1113533
v2: Added Fixes and described the VLC bug.
Fixes:
63c427fa71a ("drisw: use putImageShm if available")
Signed-off-by: Michal Srb <msrb@suse.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Michal Srb [Fri, 23 Nov 2018 15:02:27 +0000 (16:02 +0100)]
gallium: Constify drisw_loader_funcs struct
The content is not expected to change.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Michal Srb <msrb@suse.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Samuel Pitoiset [Wed, 5 Dec 2018 10:45:19 +0000 (11:45 +0100)]
radv: wait on the high 32 bits of timestamp queries
In case we are unlucky if the low part is 0xffffffff.
Fixes:
5d6a560a29 ("radv: do not use the availability bit for timestamp queries")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 5 Dec 2018 10:34:39 +0000 (11:34 +0100)]
radv: reset pending_reset_query when flushing caches
If the driver used a compute shader for resetting a query pool,
it should be completed when caches are flushed.
This might reduce the number of stalls if operations are done
between vkCmdResetQueryPool() and vkCmdBeginQuery()
(or vkCmdWriteTimestamp()).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Alex Smith <asmith@feralinteractive.com>
Lionel Landwerlin [Mon, 3 Dec 2018 14:33:35 +0000 (14:33 +0000)]
anv/query: flush render target before copying results
This change tracks render target writes in the pipeline and applies a
render target flush before copying the query results to make sure the
preceding operations have landed in memory before the command streamer
initiates the copy.
v2: Simplify logic in CopyQueryResults (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108909
Fixes:
37f9788e9a8e44 ("anv: flush pipeline before query result copies")
Cc: mesa-stable@lists.freedesktop.org
Alex Smith [Wed, 5 Dec 2018 09:45:26 +0000 (09:45 +0000)]
radv: Flush before vkCmdWriteTimestamp() if needed
As done for vkCmdBeginQuery() already. Prevents timestamps from being
overwritten by previous vkCmdResetQueryPool() calls if the shader path
was used to do the reset.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108925
Fixes:
a41e2e9cf5 ("radv: allow to use a compute shader for resetting the query pool")
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Mon, 3 Dec 2018 21:45:03 +0000 (22:45 +0100)]
radv: rework the TC-compat HTILE hardware bug with COND_EXEC
After investigating on this, it appears that COND_WRITE doesn't
work correctly in some situations. I don't know exactly why does
it fail to update DB_Z_INFO.ZRANGE_PRECISION, but as AMDVLK
also uses COND_EXEC I think there is a reason.
Now the driver stores a new metadata value in order to reflect
the last fast depth clear state. If a TC-compat HTILE is fast cleared
with 0.0f, we have to update ZRANGE_PRECISION to 0 in order to
work around that hardware bug.
This fixes rendering issues with The Forest and DXVK and doesn't
seem to introduce any regressions.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108914
Fixes:
68dead112e7 ("radv: update the ZRANGE_PRECISION value for the TC-compat bug")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dieter Nützel [Tue, 4 Dec 2018 21:20:10 +0000 (22:20 +0100)]
docs/features: Delete double nv50 entry and wrong enumeration
trivial
Fix commit
d9b2234042142dc02a4844747d3c35e140da53dc
Signed-off-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Thu, 29 Nov 2018 20:34:05 +0000 (15:34 -0500)]
st/mesa: expose EXT_render_snorm on GLES
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Marek Olšák [Mon, 6 Aug 2018 06:48:12 +0000 (02:48 -0400)]
mesa: expose AMD_texture_texture4
because the closed driver exposes it. Tested by piglit.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Marek Olšák [Mon, 6 Aug 2018 04:29:00 +0000 (00:29 -0400)]
mesa: expose EXT_texture_compression_bptc in GLES
tested by piglit.
v2: rebase
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1)
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Marek Olšák [Mon, 6 Aug 2018 02:50:54 +0000 (22:50 -0400)]
mesa: expose EXT_texture_compression_rgtc on GLES
The spec was modified to support GLES. Tested by piglit.
v2: rebase
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1)
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Erik Faye-Lund [Tue, 4 Dec 2018 11:34:39 +0000 (12:34 +0100)]
mesa/main: fix up _mesa_has_rg_textures for gles2
rg-textures are supported in GLES 2.0 if EXT_texture_rg, so let's make
sure the enums are accepted.
Fixes:
510b6424607 "mesa/main: do not allow rg-textures enums before gles3"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108936
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Mon, 3 Dec 2018 19:00:34 +0000 (20:00 +0100)]
mesa/main: correct validation for GL_RGB565
Technically speaking, this validation was incorrect, because GL_RGB565
is only supported in OpenGL ES 1.x if OES_framebuffer_object is
supported. This couldn't lead to any real incorrect behavior, because
all drivers support OES_framebuffer_object. But let's keep the code
self-documenting, by correcting the check as per the spec.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Marek Olšák [Wed, 28 Nov 2018 01:42:44 +0000 (20:42 -0500)]
mesa: expose GL_EXT_texture_view as an alias of GL_OES_texture_view
There are no spec changes.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Marek Olšák [Wed, 28 Nov 2018 01:19:11 +0000 (20:19 -0500)]
st/mesa: expose GL_OES_texture_view
For format fallbacks like ETC and ASTC, switching between sRGB and linear
decoding is undefined, or at least is not bit-exact. Same as
EXT_texture_sRGB_decode on GLES.
There are no piglit or dEQP regresssions.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Eric Engestrom [Fri, 16 Nov 2018 12:26:17 +0000 (12:26 +0000)]
loader: deduplicate logger function declaration
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Wed, 7 Nov 2018 12:30:36 +0000 (12:30 +0000)]
mesa: drop unused & deprecated lib
DeprecationWarning: the imp module is deprecated in favour of importlib
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Tue, 4 Dec 2018 13:19:20 +0000 (13:19 +0000)]
anv: add unreachable() for VK_EXT_fragment_density_map
This silences the -Wswitch compiler warning.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Eric Engestrom [Thu, 29 Nov 2018 11:50:30 +0000 (11:50 +0000)]
meson: skip asm check when asm is disabled
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Andrii Simiklit [Wed, 14 Nov 2018 16:30:48 +0000 (18:30 +0200)]
intel/tools: make sure the binary file is properly read
1. tools/i965_disasm.c:58:4: warning:
ignoring return value of ‘fread’,
declared with attribute warn_unused_result
fread(assembly, *end, 1, fp);
v2: Fixed incorrect return value check.
( Eric Engestrom <eric.engestrom@intel.com> )
v3: Zero size file check placed before fread with exit()
( Eric Engestrom <eric.engestrom@intel.com> )
v4: - Title is changed.
- The 'size' variable was moved to top of a function scope.
- The assertion was replaced by the proper error handling.
- The error message on a caller side was fixed.
( Eric Engestrom <eric.engestrom@intel.com> )
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Toni Lönnberg [Tue, 4 Dec 2018 12:14:51 +0000 (14:14 +0200)]
intel/aubinator_error_decode: Get rid of warning for missing switch case
../src/intel/tools/aubinator_error_decode.c: In function ‘instdone_register_for_ring’:
../src/intel/tools/aubinator_error_decode.c:177:4: warning: enumeration value ‘I915_ENGINE_CLASS_INVALID’ not handled in switch [-Wswitch]
switch (class) {
^~~~~~
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Ilia Mirkin [Sun, 2 Dec 2018 22:08:03 +0000 (17:08 -0500)]
nouveau: set texture upload budget
It doesn't seem like the exact number has too much effect on the
performaince in "teximage". However setting it to just about anything
prevents some OOMs from getting hit. These values are not well-tuned,
but don't seem too bad.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 2 Dec 2018 04:53:00 +0000 (23:53 -0500)]
nv50,nvc0: add explicit handling of PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
Since the max attrib stride is 2048, the max src offset makes sense as
2047.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 2 Dec 2018 02:28:04 +0000 (21:28 -0500)]
nv50: always keep TSC slot 0 bound
All TXF operations implicitly use sampler 0, and fail if it's not bound
to anything. This does not happen in LINKED_TSC mode, but we don't
currently use this.
We ensure that TSC entry at id 0 has the SRGB conversion bit enabled
(and all samplers we normally generate will too). Then when the TSC at
*slot* 0 (not to be confused with entry 0 in the global TSC table) is
unbound, we bind it to entry 0. This way, TXF operations are not
dependent on there being a regular sampler bound there.
Fixes arb_texture_buffer_object-subdata-sync among others. (TBO's are
particularly susceptible to this as they don't bind a sampler.)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Mon, 3 Dec 2018 04:38:28 +0000 (14:38 +1000)]
radv: use 3d shader for gfx9 copies if dst is 3d
This fixes some crucible 3d miptree tests I've been working on
when executed using the compute shader path.
Fixes:
d08f267814 (radv/gfx9: fix 3d image to image transfers on compute queues.)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Mon, 26 Nov 2018 15:26:37 +0000 (16:26 +0100)]
radv: Check for shareable images in central place.
One place to put the logic makes things easier to change.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Mon, 26 Nov 2018 15:26:36 +0000 (16:26 +0100)]
radv/android: Use buffer metadata to determine scanout compat.
These days we don't always allocate scanout compatible textures anymore.
That does mean we have to fix the radv android WSI though.
Fixes:
b1444c9ccb0 "radv: Implement VK_ANDROID_native_buffer."
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>