OSDN Git Service
Sam McCall [Thu, 28 May 2020 14:14:49 +0000 (16:14 +0200)]
Prevent test from failing in my home directory
Frederik Gossen [Thu, 28 May 2020 14:10:11 +0000 (14:10 +0000)]
[MLIR] Fix operand type in `from_extent_tensor` in the shape dialect
The operand of `from_extent_tensor` is now of the same index type as the result
type of the inverse operation `to_extent_tensor`.
Differential Revision: https://reviews.llvm.org/D80283
Wen-Heng (Jack) Chung [Fri, 22 May 2020 21:25:00 +0000 (16:25 -0500)]
[mlir][gpu][mlir-cuda-runner] Refactor ConvertKernelFuncToCubin to be generic.
Make ConvertKernelFuncToCubin pass to be generic:
- Rename to ConvertKernelFuncToBlob.
- Allow specifying triple, target chip, target features.
- Initializing LLVM backend is supplied by a callback function.
- Lowering process from MLIR module to LLVM module is via another callback.
- Change mlir-cuda-runner to adopt the revised pass.
- Add new tests for lowering to ROCm HSA code object (HSACO).
- Tests for CUDA and ROCm are kept in separate directories.
Differential Revision: https://reviews.llvm.org/D80142
Frederik Gossen [Thu, 28 May 2020 14:04:39 +0000 (14:04 +0000)]
[MLIR] Add `num_elements` to the shape dialect
The operation `num_elements` determines the number of elements for a given
shape.
That is the product of its dimensions.
Differential Revision: https://reviews.llvm.org/D80281
Matt Arsenault [Fri, 15 May 2020 18:54:51 +0000 (14:54 -0400)]
InferAddressSpaces: Handle ptrmask intrinsic
This one is slightly odd since it counts as an address expression,
which previously could never fail. Allow the existing TTI hook to
return the value to use, and re-use it for handling how to handle
ptrmask.
Handles the no-op addrspacecasts for AMDGPU. We could probably do
something better based on analysis of the mask value based on the
address space, but leave that for now.
Matt Arsenault [Fri, 15 May 2020 21:29:40 +0000 (17:29 -0400)]
AMDGPU: Add baseline test for ptrmask infer address space
Frederik Gossen [Thu, 28 May 2020 13:55:02 +0000 (13:55 +0000)]
[MLIR] Add `index_to_size` and `size_to_index` to the shape dialect
Add the two conversion operations `index_to_size` and `size_to_index` to the
shape dialect.
This facilitates the conversion of index types between the shape and the
standard dialect.
Differential Revision: https://reviews.llvm.org/D80280
Alexander Belyaev [Thu, 28 May 2020 11:36:40 +0000 (13:36 +0200)]
[MLIR] Add TensorFromElementsOp to Standard ops.
Differential Revision: https://reviews.llvm.org/D80705
Frederik Gossen [Thu, 28 May 2020 13:40:34 +0000 (13:40 +0000)]
[MLIR] Tidy up documentation for `Shape_JoinOp`, `Shape_ReduceOp`, and
`Shape_ConstSizeOp`
Fix places that refer to `shape.type` instead of `shape.shape`.
Differential Revision: https://reviews.llvm.org/D80278
Simon Pilgrim [Thu, 28 May 2020 13:37:17 +0000 (14:37 +0100)]
FileOutputBuffer.h - remove unused includes. NFC.
Move dependent includes down to source files where necessary.
Simon Pilgrim [Thu, 28 May 2020 12:58:35 +0000 (13:58 +0100)]
WithColor.h - reduce unnecessary includes to forward declarations. NFC.
Frederik Gossen [Thu, 28 May 2020 13:35:51 +0000 (13:35 +0000)]
[MLIR] Move `ConcatOp` to its lexicographic position
Purely cosmetic change.
The operation implementations in `Shape.cpp` are now lexicographic order.
Differential Revision: https://reviews.llvm.org/D80277
Simon Pilgrim [Thu, 28 May 2020 12:34:09 +0000 (13:34 +0100)]
[X86][SSE] Peek though MOVMSK source sign bits using SimplifyMultipleUseDemandedBits
Allows SimplifyDemandedBitsForTargetNode to peek through multi-use ops where MOVMSK only demands the signbit of each vector element.
Alok Kumar Sharma [Thu, 28 May 2020 10:16:06 +0000 (15:46 +0530)]
Fixed bot failure after
d20bf5a7258d4b6a7
There was a failure on windows bit due to format mismatch on
different(Hex and Decimal) platforms even if meaning of output is same.
For example on X86 linux =>
DW_OP_plus_uconst 0x70, DW_OP_deref, DW_OP_lit4, DW_OP_mul
^
on X86 Windows-gnu =>
DW_AT_location (DW_OP_fbreg +112, DW_OP_deref, DW_OP_lit4, DW_OP_mul)
: error: CHECK-SAME: expected string not found in input
; CHECK-SAME: DW_OP_plus_uconst 0x70, DW_OP_deref, DW_OP_lit4, DW_OP_mul
^
<stdin>:28:17: note: scanning from here
DW_AT_location (DW_OP_fbreg +112, DW_OP_deref, DW_OP_lit4, DW_OP_mul)
^
<stdin>:28:18: note: possible intended match here
DW_AT_location (DW_OP_fbreg +112, DW_OP_deref, DW_OP_lit4, DW_OP_mul)
Now the test is limited to x86 using REQUIRED and -mtriple.
http://45.33.8.238/win/16214/step_11.txt
Dmitry Preobrazhensky [Thu, 28 May 2020 12:07:58 +0000 (15:07 +0300)]
[AMDGPU][MC][GFX908] Corrected src0 of v_accvgpr_write to accept only VGPRs and inline constants.
This change disables use of special SGPR registers like scc, vccz, execz, etc as operands of v_accvgpr_write.
See bug 45414: https://bugs.llvm.org/show_bug.cgi?id=45414
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D80530
Simon Pilgrim [Thu, 28 May 2020 12:07:06 +0000 (13:07 +0100)]
Fix MSVC signed/unsigned comparison warnings. NFC.
Simon Pilgrim [Thu, 28 May 2020 12:02:44 +0000 (13:02 +0100)]
DWARFDebugMacro.h - remove unnecessary WithColor.h include. NFC.
Simon Pilgrim [Thu, 28 May 2020 12:01:53 +0000 (13:01 +0100)]
llvm-dwarfdump.h - remove unnecessary WithColor.h include. NFC.
Nemanja Ivanovic [Thu, 28 May 2020 11:55:37 +0000 (06:55 -0500)]
[Clang] Enable _Complex __float128
When I added __float128 a while ago, I neglected to add support for the complex
variant of the type. This patch just adds that.
Differential revision: https://reviews.llvm.org/D80533
Dmitry Preobrazhensky [Thu, 28 May 2020 11:25:29 +0000 (14:25 +0300)]
[AMDGPU][MC] Corrected v_writelane_b32 to fix a decoding bug
Corrected vdst_in to match vdst operand type.
See bug 45193: https://bugs.llvm.org/show_bug.cgi?id=45193
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D80636
Sam McCall [Sun, 19 Apr 2020 00:19:25 +0000 (02:19 +0200)]
[clangd] Highlight related control flow.
Summary:
This means e.g. highlighting "return" will show other returns/throws
from the same function, highlighting a case will show all the
return/breaks etc.
This is a bit of an abuse of textDocument/highlight, but seems useful.
Reviewers: adamcz
Subscribers: ilya-biryukov, MaskRay, jkorous, mgrang, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D78454
Dmitry Preobrazhensky [Thu, 28 May 2020 11:15:29 +0000 (14:15 +0300)]
[AMDGPU][MC][DISASSEMBLER] Corrected decoder to consume each code fragment only once
Summary: disabled disassembly of successfully decoded fragments of code.
See detailed bug description: https://bugs.llvm.org/show_bug.cgi?id=46101
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D80637
Valeriy Savchenko [Tue, 28 Apr 2020 09:21:39 +0000 (12:21 +0300)]
[analyzer] Allow bindings of the CompoundLiteralRegion
Summary:
CompoundLiteralRegions have been properly modeled before, but
'getBindingForElement` was not changed to accommodate this change
properly.
rdar://problem/
46144644
Differential Revision: https://reviews.llvm.org/D78990
Georgii Rymar [Thu, 14 May 2020 11:15:40 +0000 (14:15 +0300)]
[yaml2obj] - Implement the "SectionHeaderTable" tag.
With the "SectionHeaderTable" it is now possible to reorder
entries in the section header table.
It also allows to stop emitting the table.
Differential revision: https://reviews.llvm.org/D80002
Sam McCall [Tue, 26 May 2020 13:43:52 +0000 (15:43 +0200)]
[DebugInfo] Use SplitTemplateClosers (foo<bar<baz> >) in DWARF too
Summary:
D76801 caused some regressions in debuginfo compatibility by changing how
certain functions were named.
For CodeView we try to mirror MSVC exactly: this was fixed in
a549c0d00486
For DWARF the situation is murkier. Per David Blaikie:
> In general DWARF doesn't specify this at all.
> [...]
> This isn't the only naming divergence between GCC and Clang
Nevertheless, including the space seems to provide better compatibility with
GCC and GDB. E.g. cpexprs.cc in the GDB testsuite requires this formatting.
And there was no particular desire to change the printing of names in debug
info in the first place (just in diagnostics and other more user-facing text).
Fixes PR46052
Reviewers: dblaikie, labath
Subscribers: aprantl, cfe-commits, dyung
Tags: #clang
Differential Revision: https://reviews.llvm.org/D80554
Florian Hahn [Thu, 28 May 2020 09:43:47 +0000 (10:43 +0100)]
[AArch64] Precommit new fp extraction/insertion test.
Alok Kumar Sharma [Thu, 28 May 2020 09:42:28 +0000 (15:12 +0530)]
Fixed bot failure after
d20bf5a7258d4b6a7
There were some bot failures due unused funtion `rotateSign`
left in code.
http://lab.llvm.org:8011/builders/clang-ppc64le-rhel/builds/3731
error: unused function 'rotateSign' [-Werror,-Wunused-function]
static uint64_t rotateSign(int64_t I)
Cullen Rhodes [Thu, 28 May 2020 09:37:55 +0000 (09:37 +0000)]
[AArch64][SVE] Add support for spilling/filling ZPR2/3/4
Summary:
This patch enables the register allocator to spill/fill lists of 2, 3
and 4 SVE vectors registers to/from the stack. This is implemented with
pseudo instructions that get expanded to individual LDR_ZXI/STR_ZXI
instructions in AArch64ExpandPseudoInsts.
Patch by Sander de Smalen.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D75988
Victor Campos [Mon, 9 Mar 2020 13:29:37 +0000 (13:29 +0000)]
[ARM] Improve codegen of volatile load/store of i64
Summary:
Instead of generating two i32 instructions for each load or store of a volatile
i64 value (two LDRs or STRs), now emit LDRD/STRD.
These improvements cover architectures implementing ARMv5TE or Thumb-2.
The code generation explicitly deviates from using the register-offset
variant of LDRD/STRD. In this variant, the register allocated to the
register-offset cannot be reused in any of the remaining operands. Such
restriction seems to be non-trivial to implement in LLVM, thus it is
left as a to-do.
Differential Revision: https://reviews.llvm.org/D70072
Thomas Preud'homme [Tue, 5 Mar 2019 23:20:29 +0000 (23:20 +0000)]
FileCheck [10/12]: Add support for signed numeric values
Summary:
This patch is part of a patch series to add support for FileCheck
numeric expressions. This specific patch adds support signed numeric
values, thus allowing negative numeric values.
As such, the patch adds a new class to represent a signed or unsigned
value and add the logic for type promotion and type conversion in
numeric expression mixing signed and unsigned values. It also adds
the %d format specifier to represent signed value.
Finally, it also adds underflow and overflow detection when performing a
binary operation.
Copyright:
- Linaro (changes up to diff 183612 of revision D55940)
- GraphCore (changes in later versions of revision D55940 and
in new revision created off D55940)
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson
Reviewed By: jhenderson, arichardson
Subscribers: MaskRay, hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, kristina, hfinkel, rogfer01, JonChesterfield
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60390
Cullen Rhodes [Thu, 28 May 2020 09:00:51 +0000 (09:00 +0000)]
[TableGen] Fix non-standard escape warnings for braces in InstAlias
Summary:
TableGen interprets braces ('{}') in the asm string of instruction aliases as
variants but when defining aliases with literal braces they have to be escaped
to prevent them being removed.
Braces are escaped with '\\', for example:
def FooBraces : InstAlias<"foo \\{$imm\\}", (foo IntOperand:$imm)>;
Although when TableGen is emitting the assembly writer (-gen-asm-writer)
the AsmString that gets emitted is:
AsmString = "foo \{$\x01\}";
In c/c++ braces don't need to be escaped which causes compilation
warnings:
warning: use of non-standard escape character '\{' [-Wpedantic]
This patch fixes the issue by unescaping the flattened alias asm string
in the asm writer, by replacing '\{\}' with '{}'.
Reviewed By: hfinkel
Differential Revision: https://reviews.llvm.org/D79991
Marco Elver [Wed, 27 May 2020 21:55:53 +0000 (23:55 +0200)]
[Clang][Sanitizers] Expect test failure on {arm,thumb}v7
Summary:
Versions of LLVM built on {arm,thumb}v7 appear to have differently
configured pass managers, which causes restrictions on which sanitizers
we may use.
As such, expect failure of the recently added "sanitize-coverage.c" test
on these architectures until we can investigate armv7's restrictions.
Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=46117
Reviewers: vitalybuka, glider
Reviewed By: glider
Subscribers: glider, kristof.beyls, danielkiss, cfe-commits, vvereschaka
Tags: #clang
Differential Revision: https://reviews.llvm.org/D80668
Dmitry Vyukov [Thu, 28 May 2020 09:03:02 +0000 (11:03 +0200)]
tsan: disable java_finalizer2 test on darwin
pthread_barrier_t is not supported on darwin.
Do what other tests that use pthread_barrier_t do.
Sander de Smalen [Thu, 28 May 2020 08:27:00 +0000 (09:27 +0100)]
[CodeGen] Specify meaning of ISD opcodes for scalable vectors
This patch contains changes to the description of EXTRACT_SUBVECTOR,
INSERT_SUBVECTOR, INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT and
CONCAT_VECTORS to specify their behaviour for scalable vectors.
For EXTRACT_SUBVECTOR it specifies that the IDX is scaled by the
same runtime scaling as the extracted (or inserted) vector. This
definition is the most natural extension to EXTRACT_SUBVECTOR for
scalable vectors, as most use-cases that work on fixed-width types
will have the same meaning for scalable types. For legalization for
example, it is common to split the vector operation to operate on
the LO and HI halfs of a vector.
For a fixed width vector <16 x i8> this would be expressed with:
v16i8 %res = EXTRACT_SUBVECTOR v32i8 %v, i32 16
For a scalable vector, this would similarly be expressed as:
nxv16i8 %res = EXTRACT_SUBVECTOR nxv32i8 %V, i32 16
By extending the meaning of IDX for scalable vectors, most existing
optimisations on EXTRACT/INSERT_SUBVECTOR work for scalable vectors
without any changes. This definition also allows extracting a
fixed-width subvector from a scalable vector, which is useful to
e.g. extract the low N lanes of a scalable vector.
This patch is not NFC because it sets the meaning of these nodes
for scalable vectors, which future patches will build upon.
Reviewers: efriedma, ctetreau, rogfer01, craig.topper
Reviewed By: efriedma
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79806
Alok Kumar Sharma [Thu, 28 May 2020 08:01:22 +0000 (13:31 +0530)]
[DebugInfo] Upgrade DISubrange to support Fortran dynamic arrays
This patch upgrades DISubrange to support fortran requirements.
Summary:
Below are the updates/addition of fields.
lowerBound - Now accepts signed integer or DIVariable or DIExpression,
earlier it accepted only signed integer.
upperBound - This field is now added and accepts signed interger or
DIVariable or DIExpression.
stride - This field is now added and accepts signed interger or
DIVariable or DIExpression.
This is required to describe bounds of array which are known at runtime.
Testing:
unit test cases added (hand-written)
check clang
check llvm
check debug-info
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D80197
Mehdi Amini [Thu, 28 May 2020 08:08:20 +0000 (08:08 +0000)]
Harden MLIR detection of misconfiguration when missing dialect registration
This changes will catch error where C++ op are used without being
registered, either through creation with the OpBuilder or when trying to
cast to the C++ op.
Differential Revision: https://reviews.llvm.org/D80651
LLVM GN Syncbot [Thu, 28 May 2020 08:08:39 +0000 (08:08 +0000)]
[gn build] Port
5921782f744
Kazushi (Jam) Marukawa [Thu, 28 May 2020 08:07:21 +0000 (10:07 +0200)]
[VE] Implements minimum MC layer for VE (3/4)
Summary:
Define ELF binary code for VE and modify code where should use this new code.
Depends on D79544.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D79545
Sjoerd Meijer [Thu, 28 May 2020 07:36:04 +0000 (08:36 +0100)]
[HardwareLoops] LangRef Intrinsic descriptions
The HardwareLoop intrinsics were missing and not described in LangRef. This
adds these descriptions/definitions.
Differential Revision: https://reviews.llvm.org/D80316
Balázs Kéri [Wed, 27 May 2020 14:23:42 +0000 (16:23 +0200)]
[Analyzer][StreamChecker] Added check for "indeterminate file position".
Summary:
According to the standard, after a `wread` or `fwrite` call the file position
becomes "indeterminate". It is assumable that a next read or write causes
undefined behavior, so a (fatal error) warning is added for this case.
The indeterminate position can be cleared by some operations, for example
`fseek` or `freopen`, not with `clearerr`.
Reviewers: Szelethus, baloghadamsoftware, martong, NoQ, xazax.hun, dcoughlin
Reviewed By: Szelethus
Subscribers: rnkovacs, NoQ, xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, gamesh411, Charusso, martong, ASDenysPetrov, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D80018
Kazu Hirata [Thu, 28 May 2020 05:30:10 +0000 (22:30 -0700)]
[JumpThreading] Use emplace_back instead of push_back (NFC)
Summary: This patch replaces push_back with emplace_back where appropriate.
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D80688
Shengchen Kan [Mon, 25 May 2020 02:18:44 +0000 (10:18 +0800)]
[Driver][X86] Support branch align options with LTO
Summary: Before this patch, we use two different ways to pass options to align branch
depending on whether LTO is enabled. For example, `-mbranches-within-32B-boundaries`
w/o LTO and `-Wl,-plugin-opt=-x86-branches-within-32B-boundaries` w/ LTO. It's
inconvenient, so this patch unifies the way: we only need to pass options like
`-mbranches-within-32B-boundaries` to align branches, no matter LTO is enabled or not.
Differential Revision: https://reviews.llvm.org/D80289
Sourabh Singh Tomar [Wed, 27 May 2020 08:31:35 +0000 (14:01 +0530)]
[docs] Release notes for DIModule metadata
Updated the release notes for the changes in the DIModule metadata.
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D80614
Jonas Devlieghere [Thu, 28 May 2020 04:13:08 +0000 (21:13 -0700)]
[lldb/Test] Import all decorators.
Fixes "NameError: name 'skipIfReproducer' is not defined".
Jonas Devlieghere [Thu, 28 May 2020 04:01:09 +0000 (21:01 -0700)]
[lldb/Reproducers] Skip or fix the remaining tests.
After this patch all remaining tests should pass on macOS when replayed
from a reproducer.
To capture the reproducers:
./bin/llvm-lit ../llvm-project/lldb/test/ --param lldb-run-with-repro=capture
To replay the reproducers:
./bin/llvm-lit ../llvm-project/lldb/test/ --param lldb-run-with-repro=replay
Vitaly Buka [Thu, 28 May 2020 02:28:42 +0000 (19:28 -0700)]
[NFC,StackSafety] Add StackSafetyGlobalInfo class
LLVM GN Syncbot [Thu, 28 May 2020 02:47:12 +0000 (02:47 +0000)]
[gn build] Port
660cda572d6
Jan Korous [Tue, 31 Mar 2020 21:05:17 +0000 (14:05 -0700)]
[Analyzer][WebKit] NoUncountedMembersChecker
Differential Revision: https://reviews.llvm.org/D77178
Dan Liew [Wed, 27 May 2020 22:50:03 +0000 (15:50 -0700)]
Temporarily disable the following failing tests on Darwin:
AddressSanitizer-Unit :: ./Asan-i386-calls-Test/AddressSanitizer.LongJmpTest
AddressSanitizer-Unit :: ./Asan-i386-calls-Test/AddressSanitizer.SigLongJmpTest
AddressSanitizer-Unit :: ./Asan-i386-inline-Test/AddressSanitizer.LongJmpTest
AddressSanitizer-Unit :: ./Asan-i386-inline-Test/AddressSanitizer.SigLongJmpTest
These failures will be examined properly when time permits.
rdar://problem/
62141412
Philip Reames [Thu, 28 May 2020 01:56:50 +0000 (18:56 -0700)]
[Statepoint] Reduce scope of usage of ImmutableStatepoint
Can't quite fully remove it yet as some more items need sunk the GCStatepointInst class from the wrapper, but we can at least reduce scope.
Xing GUO [Wed, 27 May 2020 08:59:45 +0000 (16:59 +0800)]
[ObjectYAML][MachO] Add error handling in MachOEmitter.
Currently, `yaml2macho` doesn't support error handling. This patch helps improve it.
Differential Revision: https://reviews.llvm.org/D80535
Philip Reames [Thu, 28 May 2020 01:31:00 +0000 (18:31 -0700)]
[Statepoint] Replace uses of isX functions with idiomatic isa<X>
Now that all of the statepoint related routines have classes with isa support, let's cleanup.
I'm leaving the (dead) utitilities in tree for a few days so that I can do the same cleanup downstream without breakage.
Philip Reames [Thu, 28 May 2020 01:02:49 +0000 (18:02 -0700)]
Sink first bit of functionality from Statepoint to GCStatepointInst
Starting with the obvious stuff. I initially tried to include the inline operand sequences too, but managed to get code which confused *me*. Since several parts of those are being entirely removed in the near future, I may defer that portion until the cleanup is done.
Vitaly Buka [Thu, 28 May 2020 00:41:17 +0000 (17:41 -0700)]
[NFC,StackSafety] Cleanup alloca size calculation
Fangrui Song [Thu, 28 May 2020 00:42:35 +0000 (17:42 -0700)]
[ELF][test] Fix wrap-no-real.s after D51283
Give %t3.so a DT_SONAME so that the DT_NEEDED entry in a dependent executable has a fixed length.
Richard Smith [Thu, 28 May 2020 00:20:15 +0000 (17:20 -0700)]
Do not warn that an expression of the form (void)arr; is unused when
arr is a volatile non-local array.
This fixes a recent regression exposed by removing lvalue-to-rvalue
conversion of discarded volatile arrays. In passing, regularize the
rules we use to determine whether '(void)expr;' warns when expr is a
volatile glvalue.
Philip Reames [Thu, 28 May 2020 00:16:41 +0000 (17:16 -0700)]
Introduce a GCStatepointInst type analogous to IntrinsicInst subclasses
Back when we had CallSite, we implemented the current Statepoint/ImmutableStatepoint structure in analogous manner. Now that CallSite has been removed, the structure used for statepoints looks decidely out of place. gc.statepoint is one of the small handful of intrinsics which are invokable. Because of this, it can't subclass IntrinsicInst as is idiomatic.
This change simply introduces the GCStatepointInst class, restructures the existing Statepoint/ImmutableStatepoint types to wrap it. I will be landing a series of changes to sink functionality into GCStatepointInst and updating callers to be more idiomatic.
Fangrui Song [Thu, 28 May 2020 00:20:41 +0000 (17:20 -0700)]
[gn build] Add MLAnalysisTests after D80579
Mircea Trofin [Thu, 28 May 2020 00:04:28 +0000 (17:04 -0700)]
[llvm][NFC] ProfileSummaryInfo - const-ify APIs
Follow-up from https://reviews.llvm.org/D79920
Fangrui Song [Thu, 28 May 2020 00:12:02 +0000 (17:12 -0700)]
[gn build] Port D80579
Rui Ueyama [Wed, 27 May 2020 23:18:55 +0000 (16:18 -0700)]
[ELF] --wrap: Drop __real_ symbol from the symbol table
In D34993, we discussed and concluded that we should drop `__real_
symbol from the symbol table, but I did the opposite in D50569.
This patch is to drop `__real_` symbol.
MaskRay's note: omitting `__real_` is important if it is undefined:
otherwise a subsequent link may error due to the undefined `__real_` in .dynsym
Differential Revision: https://reviews.llvm.org/D51283
Layton Kifer [Wed, 27 May 2020 23:54:20 +0000 (16:54 -0700)]
[TRE] Allow elimination when the returned value is non-constant
Currently we can only eliminate call return pairs that either return the
result of the call or a dynamic constant. This patch removes that
limitation.
Differential Revision: https://reviews.llvm.org/D79660
Stanislav Mekhanoshin [Wed, 27 May 2020 19:21:26 +0000 (12:21 -0700)]
AMDGPU/GlobalISel: Fixed insert element for non-standard vectors
Differential Revision: https://reviews.llvm.org/D80653
Leonard Chan [Wed, 27 May 2020 23:16:56 +0000 (16:16 -0700)]
[Lexer] Fix invalid suffix diagnostic for fixed-point literals
Committing on behalf of nagart, who authored this patch.
Differential Revision: https://reviews.llvm.org/D80412
Matt Arsenault [Wed, 27 May 2020 14:59:14 +0000 (10:59 -0400)]
AMDGPU: Support non-entry block static sized allocas
OpenMP emits these for some reason, so handle them. Assume these use
4096 bytes by default, with a flag to override this. Also change the
related stack assumption for calls to have a flag.
Matt Arsenault [Wed, 27 May 2020 16:33:55 +0000 (12:33 -0400)]
DAG: Fix expansion of DYNAMIC_STACKALLOC for StackGrowsUp targets
Can't test this since I can't directly use the default expansion for
AMDGPU. It needs to scale the amount by the wave size, rather than use
the raw byte size value.
Stanislav Mekhanoshin [Thu, 21 May 2020 19:41:29 +0000 (12:41 -0700)]
AMDGPU/GlobalISel: Fixed handling of non-standard vectors
We do not have register classes for all possible vector
sizes, so round it up for extract vector element.
Also fixes selection of G_MERGE_VALUES when vectors are
not a power of two.
This has required to refactor getRegSplitParts() in way
that it can handle not just power of two vectors.
Ideally we would like RegSplitParts to be generated by
tablegen.
Differential Revision: https://reviews.llvm.org/D80457
Fangrui Song [Wed, 27 May 2020 22:29:10 +0000 (15:29 -0700)]
Fangrui Song [Wed, 27 May 2020 22:21:08 +0000 (15:21 -0700)]
[MLPolicies] Fix dependency and -DBUILD_SHARED_LIBS=on builds after D80579
Mircea Trofin [Wed, 27 May 2020 22:11:43 +0000 (15:11 -0700)]
Fix shared libs build break introduced in rG98ef93eabd76
Adrian McCarthy [Wed, 27 May 2020 20:53:47 +0000 (13:53 -0700)]
Fix Windows command line bug when last token in response file is ""
Patch by Neil Dhar <dhar@alumni.duke.edu>
Current state machine for parsing tokens from response files in Windows
does not correctly handle the case where the last token is "". The current
implementation handles the last token by only adding it if it is not empty,
however this does not cover the case where the last token is meant to be
the empty string. We can cover this case by checking whether the state
machine was last in the UNQUOTED state, which indicates that the last
character of the input was a non-whitespace character.
Differential Revision: https://reviews.llvm.org/D78346
MaheshRavishankar [Wed, 27 May 2020 21:12:35 +0000 (14:12 -0700)]
[mlir][Linalg] Add missing library linkage for shared library builds.
Differential Revision: https://reviews.llvm.org/D80664
Adrian Prantl [Wed, 27 May 2020 21:26:15 +0000 (14:26 -0700)]
Fix a use-after-free in GetXcodeSDKPath
Introduced in https://reviews.llvm.org/D80595. Thanks Jonas for noticing!
Differential Revision: https://reviews.llvm.org/D80666
Louis Dionne [Wed, 27 May 2020 20:52:22 +0000 (16:52 -0400)]
[NFC] Reformat TEST_FOO macros in test_macros.h
To make them easier to read and to make it easier to add new ones.
Jonas Devlieghere [Wed, 27 May 2020 20:49:15 +0000 (13:49 -0700)]
[lldb/Reproducers] Skip & add FIXME to tests failing with unexpected packet.
Add skip decorator to tests failing with an unexpected packet during
passive replay.
Jonas Devlieghere [Wed, 27 May 2020 20:10:19 +0000 (13:10 -0700)]
[lldb/Reproducers] Differentiate active and passive replay unexpected packet.
Sean Silva [Tue, 26 May 2020 23:45:32 +0000 (16:45 -0700)]
[mlir][shape] Use IndexElementsAttr in Shape dialect.
Summary:
Index is the proper type for storing shapes when constant folding, so
this fixes the previous code (which was using i64).
Differential Revision: https://reviews.llvm.org/D80600
Sean Silva [Tue, 26 May 2020 23:44:20 +0000 (16:44 -0700)]
[mlir][core] Add IndexElementsAttr helpers.
Summary:
In a follow-up, I'll update the Shape dialect to use this instead of
I64ElementsAttr.
Differential Revision: https://reviews.llvm.org/D80601
Mircea Trofin [Tue, 26 May 2020 19:07:08 +0000 (12:07 -0700)]
[llvm] Add function feature extraction analysis
Summary:
This patch introduces an analysis pass to extract function features,
which will be needed by the ML InlineAdvisor.
RFC: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140763.html
Reviewers: davidxl, dblaikie, jdoerfert
Subscribers: mgorny, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D80579
Michael Liao [Wed, 27 May 2020 20:02:15 +0000 (16:02 -0400)]
Enable `align <n>` to be used in the intrinsic definition.
- This allow us to specify the (minimal) alignment on an intrinsic's
arguments and, more importantly, the return value.
Differential Revision: https://reviews.llvm.org/D80422
Michael Liao [Wed, 27 May 2020 19:58:07 +0000 (15:58 -0400)]
Refactor argument attribute specification in intrinsic definition. NFC.
- Argument attribute needs specifiying through `ArgIndex<n>`
(corresponding to `FirstArgIndex`) to distinguish explicitly from the
index number from the overloaded type list.
- In addition, `RetIndex` (corresponding to `ReturnIndex`) and
`FuncIndex` (corresponding to `FunctionIndex`) are introduced for us
to associate attributes on the return value and potentially function
itself.
Differential Revision: https://reviews.llvm.org/D80422
Vitaly Buka [Wed, 27 May 2020 20:32:58 +0000 (13:32 -0700)]
[NFC,StackSafety] Rename some variables
Vitaly Buka [Wed, 27 May 2020 20:22:16 +0000 (13:22 -0700)]
[StackSafety] Bailout more aggressively
Many edge cases, e.g. wrapped ranges, can be processed
precisely without bailout. However it's very unlikely that
memory access with min/max integer offsets will be
classified as safe anyway.
Early bailout may help with ThinLTO where we can
drop unsafe parameters from summaries.
Sean Silva [Wed, 27 May 2020 03:14:34 +0000 (20:14 -0700)]
Remove error-prone mlir::ExecutionEngine::invoke overload.
I just spent a bunch of time debugging a mysterious bug that ended being due to my SmallVector getting passed to the Args&... overload instead of the MutableArrayRef overload, with disastrous results.
I appreciate the intent of this API, but for a function that does a bunch of unsafe casts, adding in potential overload confusion is just too much C++ footgun. If we end up needing this functionality, having something like a separate `packArgs(Args&...) -> SmallVector` overload would be preferable.
Turns out this API is unused and untested (even out of tree as far as I can tell, modulo the optional passing of no args to the other invoke as I fixed in this patch), so it's an easy fix -- just delete it and touch up the other overload.
Differential Revision: https://reviews.llvm.org/D80607
Juneyoung Lee [Wed, 27 May 2020 16:48:37 +0000 (01:48 +0900)]
[TargetPassConfig] Add CanonicalizeFreezeInLoops before LSR
Summary:
This patch adds CanonicalizeFreezeInLoops before LSR.
Relevant patch: https://reviews.llvm.org/D77523
Reviewers: spatel, efriedma, jdoerfert, fhahn, nikic, reames, xbolva00
Reviewed By: nikic
Subscribers: xbolva00, nikic, lebedev.ri, hiraditya, llvm-commits, sanwou01, nlopes
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D77524
Nicolas Vasilache [Wed, 27 May 2020 20:14:12 +0000 (16:14 -0400)]
[mlir] Fix RunnerUtils template specialization
Undoing a spurious change that broke SFINAE for some out of core use
cases.
MaheshRavishankar [Wed, 27 May 2020 19:42:14 +0000 (12:42 -0700)]
[mlir][Linalg] Fix build failure from D80188
Differential Revision: https://reviews.llvm.org/D80657
Michael Liao [Wed, 27 May 2020 19:57:03 +0000 (15:57 -0400)]
Fix `-Wpedantic` warning. NFC.
Jessica Paquette [Sat, 16 May 2020 00:37:12 +0000 (17:37 -0700)]
[GlobalISel] Don't combine instructions which are fed by memory instructions.
If we have a memory instruction (e.g. a load), we shouldn't combine it away in
some trivial combine.
It's possible that, say, a call lives between the instructions. This could
modify the value loaded, making the load instructions not safe to fold.
Differential Revision: https://reviews.llvm.org/D80053
Dmitry Vyukov [Wed, 27 May 2020 19:47:13 +0000 (21:47 +0200)]
tsan: fix test in debug mode
sanitizer-x86_64-linux-autoconf has failed after the previous tsan commit:
FAIL: ThreadSanitizer-x86_64 :: java_finalizer2.cpp (245 of 403)
******************** TEST 'ThreadSanitizer-x86_64 :: java_finalizer2.cpp' FAILED ********************
Script:
--
: 'RUN: at line 1'; /b/sanitizer-x86_64-linux-autoconf/build/tsan_debug_build/./bin/clang --driver-mode=g++ -fsanitize=thread -Wall -m64 -gline-tables-only -I/b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/test/tsan/../ -std=c++11 -I/b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/test/tsan/../ -nostdinc++ -I/b/sanitizer-x86_64-linux-autoconf/build/tsan_debug_build/tools/clang/runtime/compiler-rt-bins/lib/tsan/libcxx_tsan_x86_64/include/c++/v1 -O1 /b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/test/tsan/java_finalizer2.cpp -o /b/sanitizer-x86_64-linux-autoconf/build/tsan_debug_build/tools/clang/runtime/compiler-rt-bins/test/tsan/X86_64Config/Output/java_finalizer2.cpp.tmp && /b/sanitizer-x86_64-linux-autoconf/build/tsan_debug_build/tools/clang/runtime/compiler-rt-bins/test/tsan/X86_64Config/Output/java_finalizer2.cpp.tmp 2>&1 | FileCheck /b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/test/tsan/java_finalizer2.cpp
--
Exit Code: 1
Command Output (stderr):
--
/b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/test/tsan/java_finalizer2.cpp:82:11: error: CHECK: expected string not found in input
// CHECK: DONE
^
<stdin>:1:1: note: scanning from here
FATAL: ThreadSanitizer CHECK failed: /b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/lib/tsan/rtl/tsan_sync.cpp:69 "((*meta)) == ((0))" (0x4000003e, 0x0)
^
<stdin>:5:12: note: possible intended match here
#3 __tsan::OnUserAlloc(__tsan::ThreadState*, unsigned long, unsigned long, unsigned long, bool) /b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/lib/tsan/rtl/tsan_mman.cpp:225:16 (java_finalizer2.cpp.tmp+0x4af407)
^
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/51143/steps/test%20tsan%20in%20debug%20compiler-rt%20build/logs/stdio
Fix heap object overlap by offsetting java heap as other tests are doing.
alex-t [Mon, 18 May 2020 20:40:27 +0000 (23:40 +0300)]
[AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO.
Summary: This fixes the
5b898bddff51 bug when the carry-in and carry-out registers became lost in lowering S_ADD/SUB_CO_PSEUDO.
Reviewers: rampitec, arsenm
Reviewed By: arsenm
Subscribers: msearles, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D80158
Adrian Prantl [Tue, 26 May 2020 22:40:43 +0000 (15:40 -0700)]
Also cache negative results in GetXcodeSDKPath (NFC)
This fixes a performance issue in the failure case.
rdar://
63547920
Differential Revision: https://reviews.llvm.org/D80595
Jonas Devlieghere [Wed, 27 May 2020 19:07:08 +0000 (12:07 -0700)]
[lldb/Reproducers] Skip tests relying on timeouts
The reproducer don't model timeouts so tests that rely on them end up
with unexpected packets during replay. Skip them until we can handle
this scenario.
Jonas Devlieghere [Wed, 27 May 2020 19:01:36 +0000 (12:01 -0700)]
[lldb/Test] Generate YAML binary in build directory
Although it's not entirely clear to me why, this test was generating its
binary in the source directory instead of the build directory. This
patch fixes that following the same approach as other tests.
Craig Topper [Wed, 27 May 2020 18:12:05 +0000 (11:12 -0700)]
[X86] Restore selection of MULX on BMI2 targets.
Looking back over gcc and icc behavior it looks like icc does
use mulx32 on 32-bit targets and mulx64 on 64-bit targets. It's
also used when dividing i32 by constant on 32-bit targets and
i64 by constant on 64-bit targets.
gcc uses it multiplies producing a 64 bit result on 32-bit targets
and 128-bit results on a 64-bit target. gcc does not appear to use
it for division by constant.
After this patch clang is closer to the icc behavior. This
basically reverts
d1c61861ddc94457b08a5a653d3908b7b38ebb22, but
there were no strong feelings at the time.
Fixes PR45518.
Differential Revision: https://reviews.llvm.org/D80498
Mircea Trofin [Thu, 14 May 2020 02:32:40 +0000 (19:32 -0700)]
[llvm]NFC] Simplify ProfileSummaryInfo state transitions
ProfileSummaryInfo is updated seldom, as result of very specific
triggers. This patch clearly demarcates state updates from read-only uses.
This, arguably, improves readability and maintainability.
Sanjay Patel [Wed, 27 May 2020 14:26:31 +0000 (10:26 -0400)]
[InstCombine] add tests for vector demanded elements of select condition; NFC
Matt Arsenault [Wed, 27 May 2020 17:25:37 +0000 (13:25 -0400)]
AMDGPU: Start adding MODE register uses to instructions
This is the groundwork required to implement strictfp. For now, this
should be NFC for regular instructoins (many instructions just gain an
extra use of a reserved register). Regalloc won't rematerialize
instructions with reads of physical registers, but we were suffering
from that anyway with the exec reads.
Should add it for all the related FP uses (possibly with some
extras). I did not add it to either the gpr index mode instructions
(or every single VALU instruction) since it's a ridiculous feature
already modeled as an arbitrary side effect.
Also work towards marking instructions with FP exceptions. This
doesn't actually set the bit yet since this would start to change
codegen. It seems nofpexcept is currently not implied from the regular
IR FP operations. Add it to some MIR tests where I think it might
matter.
John Fastabend [Wed, 27 May 2020 18:18:16 +0000 (11:18 -0700)]
[BPF] simplify zero extension with MOV_32_64
The current pattern matching for zext results in the following code snippet
being produced,
w1 = w0
r1 <<= 32
r1 >>= 32
Because BPF implementations require zero extension on 32bit loads this
both adds a few extra unneeded instructions but also makes it a bit
harder for the verifier to track the r1 register bounds. For example in
this verifier trace we see at the end of the snippet R2 offset is unknown.
However, if we track this correctly we see w1 should have the same bounds
as r8. R8 smax is less than U32 max value so a zero extend load should keep
the same value. Adding a max value of 800 (R8=inv(id=0,smax_value=800)) to
an off=0, as seen in R7 should create a max offset of 800. However at the
end of the snippet we note the R2 max offset is 0xffffFFFF.
R0=inv(id=0,smax_value=800)
R1_w=inv(id=0,umax_value=
2147483647,var_off=(0x0; 0x7fffffff))
R6=ctx(id=0,off=0,imm=0) R7=map_value(id=0,off=0,ks=4,vs=1600,imm=0)
R8_w=inv(id=0,smax_value=800,umax_value=
4294967295,var_off=(0x0; 0xffffffff))
R9=inv800 R10=fp0 fp-8=mmmm????
58: (1c) w9 -= w8
59: (bc) w1 = w8
60: (67) r1 <<= 32
61: (77) r1 >>= 32
62: (bf) r2 = r7
63: (0f) r2 += r1
64: (bf) r1 = r6
65: (bc) w3 = w9
66: (b7) r4 = 0
67: (85) call bpf_get_stack#67
R0=inv(id=0,smax_value=800)
R1_w=ctx(id=0,off=0,imm=0)
R2_w=map_value(id=0,off=0,ks=4,vs=1600,umax_value=
4294967295,var_off=(0x0; 0xffffffff))
R3_w=inv(id=0,umax_value=800,var_off=(0x0; 0x3ff))
R4_w=inv0 R6=ctx(id=0,off=0,imm=0)
R7=map_value(id=0,off=0,ks=4,vs=1600,imm=0)
R8_w=inv(id=0,smax_value=800,umax_value=
4294967295,var_off=(0x0; 0xffffffff))
R9_w=inv(id=0,umax_value=800,var_off=(0x0; 0x3ff))
R10=fp0 fp-8=mmmm????
After this patch R1 bounds are not smashed by the <<=32 >>=32 shift and we
get correct bounds on R2 umax_value=800.
Further it reduces 3 insns to 1.
Signed-off-by: John Fastabend <john.fastabend@gmail.com>
Differential Revision: https://reviews.llvm.org/D73985
Lei Huang [Wed, 27 May 2020 14:50:14 +0000 (09:50 -0500)]
[PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
Summary:
This patch simply adds support for the new CPU in anticipation of
Power10. There isn't really any functionality added so there are no
associated test cases at this time.
Reviewers: stefanp, nemanjai, amyk, hfinkel, power-llvm-team, #powerpc
Reviewed By: stefanp, nemanjai, amyk, #powerpc
Subscribers: NeHuang, steven.zhang, hiraditya, llvm-commits, wuzish, shchenz, cfe-commits, kbarton, echristo
Tags: #clang, #powerpc, #llvm
Differential Revision: https://reviews.llvm.org/D80020