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5 years ago[MS Demangler] Rework the way operators are demangled.
Zachary Turner [Fri, 17 Aug 2018 16:14:05 +0000 (16:14 +0000)]
[MS Demangler] Rework the way operators are demangled.

Previously, some of the code for actually parsing mangled
operator names was more like formatting code in nature,
and was interspersed with the demangling code which builds
the AST.  This means that by the time we got to the printing
code, we had lost all information about what type of operator
we had, and all we were left with was a string that we just
had to print.  However, not all operators are actually even
operators.  it's basically just a catch-all mangling for
"special names", and for some of the other types it helps
to know when we're actually doing the printing what it is.

This patch changes the way things work by introducing an
OperatorInfo structure and corresponding enumeration.  When
we demangle we store the enumeration value and demangled
components separately.  This gives more flexibility during
printing.

In doing so, some demanglings of special names which we didn't
previously support come out of this for free, so we now demangle
those.

A few are more complex and are better left for a followup patch
though.

An exhaustive test of every possible operator code is included,
with the ones that don't yet work commented out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340046 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[TableGen] TypeInfer - Cache the legal types as TypeSetByHwMode
Simon Pilgrim [Fri, 17 Aug 2018 15:54:07 +0000 (15:54 +0000)]
[TableGen] TypeInfer - Cache the legal types as TypeSetByHwMode

We were just caching the MVT set of legal types, then every call creating a new TypeSetByHwMode with it and passing it back on the stack. There's no need to do this - we can create and cache the whole TypeSetByHwMode once and return a const reference to it each time.

Additionally, TypeInfer::expandOverloads wasn't making use of the fact that the cache just contains a default mode containing all the types.

Saves up to 30secs in debug builds of x86 -gen-dag-isel.

Differential Revision: https://reviews.llvm.org/D50903

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340042 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[DebugInfo] Generate DWARF debug information for labels. (Fix leak problems)
Hsiangkai Wang [Fri, 17 Aug 2018 15:22:04 +0000 (15:22 +0000)]
[DebugInfo] Generate DWARF debug information for labels. (Fix leak problems)

There are two forms for label debug information in DWARF format.

1. Labels in a non-inlined function:

DW_TAG_label
  DW_AT_name
  DW_AT_decl_file
  DW_AT_decl_line
  DW_AT_low_pc

2. Labels in an inlined function:

DW_TAG_label
  DW_AT_abstract_origin
  DW_AT_low_pc

We will collect label information from DBG_LABEL. Before every DBG_LABEL,
we will generate a temporary symbol to denote the location of the label.
The symbol could be used to get DW_AT_low_pc afterwards. So, we create a
mapping between 'inlined label' and DBG_LABEL MachineInstr in DebugHandlerBase.
The DBG_LABEL in the mapping is used to query the symbol before it.

The AbstractLabels in DwarfCompileUnit is used to process labels in inlined
functions.

We also keep a mapping between scope and labels in DwarfFile to help to
generate correct tree structure of DIEs.

It also generates label debug information under global isel.

Differential Revision: https://reviews.llvm.org/D45556

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340039 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[PowerPC] Generate lxsd instead of the ld->mtvsrd sequence for vector loads
Stefan Pintilie [Fri, 17 Aug 2018 15:15:26 +0000 (15:15 +0000)]
[PowerPC] Generate lxsd instead of the ld->mtvsrd sequence for vector loads

This patch addresses:

- Implementation within PPCISelLowering.cpp to check if we should use direct
load into vector instructions (such as lxsd/lfd ) when the scalar_to_vector
function is used; which will allow us to catch as many cases of the
scalar_to_vector uses as possible to translate the ld->mtvsrd sequence into
lxsd.

- Test cases to exhibit the behaviour of emitting lxsd/lfd.

Patch by amyk

Differential revision: https://reviews.llvm.org/D49698

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340037 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[llvm-mca] Removed references to HWStallEvent in Scheduler.h. NFCI
Andrea Di Biagio [Fri, 17 Aug 2018 15:01:37 +0000 (15:01 +0000)]
[llvm-mca] Removed references to HWStallEvent in Scheduler.h. NFCI

class Scheduler should not know anything of hardware event listeners and
hardware stall events (HWStallEvent).  HWStallEvent objects should only be
constructed by pipeline stages to notify listeners of hardware events.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340036 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[x86] Fix test breaking on Darwin after r339962
Francis Visoiu Mistrih [Fri, 17 Aug 2018 14:47:01 +0000 (14:47 +0000)]
[x86] Fix test breaking on Darwin after r339962

* -march=x86-64 -> -mtriple=x86_64-unknown-linux to avoid _ prefixes to
symbols
* add -start-before to avoid running the whole codegen on the IR. I
assumed it is meant to be running after X86SpeculativeLoadHardening.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340034 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] Fix liveness information when expanding X86::EH_SjLj_LongJmp64
Francis Visoiu Mistrih [Fri, 17 Aug 2018 14:46:56 +0000 (14:46 +0000)]
[X86] Fix liveness information when expanding X86::EH_SjLj_LongJmp64

test/CodeGen/X86/shadow-stack.ll has the following machine verifier
errors:

```
*** Bad machine code: Using a killed virtual register ***
- function:    bar
- basic block: %bb.6 entry (0x7fdc81857818)
- instruction: %3:gr64 = MOV64rm killed %2:gr64, 1, $noreg, 8, $noreg
- operand 1:   killed %2:gr64

*** Bad machine code: Using a killed virtual register ***
- function:    bar
- basic block: %bb.6 entry (0x7fdc81857818)
- instruction: $rsp = MOV64rm killed %2:gr64, 1, $noreg, 16, $noreg
- operand 1:   killed %2:gr64

*** Bad machine code: Virtual register killed in block, but needed live out. ***
- function:    bar
- basic block: %bb.2 entry (0x7fdc818574f8)
Virtual register %2 is used after the block.
```

The fix here is to only copy the machine operand's register without the
kill flags for all the instructions except the very last one of the
sequence.

I had to insert dummy PHIs in the test case to force the NoPHI function
property to be set to false. More on this here: https://llvm.org/PR38439

Differential Revision: https://reviews.llvm.org/D50260

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340033 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NewGVN] Add tests for r340031.
Florian Hahn [Fri, 17 Aug 2018 14:39:53 +0000 (14:39 +0000)]
[NewGVN] Add tests for r340031.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340032 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstrSimplify,NewGVN] Add option to ignore additional instr info when simplifying.
Florian Hahn [Fri, 17 Aug 2018 14:39:04 +0000 (14:39 +0000)]
[InstrSimplify,NewGVN] Add option to ignore additional instr info when simplifying.

NewGVN uses InstructionSimplify for simplifications of leaders of
congruence classes. It is not guaranteed that the metadata or other
flags/keywords (like nsw or exact) of the leader is available for all members
in a congruence class, so we cannot use it for simplification.

This patch adds a InstrInfoQuery struct with a boolean field
UseInstrInfo (which defaults to true to keep the current behavior as
default) and a set of helper methods to get metadata/keywords for a
given instruction, if UseInstrInfo is true. The whole thing might need a
better name, to avoid confusion with TargetInstrInfo but I am not sure
what a better name would be.

The current patch threads through InstrInfoQuery to the required
places, which is messier then it would need to be, if
InstructionSimplify and ValueTracking would share the same Query struct.

The reason I added it as a separate struct is that it can be shared
between InstructionSimplify and ValueTracking's query objects. Also,
some places do not need a full query object, just the InstrInfoQuery.

It also updates some interfaces that do not take a Query object, but a
set of optional parameters to take an additional boolean UseInstrInfo.

See https://bugs.llvm.org/show_bug.cgi?id=37540.

Reviewers: dberlin, davide, efriedma, sebpop, hiraditya

Reviewed By: hiraditya

Differential Revision: https://reviews.llvm.org/D47143

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340031 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Hexagon] Expand vgather pseudos during packetization
Krzysztof Parzyszek [Fri, 17 Aug 2018 14:24:24 +0000 (14:24 +0000)]
[Hexagon] Expand vgather pseudos during packetization

This will allow packetizing the vgather expansion with other instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340028 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AtomicExpandPass] Widen partword atomicrmw or/xor/and before tryExpandAtomicRMW
Alex Bradbury [Fri, 17 Aug 2018 14:03:37 +0000 (14:03 +0000)]
[AtomicExpandPass] Widen partword atomicrmw or/xor/and before tryExpandAtomicRMW

This patch performs a widening transformation of bitwise atomicrmw
{or,xor,and} and applies it prior to tryExpandAtomicRMW. This operates
similarly to convertCmpXchgToIntegerType. For these operations, the i8/i16
atomicrmw can be implemented in terms of the 32-bit atomicrmw by appropriately
manipulating the operands. There is no functional change for the handling of
partword or/xor, but the transformation for partword 'and' is new.

The advantage of performing this transformation early is that the same
code-path can be used regardless of the approach used to expand the atomicrmw
(AtomicExpansionKind). i.e. the same logic is used for
AtomicExpansionKind::CmpXchg and can also be used by the intrinsic-based
expansion in D47882.

Differential Revision: https://reviews.llvm.org/D48129

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340027 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[LICM] Add a diagnostic analysis for identifying alias information
Anna Thomas [Fri, 17 Aug 2018 13:44:00 +0000 (13:44 +0000)]
[LICM] Add a diagnostic analysis for identifying alias information

Summary:
Currently, in LICM, we use the alias set tracker to identify if the
instruction (we're interested in hoisting) aliases with instruction that
modifies that memory location.

This patch adds an LICM alias analysis diagnostic tool that checks the
mod ref info of the instruction we are interested in hoisting/sinking,
with every instruction in the loop.  Because of O(N^2) complexity this
is now only a diagnostic tool to show the limitation we have with the
alias set tracker and is OFF by default.

Test cases show the difference with the diagnostic analysis tool, where
we're able to hoist out loads and readonly + argmemonly calls from the
loop, where the alias set tracker analysis is not able to hoist these
instructions out.

Reviewers: reames, mkazantsev, fedor.sergeev, hfinkel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D50854

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340026 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[RISCV] Remove unused function
Roger Ferrer Ibanez [Fri, 17 Aug 2018 13:40:03 +0000 (13:40 +0000)]
[RISCV] Remove unused function

This function is not virtual, it is private and it is not called anywhere. No
regression is introduced by removing it.

I think we can safely remove it.

Differential Revision: https://reviews.llvm.org/D50836

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340024 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ConstantFolding] add simplifications for funnel shift intrinsics
Sanjay Patel [Fri, 17 Aug 2018 13:23:44 +0000 (13:23 +0000)]
[ConstantFolding] add simplifications for funnel shift intrinsics

This is another step towards being able to canonicalize to the funnel shift
intrinsics in IR (see D49242 for the initial patch).
We should not have any loss of simplification power in IR between these and
the equivalent IR constructs.

Differential Revision: https://reviews.llvm.org/D50848

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340022 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[TableGen] TypeSetByHwMode::insert - cache the default MVT. NFCI.
Simon Pilgrim [Fri, 17 Aug 2018 13:03:17 +0000 (13:03 +0000)]
[TableGen] TypeSetByHwMode::insert - cache the default MVT. NFCI.

Avoids repeated count()/find() calls that we've already have the default values for.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340020 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AArch64] - Generate pointer authentication instructions
Luke Cheeseman [Fri, 17 Aug 2018 12:53:22 +0000 (12:53 +0000)]
[AArch64] - Generate pointer authentication instructions

- Generate pointer authentication instructions
- The functions instrumented depend on function attribtues:
  all (all functions instrumentent)
  non-leaf (only those that spill LR)
  none
- Function epilogues sign the LR before spilling to the stack and authenticate
  the LR once restored
- If the target is v8.3a or greater than can use the combined authenticate and
  return instruction

Differential revision: https://reviews.llvm.org/D49793

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340018 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoRevert extraneous directory added by accident in rL340016
Nemanja Ivanovic [Fri, 17 Aug 2018 12:41:49 +0000 (12:41 +0000)]
Revert extraneous directory added by accident in rL340016

It appears that the way this patch was produced ended up creating an
extra 'llvm' directory where the test was placed. When I committed the
patch, that directory ended up being created upstream. This commit should
revert that.
Sorry for the noise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340017 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction
Nemanja Ivanovic [Fri, 17 Aug 2018 12:35:44 +0000 (12:35 +0000)]
[PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction

Add a DAG combine for the PowerPC code generator to generate the Power9 extswsli
extend sign and shift immediate instruction.

Patch by RolandF.

Differential revision: https://reviews.llvm.org/D49879

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340016 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[DAGCombiner] extractShiftForRotate - fix out of range shift issue
Simon Pilgrim [Fri, 17 Aug 2018 12:25:18 +0000 (12:25 +0000)]
[DAGCombiner] extractShiftForRotate - fix out of range shift issue

Don't just check for negative shift amounts.

Fixes OSS Fuzz #9935
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=9935

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340015 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] Remove unused method FAddCombine::createFDiv(). NFC
Andrea Di Biagio [Fri, 17 Aug 2018 11:33:48 +0000 (11:33 +0000)]
[InstCombine] Remove unused method FAddCombine::createFDiv(). NFC

This commit fixes a (gcc 7.3.0) [-Wunused-function] warning caused by the
presence of unused method FaddCombine::createFDiv().
The last use of that method was removed at r339519.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340014 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM/AArch64] Support FP16 +fp16fml instructions
Bernard Ogden [Fri, 17 Aug 2018 11:29:49 +0000 (11:29 +0000)]
[ARM/AArch64] Support FP16 +fp16fml instructions

Add +fp16fml feature for new FP16 instructions, which are a
mandatory part of FP16 from v8.4-A and an optional part of FP16
from v8.2-A. It doesn't seem to be possible to model this in
LLVM, but the relationship between the options is handled by
the related clang patch.

In keeping with what I think is the usual practice, the fp16fml
extension is accepted regardless of base architecture version.

Builds on/replaces Sjoerd Meijer's patch to add these instructions at
https://reviews.llvm.org/D49839.

Differential Revision: https://reviews.llvm.org/D50228

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340013 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM/AArch64] TargetParserTest fixes
Bernard Ogden [Fri, 17 Aug 2018 11:26:57 +0000 (11:26 +0000)]
[ARM/AArch64] TargetParserTest fixes

Adds some missing tests for the FP16 extension,
fixes an existing test that misnames it.

Differential Revision: https://reviews.llvm.org/D50227

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340012 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) folding
Simon Pilgrim [Fri, 17 Aug 2018 10:52:49 +0000 (10:52 +0000)]
[DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) folding

Add support for cases where only some c1+c2 results exceed the max bitshift, clamping accordingly.

Differential Revision: https://reviews.llvm.org/D35722

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340010 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Sparc] Get sret arg size from CallLoweringInfo.getArgs()
Daniel Cederman [Fri, 17 Aug 2018 10:40:00 +0000 (10:40 +0000)]
[Sparc] Get sret arg size from CallLoweringInfo.getArgs()

Summary:
Looking at the callee argument list, as is done now, might not work if
the function has been typecasted into one that is expected to return
a struct. This change also simplifies the code.

The isFP128ABICall() function can be removed as it is no longer needed.
The test in fp128.ll has been updated to verify this.

Reviewers: jyknight, venkatra

Reviewed By: jyknight

Subscribers: fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D48117

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340008 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix "control reaches end of non-void function" -Wreturn-type warning. NFCI.
Simon Pilgrim [Fri, 17 Aug 2018 09:47:52 +0000 (09:47 +0000)]
Fix "control reaches end of non-void function" -Wreturn-type warning. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340006 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Sparc] Flush register windows for @llvm.returnaddress(1)
Daniel Cederman [Fri, 17 Aug 2018 09:18:31 +0000 (09:18 +0000)]
[Sparc] Flush register windows for @llvm.returnaddress(1)

Summary: When @llvm.returnaddress is called with a value higher than 0
it needs to read from the call stack to get the return address. This
means that the register windows needs to be flushed to the stack to
guarantee that the data read is valid. For values higher than 1 this
is done indirectly by the call to getFRAMEADDR(), but not for the value 1.

Reviewers: jyknight, venkatra

Reviewed By: jyknight

Subscribers: fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D48636

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340003 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MISC]Fix wrong usage of std::equal()
Chen Zheng [Fri, 17 Aug 2018 07:51:01 +0000 (07:51 +0000)]
[MISC]Fix wrong usage of std::equal()
Differential Revision: https://reviews.llvm.org/D49958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340000 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM][NFC] ARMCodeGenPrepare: some refactoring and algorithm description
Sjoerd Meijer [Fri, 17 Aug 2018 07:34:01 +0000 (07:34 +0000)]
[ARM][NFC] ARMCodeGenPrepare: some refactoring and algorithm description

Differential Revision: https://reviews.llvm.org/D50846

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339997 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MustExecute] Fix algorithmic bug in isGuaranteedToExecute. PR38514
Max Kazantsev [Fri, 17 Aug 2018 06:19:17 +0000 (06:19 +0000)]
[MustExecute] Fix algorithmic bug in isGuaranteedToExecute. PR38514

The description of `isGuaranteedToExecute` does not correspond to its implementation.
According to description, it should return `true` if an instruction is executed under the
assumption that its loop is *entered*. However there is a sophisticated alrogithm inside
that tries to prove that the instruction is executed if the loop is *exited*, which is not the
same thing for infinite loops. There is an attempt to protect from dealing with infinite loops
by prohibiting loops without exit blocks, however an infinite loop can have exit blocks.

As result of that, MustExecute can falsely consider some blocks that are never entered as
mustexec, and LICM can hoist dangerous instructions out of them basing on this fact.
This may introduce UB to programs which did not contain it initially.

This patch removes the problematic algorithm and replaced it with a one which tries to
prove what is required in description.

Differential Revision: https://reviews.llvm.org/D50558
Reviewed By: reames

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339984 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC] Add tests to ensure that improvement of MustThrow analysis will not lead to...
Max Kazantsev [Fri, 17 Aug 2018 05:20:25 +0000 (05:20 +0000)]
[NFC] Add tests to ensure that improvement of MustThrow analysis will not lead to problems in future

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339983 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoRevert r339977: [GISel]: Add Opcodes for a few LLVM Intrinsics
Chandler Carruth [Fri, 17 Aug 2018 04:47:16 +0000 (04:47 +0000)]
Revert r339977: [GISel]: Add Opcodes for a few LLVM Intrinsics

This is breaking ~all the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339982 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[llvm-mc-assemble-fuzzer] Update API - Pass MCObjectWriter instead of a stream
Brian Cain [Fri, 17 Aug 2018 04:38:41 +0000 (04:38 +0000)]
[llvm-mc-assemble-fuzzer] Update API - Pass MCObjectWriter instead of a stream

Fixes build breakage of llvm-mc-assemble-fuzzer introduced by r332749.

Fix provided by pbhatu (Pratik Bhatu)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339981 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Support] Add a public API to allow clearing all (static) timer groups.
Graydon Hoare [Fri, 17 Aug 2018 04:13:19 +0000 (04:13 +0000)]
[Support] Add a public API to allow clearing all (static) timer groups.

Summary:
Formerly, all timer groups were automatically cleared when printed out. In
https://reviews.llvm.org/rL324788 this behaviour was changed to not-clearing
timers on printout, to allow printing timers more than once, but as a result
clients (specifically Swift) that relied on the clear-on-print behaviour to
inhibit duplicate timer printing on shutdown were broken.

Rather than revert that change, this change adds a new API that enables
clients that _want_ to clear all timers to do so explicitly.

Reviewers: george.karpenkov, thegameg

Reviewed By: george.karpenkov

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D50874

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339980 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[GISel]: Add Opcodes for a few LLVM Intrinsics
Aditya Nandakumar [Fri, 17 Aug 2018 01:41:56 +0000 (01:41 +0000)]
[GISel]: Add Opcodes for a few LLVM Intrinsics

https://reviews.llvm.org/D50401

Add opcodes for llvm.intrinsic.trunc, round, and update the IRTranslator
for the same.

Reviewed by: dsanders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339977 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ADT] Replace a member initializer of a union with an explicit
Chandler Carruth [Fri, 17 Aug 2018 01:10:33 +0000 (01:10 +0000)]
[ADT] Replace a member initializer of a union with an explicit
constructor.

This breaking an old/weird host compiler is my best bet for the current
crashes I'm getting from bots since this functionality was added to this
ADT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339975 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[WebAssembly] Modify LateEHPrepare one-line description (NFC)
Heejin Ahn [Fri, 17 Aug 2018 00:12:04 +0000 (00:12 +0000)]
[WebAssembly] Modify LateEHPrepare one-line description (NFC)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339972 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoDebugInfo: Remove command line (& target-based) disabling of pubnames in favor of...
David Blaikie [Thu, 16 Aug 2018 23:57:15 +0000 (23:57 +0000)]
DebugInfo: Remove command line (& target-based) disabling of pubnames in favor of metadata

Now that Clang disables NVPTX pubnames via metadata there's no need for
this fallback to target detection in the backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339970 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[WebAssembly] CFG stackify support for exception handling
Heejin Ahn [Thu, 16 Aug 2018 23:50:59 +0000 (23:50 +0000)]
[WebAssembly] CFG stackify support for exception handling

Summary:
This adds support for exception handling to CFGStackify pass. This only
adds TRY / END_TRY markers and DOES NOT yet fix unwind mismatches that
can be created by the linearization of the CFG into the structural wasm
format. The mismatch fix will be added by following patches.

In detail, this patch
- Added support for TRY / END_TRY markers to support EH
- Changed many static functions into class member functions as they take
too many arguments now
- Added several more bookeeping data structures
- Refactored routines that decide where to insert markers, because
without refactoring this got too complicated as we added support for new
kinds of markers (TRY/END_TRY).
- Rewrote rethrow instructions' BB arguments to relative depths in EH
pad stack.

Reviewers: dschuff, sunfish

Subscribers: sbc100, jgravelle-google, llvm-commits

Differential Revision: https://reviews.llvm.org/D48273

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339967 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[x86/MIR] Implement support for pre- and post-instruction symbols, as
Chandler Carruth [Thu, 16 Aug 2018 23:11:05 +0000 (23:11 +0000)]
[x86/MIR] Implement support for pre- and post-instruction symbols, as
well as MIR parsing support for `MCSymbol` `MachineOperand`s.

The only real way to test pre- and post-instruction symbol support is to
use them in operands, so I ended up implementing that within the patch
as well. I can split out the operand support if folks really want but it
doesn't really seem worth it.

The functional implementation of pre- and post-instruction symbols is
now *completely trivial*. Two tiny bits of code in the (misnamed)
AsmPrinter. It should be completely target independent as well. We emit
these exactly the same way as we emit basic block labels. Most of the
code here is to give full dumping, MIR printing, and MIR parsing support
so that we can write useful tests.

The MIR parsing of MC symbol operands still isn't 100%, as it forces the
symbols to be non-temporary and non-local symbols with names. However,
those names often can encode most (if not all) of the special semantics
desired, and unnamed symbols seem especially annoying to serialize and
de-serialize. While this isn't perfect or full support, it seems plenty
to write tests that exercise usage of these kinds of operands.

The MIR support for pre-and post-instruction symbols was quite
straightforward. I chose to print them out in an as-if-operand syntax
similar to debug locations as this seemed the cleanest way and let me
use nice introducer tokens rather than inventing more magic punctuation
like we use for memoperands.

However, supporting MIR-based parsing of these symbols caused me to
change the design of the symbol support to allow setting arbitrary
symbols. Without this, I don't see any reasonable way to test things
with MIR.

Differential Revision: https://reviews.llvm.org/D50833

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339962 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] add reflection fold for tan(-x)
Sanjay Patel [Thu, 16 Aug 2018 22:46:20 +0000 (22:46 +0000)]
[InstCombine] add reflection fold for tan(-x)

This is a follow-up suggested with rL339604.
For tan(), we don't have a corresponding LLVM
intrinsic -- unlike sin/cos -- so this is the
only way/place that we can do this fold currently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339958 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstrProf] Use atomic profile counter updates for TSan
Vedant Kumar [Thu, 16 Aug 2018 22:24:47 +0000 (22:24 +0000)]
[InstrProf] Use atomic profile counter updates for TSan

Thread sanitizer instrumentation fails to skip all loads and stores to
profile counters. This can happen if profile counter updates are merged:

  %.sink = phi i64* ...
  %pgocount5 = load i64, i64* %.sink
  %27 = add i64 %pgocount5, 1
  %28 = bitcast i64* %.sink to i8*
  call void @__tsan_write8(i8* %28)
  store i64 %27, i64* %.sink

To suppress TSan diagnostics about racy counter updates, make the
counter updates atomic when TSan is enabled. If there's general interest
in this mode it can be surfaced as a clang/swift driver option.

Testing: check-{llvm,clang,profile}

rdar://40477803

Differential Revision: https://reviews.llvm.org/D50867

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339955 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] add tests for tan with negated arg; NFC
Sanjay Patel [Thu, 16 Aug 2018 22:05:51 +0000 (22:05 +0000)]
[InstCombine] add tests for tan with negated arg; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339953 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoUpdate MemorySSA in Local utils removing blocks.
Alina Sbirlea [Thu, 16 Aug 2018 21:58:44 +0000 (21:58 +0000)]
Update MemorySSA in Local utils removing blocks.

Summary: Extend Local utils to update MemorySSA.

Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits

Differential Revision: https://reviews.llvm.org/D48790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339951 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[docs] Try to clarify the FuzzingLLVM docs
Justin Bogner [Thu, 16 Aug 2018 21:55:09 +0000 (21:55 +0000)]
[docs] Try to clarify the FuzzingLLVM docs

Try to improve these docs based on some recent questions that were
sent to llvm-dev:

  http://lists.llvm.org/pipermail/llvm-dev/2018-August/125329.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339949 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[DomTree] Add constructor to create a new DT based on current DT/CFG and a set of...
Alina Sbirlea [Thu, 16 Aug 2018 21:54:33 +0000 (21:54 +0000)]
[DomTree] Add constructor to create a new DT based on current DT/CFG and a set of Updates.

Summary:
Add the posibility of creating a new DT using a set of Updates.
This will essentially create a DT based on a CFG snapshot/view.

Additional refactoring for either this patch or follow-ups:
- create an utility for building BUI.
- replace BUI with a GraphDiff.

Reviewers: kuhar

Subscribers: sanjoy, jlebar, llvm-commits

Differential Revision: https://reviews.llvm.org/D50671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339947 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[DAGCombiner] Don't reassociate operations that have the vector reduction flag set.
Craig Topper [Thu, 16 Aug 2018 21:54:05 +0000 (21:54 +0000)]
[DAGCombiner] Don't reassociate operations that have the vector reduction flag set.

When nodes are reassociated the vector-reduction flag gets lost.

The test case is here is what would happen if you had a sum of absolute differences loop that started with a non-zero but contant sum and that loop was unrolled. The vectorizer will generate a constant vector for the initial value. And DAGCombiner reassociate tries to move it down the addition tree erasing the vector-reduction flag. Interestingly this moves constants the opposite direction of the reassociate IR pass.

I've chosen to just punt on the reassociate, but I suppose we could maybe preserve the flag if both nodes have it set.

Differential Revision: https://reviews.llvm.org/D50827

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339946 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] In EFLAGS copy pass, don't emit EXTRACT_SUBREG instructions since we're after...
Craig Topper [Thu, 16 Aug 2018 21:54:02 +0000 (21:54 +0000)]
[X86] In EFLAGS copy pass, don't emit EXTRACT_SUBREG instructions since we're after peephole

Normally the peephole pass converts EXTRACT_SUBREG to COPY instructions. But we're after peephole so we can't rely on it to clean these up.

To fix this, the eflags pass now emits a COPY with a subreg input.

I also noticed that in 32-bit mode we need to constrain the input to the copy to ensure the subreg is valid. Otherwise we'll fail verify-machineinstrs

Differential Revision: https://reviews.llvm.org/D50656

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339945 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFactor Node creation out of the demangler. No functionality change
Richard Smith [Thu, 16 Aug 2018 21:40:57 +0000 (21:40 +0000)]
Factor Node creation out of the demangler. No functionality change
intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339944 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MC] Improve COFF associative section lookup
Reid Kleckner [Thu, 16 Aug 2018 21:34:41 +0000 (21:34 +0000)]
[MC] Improve COFF associative section lookup

Handle the case when the symbol is private. Private symbols are not in
the COFF object file symbol table, so they aren't inserted into
SymbolMap. We can't look up the section of the symbol that way. Instead,
get the MCSection from the MCSymbol and map that to the object file
section.

Print a better error message when the symbol has no section, like when
the symbol is undefined.

Fixes PR38607

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339942 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MI] Change the array of `MachineMemOperand` pointers to be
Chandler Carruth [Thu, 16 Aug 2018 21:30:05 +0000 (21:30 +0000)]
[MI] Change the array of `MachineMemOperand` pointers to be
a generically extensible collection of extra info attached to
a `MachineInstr`.

The primary change here is cleaning up the APIs used for setting and
manipulating the `MachineMemOperand` pointer arrays so chat we can
change how they are allocated.

Then we introduce an extra info object that using the trailing object
pattern to attach some number of MMOs but also other extra info. The
design of this is specifically so that this extra info has a fixed
necessary cost (the header tracking what extra info is included) and
everything else can be tail allocated. This pattern works especially
well with a `BumpPtrAllocator` which we use here.

I've also added the basic scaffolding for putting interesting pointers
into this, namely pre- and post-instruction symbols. These aren't used
anywhere yet, they're just there to ensure I've actually gotten the data
structure types correct. I'll flesh out support for these in
a subsequent patch (MIR dumping, parsing, the works).

Finally, I've included an optimization where we store any single pointer
inline in the `MachineInstr` to avoid the allocation overhead. This is
expected to be the overwhelmingly most common case and so should avoid
any memory usage growth due to slightly less clever / dense allocation
when dealing with >1 MMO. This did require several ergonomic
improvements to the `PointerSumType` to reasonably support the various
usage models.

This also has a side effect of freeing up 8 bits within the
`MachineInstr` which could be repurposed for something else.

The suggested direction here came largely from Hal Finkel. I hope it was
worth it. ;] It does hopefully clear a path for subsequent extensions
w/o nearly as much leg work. Lots of thanks to Reid and Justin for
careful reviews and ideas about how to do all of this.

Differential Revision: https://reviews.llvm.org/D50701

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339940 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoDebugInfo: Add metadata support for disabling DWARF pub sections
David Blaikie [Thu, 16 Aug 2018 21:29:55 +0000 (21:29 +0000)]
DebugInfo: Add metadata support for disabling DWARF pub sections

In cases where the debugger load time is a worthwhile tradeoff (or less
costly - such as loading from a DWP instead of a variety of DWOs
(possibly over a high-latency/distributed filesystem)) against object
file size, it can be reasonable to disable pubnames and corresponding
gdb-index creation in the linker.

A backend-flag version of this was implemented for NVPTX in
D44385/r327994 - which was fine for NVPTX which wouldn't mix-and-match
CUs. Now that it's going to be a user-facing option (likely powered by
"-gno-pubnames", the same as GCC) it should be encoded in the
DICompileUnit so it can vary per-CU.

After this, likely the NVPTX support should be migrated to the metadata
& the previous flag implementation should be removed.

Reviewers: aprantl

Differential Revision: https://reviews.llvm.org/D50213

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339939 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoadd a missed case for binary op FMF propagation under select folds
Michael Berg [Thu, 16 Aug 2018 20:59:45 +0000 (20:59 +0000)]
add a missed case for binary op FMF propagation under select folds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339938 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AST] Speculative build fix for a polly buildbot
Philip Reames [Thu, 16 Aug 2018 20:58:48 +0000 (20:58 +0000)]
[AST] Speculative build fix for a polly buildbot

I don't have polly setup to bulld locally and don't plan to.  This should let the old API adapt to the new one.  Can someone from polly please migrate usage and then delete the wrapper?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339937 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MemLoc] Fix a bug causing any use of invariant.end to crash in LICM
Philip Reames [Thu, 16 Aug 2018 20:48:55 +0000 (20:48 +0000)]
[MemLoc] Fix a bug causing any use of invariant.end to crash in LICM

The fix is fairly simple, but is says something unpleasant about the usage and testing of invariant.start/end scopes that this went undetected.  To put this in perspective, *any* invariant.end in a loop flowing through LICM crashed.  I haven't bothered to figure out just how far back this goes, but it's not caused by any of the recent changes.  We're probably talking months if not years.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339936 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[SystemZ] Require asserts in subregliveness-06.mir
Krzysztof Parzyszek [Thu, 16 Aug 2018 20:12:15 +0000 (20:12 +0000)]
[SystemZ] Require asserts in subregliveness-06.mir

The option -misched=shuffle is only available with !NDEBUG builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339931 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[LICM][NFC] Restructure pointer invalidation API in terms of MemoryLocation
Philip Reames [Thu, 16 Aug 2018 20:11:15 +0000 (20:11 +0000)]
[LICM][NFC] Restructure pointer invalidation API in terms of MemoryLocation

Main value is just simplifying code.  I'll further simply the argument handling case in a bit, but that involved a slightly orthogonal change so I went with the mildy ugly intermediate for this patch.

Note that the isSized check in the old LICM code was not carried across.  It turns out that check was dead.  a) no test exercised it, and b) langref and verifier had been updated to disallow unsized types used in loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339930 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[llvm-mca] Fix -Wpessimizing-move warnings introduced by r339923.
Andrea Di Biagio [Thu, 16 Aug 2018 19:45:13 +0000 (19:45 +0000)]
[llvm-mca] Fix -Wpessimizing-move warnings introduced by r339923.

Reported by buildbot `clang-with-lto-ubuntu` ( build #9858 ).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339928 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAdd missing test file from r339799.
Peter Collingbourne [Thu, 16 Aug 2018 19:29:01 +0000 (19:29 +0000)]
Add missing test file from r339799.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339927 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] Pre-commit test case for D50827.
Craig Topper [Thu, 16 Aug 2018 19:27:43 +0000 (19:27 +0000)]
[X86] Pre-commit test case for D50827.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339926 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[WebAssembly] Remove temporary workaround for function bitcasts
Jacob Gravelle [Thu, 16 Aug 2018 19:24:31 +0000 (19:24 +0000)]
[WebAssembly] Remove temporary workaround for function bitcasts

Summary:
EM_ASM no longer is lowered as varargs in C, so this workaround is
obsolete.

Reviewers: dschuff, sunfish

Subscribers: sbc100, aheejin, llvm-commits

Differential Revision: https://reviews.llvm.org/D50859

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339925 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MachineVerifier] Check if predecessor is jointly dominated by undefs
Krzysztof Parzyszek [Thu, 16 Aug 2018 19:13:28 +0000 (19:13 +0000)]
[MachineVerifier] Check if predecessor is jointly dominated by undefs

Each use of a value should be jointly dominated by the union of defs and
undefs. It can happen that it will only be jointly dominated by undefs,
and that is still legal. Make sure that the verifier is aware of that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339924 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[llvm-mca] Refactor how execution is orchestrated by the Pipeline.
Andrea Di Biagio [Thu, 16 Aug 2018 19:00:48 +0000 (19:00 +0000)]
[llvm-mca] Refactor how execution is orchestrated by the Pipeline.

This patch changes how instruction execution is orchestrated by the Pipeline.
In particular, this patch makes it more explicit how instructions transition
through the various pipeline stages during execution.

The main goal is to simplify both the stage API and the Pipeline execution.  At
the same time, this patch fixes some design issues which are currently latent,
but that are likely to cause problems in future if people start defining custom
pipelines.

The new design assumes that each pipeline stage knows the "next-in-sequence".
The Stage API has gained three new methods:
 -   isAvailable(IR)
 -   checkNextStage(IR)
 -   moveToTheNextStage(IR).

An instruction IR can be executed by a Stage if method `Stage::isAvailable(IR)`
returns true.
Instructions can move to next stages using method moveToTheNextStage(IR).
An instruction cannot be moved to the next stage if method checkNextStage(IR)
(called on the current stage) returns false.
Stages are now responsible for moving instructions to the next stage in sequence
if necessary.

Instructions are allowed to transition through multiple stages during a single
cycle (as long as stages are available, and as long as all the calls to
`checkNextStage(IR)` returns true).

Methods `Stage::preExecute()` and `Stage::postExecute()` have now become
redundant, and those are removed by this patch.

Method Pipeline::runCycle() is now simpler, and it correctly visits stages
on every begin/end of cycle.

Other changes:
 - DispatchStage no longer requires a reference to the Scheduler.
 - ExecuteStage no longer needs to directly interact with the
   RetireControlUnit. Instead, executed instructions are now directly moved to the
   next stage (i.e. the retire stage).
 - RetireStage gained an execute method. This allowed us to remove the
   dependency with the RCU in ExecuteStage.
 - FecthStage now updates the "program counter" during cycleBegin() (i.e.
   before we start executing new instructions).
 - We no longer need Stage::Status to be returned by method execute(). It has
   been dropped in favor of a more lightweight llvm::Error.

Overally, I measured a ~11% performance gain w.r.t. the previous design.  I also
think that the Stage interface is probably easier to read now.  That being said,
code comments have to be improved, and I plan to do it in a follow-up patch.

Differential revision: https://reviews.llvm.org/D50849

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339923 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[SelectionDAG] Improve the legalisation lowering of UMULO.
Eli Friedman [Thu, 16 Aug 2018 18:39:39 +0000 (18:39 +0000)]
[SelectionDAG] Improve the legalisation lowering of UMULO.

There is no way in the universe, that doing a full-width division in
software will be faster than doing overflowing multiplication in
software in the first place, especially given that this same full-width
multiplication needs to be done anyway.

This patch replaces the previous implementation with a direct lowering
into an overflowing multiplication algorithm based on half-width
operations.

Correctness of the algorithm was verified by exhaustively checking the
output of this algorithm for overflowing multiplication of 16 bit
integers against an obviously correct widening multiplication. Baring
any oversights introduced by porting the algorithm to DAG, confidence in
correctness of this algorithm is extremely high.

Following table shows the change in both t = runtime and s = space. The
change is expressed as a multiplier of original, so anything under 1 is
“better” and anything above 1 is worse.

+-------+-----------+-----------+-------------+-------------+
| Arch  | u64*u64 t | u64*u64 s | u128*u128 t | u128*u128 s |
+-------+-----------+-----------+-------------+-------------+
|   X64 |     -     |     -     |    ~0.5     |    ~0.64    |
|  i686 |   ~0.5    |   ~0.6666 |    ~0.05    |    ~0.9     |
| armv7 |     -     |   ~0.75   |      -      |    ~1.4     |
+-------+-----------+-----------+-------------+-------------+

Performance numbers have been collected by running overflowing
multiplication in a loop under `perf` on two x86_64 (one Intel Haswell,
other AMD Ryzen) based machines. Size numbers have been collected by
looking at the size of function containing an overflowing multiply in
a loop.

All in all, it can be seen that both performance and size has improved
except in the case of armv7 where code size has regressed for 128-bit
multiply. u128*u128 overflowing multiply on 32-bit platforms seem to
benefit from this change a lot, taking only 5% of the time compared to
original algorithm to calculate the same thing.

The final benefit of this change is that LLVM is now capable of lowering
the overflowing unsigned multiply for integers of any bit-width as long
as the target is capable of lowering regular multiplication for the same
bit-width. Previously, 128-bit overflowing multiply was the widest
possible.

Patch by Simonas Kazlauskas!

Differential Revision: https://reviews.llvm.org/D50310

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339922 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[llvm-strip] Add support for -p/--preserve-dates
Jordan Rupprecht [Thu, 16 Aug 2018 18:29:40 +0000 (18:29 +0000)]
[llvm-strip] Add support for -p/--preserve-dates

Summary: [llvm-strip] Preserve access/modification timestamps when -p is used.

Reviewers: jakehehrlich, jhenderson, alexshap

Reviewed By: jhenderson

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D50744

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339921 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[RegisterCoalescer] Shrink to uses if needed after removeCopyByCommutingDef
Krzysztof Parzyszek [Thu, 16 Aug 2018 18:02:59 +0000 (18:02 +0000)]
[RegisterCoalescer] Shrink to uses if needed after removeCopyByCommutingDef

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339912 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix memory leak in demangling of string literals.
Zachary Turner [Thu, 16 Aug 2018 17:48:32 +0000 (17:48 +0000)]
Fix memory leak in demangling of string literals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339909 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[TargetLowering] Add support for non-uniform vectors to BuildSDIV
Simon Pilgrim [Thu, 16 Aug 2018 17:44:33 +0000 (17:44 +0000)]
[TargetLowering] Add support for non-uniform vectors to BuildSDIV

This patch refactors the existing TargetLowering::BuildSDIV base implementation to support non-uniform constant vector denominators.

This is the last patch necessary to close PR36545

Differential Revision: https://reviews.llvm.org/D50765

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339908 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[codeview] Use push_macro to avoid conflicts instead of a prefix
Reid Kleckner [Thu, 16 Aug 2018 17:34:31 +0000 (17:34 +0000)]
[codeview] Use push_macro to avoid conflicts instead of a prefix

Summary:
This prefix was added in r333421, and it changed our dumper output to
say things like "CVRegEAX" instead of just "EAX". That's a functional
change that I'd rather avoid.

I tested GCC, Clang, and MSVC, and all of them support #pragma
push_macro. They don't issue warnings whem the macro is not defined
either.

I don't have a Mac so I can't test the real termios.h header, but I
looked at the termios.h sources online and looked for other conflicts.
I saw only the CR* macros, so those are the ones we work around.

Reviewers: zturner, JDevlieghere

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D50851

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339907 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MC] Cleanup noop default case spelling. NFC.
Nirav Dave [Thu, 16 Aug 2018 17:22:31 +0000 (17:22 +0000)]
[MC] Cleanup noop default case spelling. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339906 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoRevert "unittests: Don't install TestPlugin.so"
Tom Stellard [Thu, 16 Aug 2018 17:15:03 +0000 (17:15 +0000)]
Revert "unittests: Don't install TestPlugin.so"

This reverts commit r339897.

This breaks the build on Windows and platforms where loadable modules
aren't supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339903 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Custom lower fexp
Matt Arsenault [Thu, 16 Aug 2018 17:07:52 +0000 (17:07 +0000)]
AMDGPU: Custom lower fexp

This will allow the library to just use __builtin_expf directly
without expanding this itself. Note f64 still won't work because
there is no exp instruction for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339902 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86][SSE] Add sdiv by nonuniform constant vector test containing -1/+1 and all-bits...
Simon Pilgrim [Thu, 16 Aug 2018 17:07:41 +0000 (17:07 +0000)]
[X86][SSE] Add sdiv by nonuniform constant vector test containing -1/+1 and all-bits style constants

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339901 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC] Fix typo in test cases
Evandro Menezes [Thu, 16 Aug 2018 17:03:22 +0000 (17:03 +0000)]
[NFC] Fix typo in test cases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339900 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[TargetLowering] Refactor BuildSDIV in preparation for D50765. NFCI.
Simon Pilgrim [Thu, 16 Aug 2018 16:54:06 +0000 (16:54 +0000)]
[TargetLowering] Refactor BuildSDIV in preparation for D50765. NFCI.

Pull out magic factor calculators into a helper function, use 0/+1/-1 multiplication factor to (optionally) add/sub the numerator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339898 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agounittests: Don't install TestPlugin.so
Tom Stellard [Thu, 16 Aug 2018 16:53:06 +0000 (16:53 +0000)]
unittests: Don't install TestPlugin.so

Summary:
add_llvm_loadable_module adds an install target by default, but this
module is only used for a unit test, so we don't need to install it.

Reviewers: philip.pfaffe, thakis

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D50668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339897 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MC] Remove unused variable
Benjamin Kramer [Thu, 16 Aug 2018 16:50:23 +0000 (16:50 +0000)]
[MC] Remove unused variable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339896 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MC][X86] Enhance X86 Register expression handling to more closely match GCC.
Nirav Dave [Thu, 16 Aug 2018 16:31:14 +0000 (16:31 +0000)]
[MC][X86] Enhance X86 Register expression handling to more closely match GCC.

Allow the comparison of x86 registers in the evaluation of assembler
directives. This generalizes and simplifies the extension from r334022
to catch another case found in the Linux kernel.

Reviewers: rnk, void

Reviewed By: rnk

Subscribers: hiraditya, nickdesaulniers, llvm-commits

Differential Revision: https://reviews.llvm.org/D50795

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339895 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix -Wmicrosoft-goto warnings.
Zachary Turner [Thu, 16 Aug 2018 16:30:27 +0000 (16:30 +0000)]
Fix -Wmicrosoft-goto warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339894 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAdd support for AVX-512 CodeView registers.
Zachary Turner [Thu, 16 Aug 2018 16:17:55 +0000 (16:17 +0000)]
Add support for AVX-512 CodeView registers.

When compiling with /arch:AVX512 and optimizations turned on,
we could crash while emitting debug info because we did not
have CodeView register constants for the AVX 512 register
set defined.  This patch defines them.

Differential Revision: https://reviews.llvm.org/D50819

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339893 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MS Demangler] Demangle string literals.
Zachary Turner [Thu, 16 Aug 2018 16:17:36 +0000 (16:17 +0000)]
[MS Demangler] Demangle string literals.

When demangling string literals, Microsoft's undname
simply prints 'string'.  This patch implements string
literal demangling while doing a bit better than this
by decoding as much of the string as possible and
trying to faithfully reproduce the original string
literal definition.

This is a bit tricky because the different character
types char, char16_t, and char32_t are not uniquely
identified by the mangling, so we have to use a
heuristic to try to guess the character type.  But
it works pretty well, and many tests are added to
illustrate the behavior.

Differential Revision: https://reviews.llvm.org/D50806

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339892 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MS Demangler] Don't fail on MD5-mangled names.
Zachary Turner [Thu, 16 Aug 2018 16:17:17 +0000 (16:17 +0000)]
[MS Demangler] Don't fail on MD5-mangled names.

When we have an MD5 mangled name, we shouldn't choke and say
that it's an invalid name.  Even though it's impossible to demangle,
we should just output the original name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339891 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[TableGen] TypeSetByHwMode::operator== optimization
Simon Pilgrim [Thu, 16 Aug 2018 16:16:28 +0000 (16:16 +0000)]
[TableGen] TypeSetByHwMode::operator== optimization

This operator is called a great deal, by checking for the cheap isSimple equality cases first (a common occurrence) we can improve performance as we avoid a lot of std::map find/iteration in hasDefault.

isSimple also means that a default value is present, so we can avoid some hasDefault calls.

This also avoids a rather dodgy piece of logic that was checking for isSimple() && !VTS.isSimple() but not the inverse - it now uses the general hasDefault mode comparison test instead.

Saves around 15secs in debug builds of x86 -gen-dag-isel.

Differential Revision: https://reviews.llvm.org/D50841

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339890 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ConstantFolding] add tests for funnel shift intrinsics; NFC
Sanjay Patel [Thu, 16 Aug 2018 16:10:42 +0000 (16:10 +0000)]
[ConstantFolding] add tests for funnel shift intrinsics; NFC

No functionality for this yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339889 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[TableGen] Avoid self getPredicates() != comparison. NFCI.
Simon Pilgrim [Thu, 16 Aug 2018 16:04:05 +0000 (16:04 +0000)]
[TableGen] Avoid self getPredicates() != comparison. NFCI.

We were performing a completely unnecessary full comparison of the same std::vector<Predicate>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339888 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] Expand the simplification of pow(x, 0.5) to sqrt(x)
Evandro Menezes [Thu, 16 Aug 2018 15:58:08 +0000 (15:58 +0000)]
[InstCombine] Expand the simplification of pow(x, 0.5) to sqrt(x)

Expand the number of cases when `pow(x, 0.5)` is simplified into `sqrt(x)`
by considering the math semantics with more granularity.

Differential revision: https://reviews.llvm.org/D50036

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339887 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[llvm-mca] Small refactoring in preparation for another patch that will improve the...
Andrea Di Biagio [Thu, 16 Aug 2018 15:43:09 +0000 (15:43 +0000)]
[llvm-mca] Small refactoring in preparation for another patch that will improve the modularity of the Pipeline. NFCI

The main difference is that now `cycleStart()` and `cycleEnd()` return an
llvm::Error.

This patch implements a few minor style changes, and adds missing 'const' to
some methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339885 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass...
Simon Pilgrim [Thu, 16 Aug 2018 15:29:24 +0000 (15:29 +0000)]
[TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass::getValueTypeNum

Avoids costly std::map copies inside ValueTypeByHwMode constructor

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339884 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[cmake] Prevent LLVMgold.so from being unloaded on Linux
Hans Wennborg [Thu, 16 Aug 2018 15:12:12 +0000 (15:12 +0000)]
[cmake] Prevent LLVMgold.so from being unloaded on Linux

Extend the fix from D40459 to also apply to modules such as the LLVM
gold plugin. This is needed because current binutils master (and future
binutils 2.32) calls dlclose() on bfd plugins as part of a recent fix
for https://sourceware.org/bugzilla/show_bug.cgi?id=23460.

Patch by Evangelos Foutras!

Differential Revision: https://reviews.llvm.org/D50416

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339883 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] move vector compare before same-shuffled ops
Sanjay Patel [Thu, 16 Aug 2018 12:52:17 +0000 (12:52 +0000)]
[InstCombine] move vector compare before same-shuffled ops

This is a step towards fixing PR37463:
https://bugs.llvm.org/show_bug.cgi?id=37463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339875 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[yaml2obj] - Allow to use numeric sh_link (Link) value for sections.
George Rimar [Thu, 16 Aug 2018 12:44:17 +0000 (12:44 +0000)]
[yaml2obj] - Allow to use numeric sh_link (Link) value for sections.

That change allows using numeric values for Link field.
It is consistent with the code for another fields in this method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339873 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[yaml2elf] - Use check-next in test.
George Rimar [Thu, 16 Aug 2018 12:40:27 +0000 (12:40 +0000)]
[yaml2elf] - Use check-next in test.

Its a follow up for rL339870.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339872 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM] Ignore GEPs in ARMCodeGenPrepare
Sam Parker [Thu, 16 Aug 2018 12:24:40 +0000 (12:24 +0000)]
[ARM] Ignore GEPs in ARMCodeGenPrepare

While searching through the use-def tree, ignore GetElementPtrInst
instructions because they don't need promoting and neither do their
indices. Otherwise, the wide indices prevent the transformation from
happening.

Differential Revision: https://reviews.llvm.org/D50762

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339871 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[yaml2elf] - Simplify code, add a test. NFC.
George Rimar [Thu, 16 Aug 2018 12:23:22 +0000 (12:23 +0000)]
[yaml2elf] - Simplify code, add a test. NFC.

This simplifies the code allowing to set the sh_info
for relocations sections. And adds a missing test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339870 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM] Allow zext in ARMCodeGenPrepare
Sam Parker [Thu, 16 Aug 2018 11:54:09 +0000 (11:54 +0000)]
[ARM] Allow zext in ARMCodeGenPrepare

Treat zext instructions as roots, like we do for truncs.

Differential Revision: https://reviews.llvm.org/D50759

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339868 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is...
Alex Bradbury [Thu, 16 Aug 2018 11:26:37 +0000 (11:26 +0000)]
[RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true

When emitting the difference between two symbols, the standard behavior is
that the difference will be resolved to an absolute value if both of the
symbols are offsets from the same data fragment. This is undesirable on
architectures such as RISC-V where relaxation in the linker may cause the
computed difference to become invalid. This caused an issue when compiling to
object code, where the size of a function in the debug information was already
calculated even though it could change as a consequence of relaxation in the
subsequent linking stage.

This patch inhibits the resolution of symbol differences to absolute values
where the target's AsmBackend has declared that it does not want these to be
folded.

Differential Revision: https://reviews.llvm.org/D45773
Patch by Edward Jones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339864 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ADT] Replace APInt::WORD_MAX with APInt::WORDTYPE_MAX
Simon Pilgrim [Thu, 16 Aug 2018 11:08:23 +0000 (11:08 +0000)]
[ADT] Replace APInt::WORD_MAX with APInt::WORDTYPE_MAX

The windows SDK defines WORD_MAX, so any poor soul that wants to use LLVM in a project that depends on the windows SDK gets a build error.

Given that it actually describes the maximal value of WordType, it actually fits even better than WORD_MAX

Patch by: @miscco

Differential Revision: https://reviews.llvm.org/D50777

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339863 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM] Allow signed icmps in ARMCodeGenPrepare
Sam Parker [Thu, 16 Aug 2018 10:05:39 +0000 (10:05 +0000)]
[ARM] Allow signed icmps in ARMCodeGenPrepare

Originally committed in r339755 which was reverted in r339806 due to
an asan issue. The issue was caused by my assumption that operands to
a CallInst mapped to the FunctionType Params. CallInsts are now
handled by iterating over their ArgOperands instead of Operands.

Original Message:
  Treat signed icmps as 'sinks', allowing them to be in the use-def
  tree, enabling more promotions to be performed. As a sink, any
  promoted incoming values need to be truncated before being used by
  the signed icmp.

  Differential Revision: https://reviews.llvm.org/D50067

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339858 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[mips] Remove dead code from MipsPassConfig
Simon Atanasyan [Thu, 16 Aug 2018 08:43:17 +0000 (08:43 +0000)]
[mips] Remove dead code from MipsPassConfig

Found by GCC's -Wunused-function.

Patch by Kim Gräsman.

Differential revision: https://reviews.llvm.org/D50612

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339847 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC] Remove const modifier to allow further development in LICM
Max Kazantsev [Thu, 16 Aug 2018 08:30:15 +0000 (08:30 +0000)]
[NFC] Remove const modifier to allow further development in LICM

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339846 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC] Add missing const modifier
Max Kazantsev [Thu, 16 Aug 2018 06:28:04 +0000 (06:28 +0000)]
[NFC] Add missing const modifier

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339844 91177308-0d34-0410-b5e6-96231b3b80d8