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Jonas Devlieghere [Thu, 17 Aug 2017 17:06:48 +0000 (17:06 +0000)]
[Debug info] Transfer DI to fragment expressions for split integer values.
This patch teaches the SDag type legalizer how to split up debug info for
integer values that are split into a hi and lo part.
Differential Revision: https://reviews.llvm.org/D36805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311102
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Sanjay Patel [Thu, 17 Aug 2017 17:03:11 +0000 (17:03 +0000)]
[PowerPC] add tests for vector select-of-constants; NFC
We've discussed canonicalizing to this form in IR, so the backend
should be prepared to lower these in ways better than what we see
here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311099
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Adrian Prantl [Thu, 17 Aug 2017 16:57:13 +0000 (16:57 +0000)]
Improve line debug info when translating a CaseBlock to SDNodes.
The SelectionDAGBuilder translates various conditional branches into
CaseBlocks which are then translated into SDNodes. If a conditional
branch results in multiple CaseBlocks only the first CaseBlock is
translated into SDNodes immediately, the rest of the CaseBlocks are
put in a queue and processed when all LLVM IR instructions in the
basic block have been processed.
When a CaseBlock is transformed into SDNodes the SelectionDAGBuilder
is queried for the current LLVM IR instruction and the resulting
SDNodes are annotated with the debug info of the current
instruction (if it exists and has debug metadata).
When the deferred CaseBlocks are processed, the SelectionDAGBuilder
does not have a current LLVM IR instruction, and the resulting SDNodes
will not have any debuginfo. As DwarfDebug::beginInstruction() outputs
a .loc directive for the first instruction in a labeled
block (typically the case for something coming from a CaseBlock) this
tends to produce a line-0 directive.
This patch changes the handling of CaseBlocks to store the current
instruction's debug info into the CaseBlock when it is created (and the
SelectionDAGBuilder knows the current instruction) and to always use
the stored debug info when translating a CaseBlock to SDNodes.
Patch by Frej Drejhammar!
Differential Revision: https://reviews.llvm.org/D36671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311097
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Jakub Kuderski [Thu, 17 Aug 2017 16:45:35 +0000 (16:45 +0000)]
[Dominators] Teach LoopUnswitch to use the incremental API
Summary:
This patch makes LoopUnswitch use new incremental API for updating dominators.
It also updates SplitCriticalEdge, as it is called in LoopUnswitch.
There doesn't seem to be any noticeable performance difference when bootstrapping clang with this patch.
Reviewers: dberlin, davide, sanjoy, grosser, chandlerc
Reviewed By: davide, grosser
Subscribers: mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D35528
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311093
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Craig Topper [Thu, 17 Aug 2017 15:40:25 +0000 (15:40 +0000)]
[AVX512] Don't switch unmasked subvector insert/extract instructions when AVX512DQI is enabled.
There's no reason to switch instructions with and without DQI. It just creates extra isel patterns and test divergences.
There is however value in enabling the masked version of the instructions with DQI.
This required introducing some new multiclasses to enabling this splitting.
Differential Revision: https://reviews.llvm.org/D36661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311091
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Craig Topper [Thu, 17 Aug 2017 15:25:05 +0000 (15:25 +0000)]
[X86] Remove memopmmx pattern fragment
Summary: Just like the FIXME says, there is no alignment requirement for MMX.
Reviewers: RKSimon, zvi, igorb
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311090
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Victor Leschuk [Thu, 17 Aug 2017 15:07:03 +0000 (15:07 +0000)]
Mark Verifier/invalid-eh.ll as unsupported on windows
Mark this unsupported for now as it causes tests hangs on buildbot.
Will place it back when the problem is debugged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311089
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Simon Dardis [Thu, 17 Aug 2017 14:14:25 +0000 (14:14 +0000)]
[dfsan] Add explicit zero extensions for shadow parameters in function wrappers.
In the case where dfsan provides a custom wrapper for a function,
shadow parameters are added for each parameter of the function.
These parameters are i16s. For targets which do not consider this
a legal type, the lack of sign extension information would cause
LLVM to generate anyexts around their usage with phi variables
and calling convention logic.
Address this by introducing zero exts for each shadow parameter.
Reviewers: pcc, slthakur
Differential Revision: https://reviews.llvm.org/D33349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311087
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Daniel Sanders [Thu, 17 Aug 2017 13:18:35 +0000 (13:18 +0000)]
[globalisel][tablegen] Generate TypeObject table. NFC
Summary:
Generate the type table from the types used by a target rather than hard-coding
the union of types used by all targets.
Depends on D36084
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: rovka
Subscribers: kristof.beyls, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D36085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311084
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Simon Pilgrim [Thu, 17 Aug 2017 13:03:34 +0000 (13:03 +0000)]
[DAGCombiner] Add support for non-uniform constant vectors to (mul x, (1 << c)) -> x << c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311083
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Amjad Aboud [Thu, 17 Aug 2017 12:12:30 +0000 (12:12 +0000)]
[X86] Refactoring of X86TargetLowering::EmitLoweredSelect. NFC.
Authored by aivchenk
Differential Revision: https://reviews.llvm.org/D35685
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311082
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Davide Italiano [Thu, 17 Aug 2017 11:32:21 +0000 (11:32 +0000)]
[Verifier] Avoid visiting DIGlobalVariables twice.
We currently visit them twice.
Once, through `visitMDNode()` -> (the code generated by)
`../include/llvm/IR/Metadata.def:109` -> `visitDIGlobalVariable()`
Then, through `visitMDNode()` -> `visitDIGlobalVariableExpression()`
-> `visitDIGlobalVariable()`
This results in verification failures printed twice, e.g.:
$ ./opt -verify ../../test/DebugInfo/pr34186.ll
missing global variable type
!4 = distinct !DIGlobalVariable(name: "pat", scope: !0,
file: !1, line: 27, isLocal: true, isDefinition: true)
missing global variable type
!4 = distinct !DIGlobalVariable(name: "pat", scope: !0,
file: !1, line: 27, isLocal: true, isDefinition: true)
./opt: ../../test/DebugInfo/pr34186.ll: error: input module is broken!
The patch removes one call so we ensure each GV is visited exactly once.
Differential Revision: https://reviews.llvm.org/D36797
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311081
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Ayal Zaks [Thu, 17 Aug 2017 09:29:59 +0000 (09:29 +0000)]
[LV] Using VPlan to model the vectorized code and drive its transformation
VPlan is an ongoing effort to refactor and extend the Loop Vectorizer. This
patch introduces the VPlan model into LV and uses it to represent the vectorized
code and drive the generation of vectorized IR.
In this patch VPlan models the vectorized loop body: the vectorized control-flow
is represented using VPlan's Hierarchical CFG, with predication refactored from
being a post-vectorization-step into a vectorization planning step modeling
if-then VPRegionBlocks, and generating code inline with non-predicated code. The
vectorized code within each VPBasicBlock is represented as a sequence of
Recipes, each responsible for modelling and generating a sequence of IR
instructions. To keep the size of this commit manageable the Recipes in this
patch are coarse-grained and capture large chunks of LV's code-generation logic.
The constructed VPlans are dumped in dot format under -debug.
This commit retains current vectorizer output, except for minor instruction
reorderings; see associated modifications to lit tests.
For further details on the VPlan model see docs/Proposals/VectorizationPlan.rst
and its references.
Authors: Gil Rapaport and Ayal Zaks
Differential Revision: https://reviews.llvm.org/D32871
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311077
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Daniel Sanders [Thu, 17 Aug 2017 09:26:14 +0000 (09:26 +0000)]
Re-commit: [globalisel][tablegen] Support zero-instruction emission.
Summary:
Support the case where an operand of a pattern is also the whole of the
result pattern. In this case the original result and all its uses must be
replaced by the operand. However, register class restrictions can require
a COPY. This patch handles both cases by always emitting the copy and
leaving it for the register allocator to optimize.
The previous commit failed on Windows machines due to a flaw in the sort
predicate which allowed both A < B < C and B == C to be satisfied
simultaneously. The cause of this was some sloppiness in the priority order of
G_CONSTANT instructions compared to other instructions. These had equal priority
because it makes no difference, however there were operands had higher priority
than G_CONSTANT but lower priority than any other instruction. As a result, a
priority order between G_CONSTANT and other instructions must be enforced to
ensure the predicate defines a strict weak order.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D36084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311076
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Jonas Paulsson [Thu, 17 Aug 2017 09:18:02 +0000 (09:18 +0000)]
[SystemZ] Also wrap TII with #ifndef NDEBUG in constructor initilizer list.
TII needs to be wrapped with #ifndef NDEBUG to silece compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311075
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Jonas Paulsson [Thu, 17 Aug 2017 08:56:09 +0000 (08:56 +0000)]
[SystemZ] Add a wrapping with #ifndef NDEBUG to silence warning.
SystemZHazardRecognizer::TII is only used for debug output, so it needs
also to be wrapped with #ifndef NDEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311074
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Jonas Paulsson [Thu, 17 Aug 2017 08:33:44 +0000 (08:33 +0000)]
[SystemZ, MachineScheduler] Improve post-RA scheduling.
The idea of this patch is to continue the scheduler state over an MBB boundary
in the case where the successor block has only one predecessor. This means
that the scheduler will continue in the successor block (after emitting any
branch instructions) with e.g. maintained processor resource counters.
Benchmarks have been confirmed to benefit from this.
The algorithm in MachineScheduler.cpp that extracts scheduling regions of an
MBB has been extended so that the strategy may optionally reverse the order
of processing the regions themselves. This is controlled by a new method
doMBBSchedRegionsTopDown(), which defaults to false.
Handling the top-most region of an MBB first also means that a top-down
scheduler can continue the scheduler state across any scheduling boundary
between to regions inside MBB.
Review: Ulrich Weigand, Matthias Braun, Andy Trick.
https://reviews.llvm.org/D35053
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311072
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Elad Cohen [Thu, 17 Aug 2017 08:06:36 +0000 (08:06 +0000)]
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC
When v1i1 is legal (e.g. AVX512) the legalizer can reach
a case where a v1i1 SETCC with an illgeal vector type operand
wasn't scalarized (since v1i1 is legal) but its operands does
have to be scalarized. This used to assert because SETCC was
missing from the vector operand scalarizer.
This patch attemps to teach the legalizer to handle these cases
by scalazring the operands, converting the node into a scalar
SETCC node.
Differential revision: https://reviews.llvm.org/D36651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311071
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Martin Storsjo [Thu, 17 Aug 2017 06:26:42 +0000 (06:26 +0000)]
[llvm-dlltool] Improve an error message when unable to open files. NFC.
Differential Revision: https://reviews.llvm.org/D36818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311069
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Martin Storsjo [Thu, 17 Aug 2017 05:58:27 +0000 (05:58 +0000)]
[llvm-dlltool] Don't crash if no def file is provided or it can't be opened
Differential Revision: https://reviews.llvm.org/D36780
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311068
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Serguei Katkov [Thu, 17 Aug 2017 05:48:30 +0000 (05:48 +0000)]
[CGP] Fix the rematerialization of gc.relocates
If we want to substitute the relocation of derived pointer with gep of base then
we must ensure that relocation of base dominates the relocation of derived pointer.
Currently only check for basic block is present. However it is possible that both
relocation are in the same basic block but relocation of derived pointer is defined
earlier.
The patch moves the relocation of base pointer right before relocation of derived
pointer in this case.
Reviewers: sanjoy,artagnon,igor-laevsky,reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311067
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Geoff Berry [Thu, 17 Aug 2017 04:04:11 +0000 (04:04 +0000)]
Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
This reverts commit r311038.
Several buildbots are breaking, and at least one appears to be due to
the forwarding of physical regs enabled by this change. Reverting while
I investigate further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311062
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Saleem Abdulrasool [Thu, 17 Aug 2017 02:42:24 +0000 (02:42 +0000)]
ARM: mark CPSR as clobbered for Windows VLAs
When lowering a VLA, we emit a __chstk call. However, this call can
internally clobber CPSR. We did not mark this register as an ImpDef,
which could potentially allow a comparison to be hoisted above the call
to `__chkstk`. In such a case, the CPSR could be clobbered, and the
check invalidated. When the support was initially added, it seemed that
the call would take care of preventing CPSR from being clobbered, but
this is not the case. Mark the register as clobbered to fix a possible
state corruption.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311061
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Craig Topper [Thu, 17 Aug 2017 02:34:35 +0000 (02:34 +0000)]
[X86] Exchange the memory op predicate for PALIGNR/VPALIGNR. I accidentally swapped them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311060
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Craig Topper [Thu, 17 Aug 2017 01:48:03 +0000 (01:48 +0000)]
[X86] Cleanup multiclasses for SSE/AVX2 PALIGNR. Add missing load patterns.
We used to have a separate multiclass for AVX2 and SSE/AVX. Now we have one multiclass and pass the relevant differences.
We were also missing load patterns, though we had them for the AVX-512 version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311059
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Craig Topper [Thu, 17 Aug 2017 01:48:00 +0000 (01:48 +0000)]
[X86] Remove patterns for PALIGNR with non-vXi8 types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311058
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Jakub Kuderski [Thu, 17 Aug 2017 01:41:49 +0000 (01:41 +0000)]
Reapply: [ADCE][Dominators] Teach ADCE to preserve dominators
Summary:
This patch teaches ADCE to preserve both DominatorTrees and PostDominatorTrees.
I didn't notice any performance impact when bootstrapping clang with this patch.
The patch was originally committed in r311039 and reverted in r311049.
This revision fixes the problem with not adding a dependency on the
DominatorTreeWrapperPass for the LegacyPassManager.
Reviewers: dberlin, chandlerc, sanjoy, davide, grosser, brzycki
Reviewed By: davide
Subscribers: grandinj, zhendongsu, llvm-commits, david2050
Differential Revision: https://reviews.llvm.org/D35869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311057
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Craig Topper [Wed, 16 Aug 2017 23:38:25 +0000 (23:38 +0000)]
[X86] Put multiclass closer to its use and simplify slightly. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311055
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Craig Topper [Wed, 16 Aug 2017 23:16:43 +0000 (23:16 +0000)]
[X86] Use a static array instead of a SmallVector for a small fixed size array. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311054
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Sanjay Patel [Wed, 16 Aug 2017 22:50:11 +0000 (22:50 +0000)]
[x86] add cmov promotion tests for D36711; NFC
This way we can see what the current codegen looks like.
I've also explicitly added/removed the cmov attribute from the RUN lines,
so we know exactly what we're checking in the runs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311052
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Amjad Aboud [Wed, 16 Aug 2017 22:42:38 +0000 (22:42 +0000)]
[InstCombine] Teach canEvaluateTruncated to handle arithmetic shift (including those with vector splat shift amount)
Differential Revision: https://reviews.llvm.org/D36784
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311050
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Jakub Kuderski [Wed, 16 Aug 2017 22:10:53 +0000 (22:10 +0000)]
Revert "[ADCE][Dominators] Teach ADCE to preserve dominators"
This reverts commit r311039. The patch caused the
`test/Bindings/OCaml/Output/scalar_opts.ml` to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311049
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Eugene Zelenko [Wed, 16 Aug 2017 22:07:40 +0000 (22:07 +0000)]
[Analysis] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311048
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Craig Topper [Wed, 16 Aug 2017 21:52:07 +0000 (21:52 +0000)]
[InstCombine] Make folding (X >s -1) ? C1 : C2 --> ((X >>s 31) & (C2 - C1)) + C1 support splat vectors
This also uses decomposeBitTestICmp to decode the compare.
Differential Revision: https://reviews.llvm.org/D36781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311044
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Jakub Kuderski [Wed, 16 Aug 2017 20:50:23 +0000 (20:50 +0000)]
[ADCE][Dominators] Teach ADCE to preserve dominators
Summary:
This patch teaches ADCE to preserve both DominatorTrees and PostDominatorTrees.
I didn't notice any performance impact when bootstrapping clang with this patch.
Reviewers: dberlin, chandlerc, sanjoy, davide, grosser, brzycki
Reviewed By: davide
Subscribers: grandinj, zhendongsu, llvm-commits, david2050
Differential Revision: https://reviews.llvm.org/D35869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311039
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Geoff Berry [Wed, 16 Aug 2017 20:50:01 +0000 (20:50 +0000)]
[MachineCopyPropagation] Extend pass to do COPY source forwarding
This change extends MachineCopyPropagation to do COPY source forwarding.
This change also extends the MachineCopyPropagation pass to be able to
be run during register allocation, after physical registers have been
assigned, but before the virtual registers have been re-written, which
allows it to remove virtual register COPY LiveIntervals that become dead
through the forwarding of all of their uses.
Reviewers: qcolombet, javed.absar, MatzeB, jonpa
Subscribers: jyknight, nemanjai, llvm-commits, nhaehnle, mcrosier, mgorny
Differential Revision: https://reviews.llvm.org/D30751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311038
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Petr Hosek [Wed, 16 Aug 2017 19:13:45 +0000 (19:13 +0000)]
[CMake][runtimes] Support for building target variants
This can be used to build non-sanitized and sanitized versions of
runtimes, where sanitized versions use the just built sanitizer
which in turn may use the non-sanitized version.
Differential Revision: https://reviews.llvm.org/D36348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311036
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Geoff Berry [Wed, 16 Aug 2017 19:03:16 +0000 (19:03 +0000)]
[LoopDataPrefetch][AArch64FalkorHWPFFix] Preserve ScalarEvolution
Summary:
Mark LoopDataPrefetch and AArch64FalkorHWPFFix passes as preserving
ScalarEvolution since they do not alter loop structure and should not
alter any SCEV values (though LoopDataPrefetch may introduce new
instructions that won't have cached SCEV values yet).
This can result in slight code differences, mainly w.r.t. nsw/nuw flags
on SCEVs, since these are computed somewhat lazily when a zext/sext
instruction is encountered. As a result, passes after the modified
passes may see SCEVs with more nsw/nuw flags present.
Reviewers: sanjoy, anemet
Subscribers: aemerson, rengolin, mzolotukhin, javed.absar, kristof.beyls, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D36716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311032
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Simon Atanasyan [Wed, 16 Aug 2017 19:01:22 +0000 (19:01 +0000)]
[mips] Handle R_MIPS_TLS_DTPREL32/64 relocations in the RelocVisitor
Debug information for TLS variables on MIPS might have R_MIPS_TLS_DTPREL32
or R_MIPS_TLS_DTPREL64 relocations. This patch adds a support for such
relocations in the `RelocVisitor`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311031
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Adrian Prantl [Wed, 16 Aug 2017 17:43:01 +0000 (17:43 +0000)]
Add a convenience overload of DWARFDie::dump() for debugging purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311026
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Xinliang David Li [Wed, 16 Aug 2017 17:33:43 +0000 (17:33 +0000)]
Add more comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311025
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Xinliang David Li [Wed, 16 Aug 2017 17:18:01 +0000 (17:18 +0000)]
[PGO] Fix ThinLTO crash
Differential Revsion: http://reviews.llvm.org/D36640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311023
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Evgeny Mankov [Wed, 16 Aug 2017 16:47:29 +0000 (16:47 +0000)]
[AMDGPU] NFC: test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311019
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Konstantin Zhuravlyov [Wed, 16 Aug 2017 16:23:32 +0000 (16:23 +0000)]
AMDGPU/NFC: Sort files in CMakeLists.txt alphabetically
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311017
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Simon Pilgrim [Wed, 16 Aug 2017 16:22:19 +0000 (16:22 +0000)]
[X86] Regenerate immediate store merging tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311016
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Jakub Kuderski [Wed, 16 Aug 2017 16:12:52 +0000 (16:12 +0000)]
[Dominators] Introduce batch updates
Summary:
This patch introduces a way of informing the (Post)DominatorTree about multiple CFG updates that happened since the last tree update. This makes performing tree updates much easier, as it internally takes care of applying the updates in lockstep with the (virtual) updates to the CFG, which is done by reverse-applying future CFG updates.
The batch updater is able to remove redundant updates that cancel each other out. In the future, it should be also possible to reorder updates to reduce the amount of work needed to perform the updates.
Reviewers: dberlin, sanjoy, grosser, davide, brzycki
Reviewed By: brzycki
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D36167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311015
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Hal Finkel [Wed, 16 Aug 2017 16:09:22 +0000 (16:09 +0000)]
[BDCE] Don't check demanded bits on unsized types
To clear assumptions that are potentially invalid after trivialization, we need
to walk the use/def chain. Normally, the only way to reach an instruction with
an unsized type is via an instruction that has side effects (or otherwise will
demand its input bits). That would stop the walk. However, if we have a
readnone function that returns an unsized type (e.g., void), we must avoid
asking for the demanded bits of the function call's return value. A
void-returning readnone function is always dead (and so we can stop walking the
use/def chain here), but the check is necessary to avoid asserting.
Fixes PR34211.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311014
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Davide Italiano [Wed, 16 Aug 2017 15:16:33 +0000 (15:16 +0000)]
[Verifier] Reject globals without a type associated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311012
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Dmitry Preobrazhensky [Wed, 16 Aug 2017 15:16:32 +0000 (15:16 +0000)]
[AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16
This change implements features postponed in https://reviews.llvm.org/D35424 because of a dependency on https://reviews.llvm.org/D36322
Reviewers: SamWot, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D36694
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311011
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Sanjay Patel [Wed, 16 Aug 2017 14:28:23 +0000 (14:28 +0000)]
[DemandedBits] simplify call; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311009
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Balaram Makam [Wed, 16 Aug 2017 14:17:43 +0000 (14:17 +0000)]
Revert "MachineInstr: Reason locally about some memory objects before going to AA."
r310825 caused the clang-ppc64le-linux-lnt bot to go red
(http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/5712)
because of a test-suite failure of
SingleSource/UnitTests/2003-07-09-SignedArgs
This reverts commit
0028f6a87224fb595a1c19c544cde9b003035996.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311008
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Dmitry Preobrazhensky [Wed, 16 Aug 2017 13:51:56 +0000 (13:51 +0000)]
[AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes
See Bug 34152: https://bugs.llvm.org//show_bug.cgi?id=34152
Reviewers: SamWot, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D36674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311006
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Simon Pilgrim [Wed, 16 Aug 2017 13:50:20 +0000 (13:50 +0000)]
[CostModel][X86][XOP] Improve costs for XOP shuffles
VPPERM/VPERMIL2PD/VPERMIL2PS all provide more effective 2-input shuffles than regular AVX instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311005
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Davide Italiano [Wed, 16 Aug 2017 13:39:07 +0000 (13:39 +0000)]
[DI] Every DIGlobalVariable should have a type.
I'll make this a verifier check to catch other violations. This
commit fixes the tests already in tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311004
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Simon Dardis [Wed, 16 Aug 2017 12:18:04 +0000 (12:18 +0000)]
[mips] Handle variables with an explicit section and interactions with .sdata, .sbss
If a variable has an explicit section such as .sdata or .sbss, it is placed
in that section and accessed in a gp relative manner. This overrides the global
-G setting.
Otherwise if a variable has a explicit section attached to it, such as '.rodata'
or '.mysection', it is not placed in the small data section. This also overrides
the global -G setting.
Reviewers: atanasyan, nitesh.jain
Differential Revision: https://reviews.llvm.org/D36616
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311001
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Sam Parker [Wed, 16 Aug 2017 07:42:44 +0000 (07:42 +0000)]
[ARM] Improve loop unrolling for Cortex-M
- Set the default runtime unroll count to 4 and use the newly added
UnrollRemainder option.
- Create loop cost and force unroll for a cost less than 12.
- Disable unrolling on Thumb1 only targets.
Differential Revision: https://reviews.llvm.org/D36134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310997
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Igor Breger [Wed, 16 Aug 2017 07:25:51 +0000 (07:25 +0000)]
[GlobalISel][X86] Fix mir tests, use correct physical register.NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310996
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Martin Storsjo [Wed, 16 Aug 2017 05:22:49 +0000 (05:22 +0000)]
[COFF] Make the weak aliases optional
When creating an import library from lld, the cases with
Name != ExtName shouldn't end up as a weak alias, but as a real
export of the new name, which is what actually is exported from
the DLL.
This restores the behaviour of renamed exports to what it was in
4.0.
The other half of this commit, including test, goes into lld.
Differential Revision: https://reviews.llvm.org/D36633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310991
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Martin Storsjo [Wed, 16 Aug 2017 05:18:36 +0000 (05:18 +0000)]
[llvm-dlltool] Fix creating stdcall/fastcall import libraries for i386
Hook up the -k option (that in the original GNU dlltool removes the
@n suffix from the symbol that the final executable ends up linked to).
In llvm-dlltool, make sure that functions end up with the undecorate
name type if this option is set and they are decorated. In mingw, when
creating import libraries from def files instead of creating an import
library as a side effect of linking a DLL, the symbol names in the def
contain the stdcall/fastcall decoration (but no leading underscore).
By setting the undecorate name type, a linker linking to the import
library will omit the decoration from the DLL import entry.
With this in place, mingw-w64 for i386 built with llvm-dlltool/clang
produces import libraries that actually work.
Differential Revision: https://reviews.llvm.org/D36548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310990
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Martin Storsjo [Wed, 16 Aug 2017 05:13:16 +0000 (05:13 +0000)]
[COFF] Add SymbolName as a distinct field in COFFImportFile
The previous Name and ExtName aren't enough to convey all the nuances
between weak aliases and stdcall decorated function names.
A test for this will be added in LLD.
Differential Revision: https://reviews.llvm.org/D36544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310988
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Stanislav Mekhanoshin [Wed, 16 Aug 2017 04:43:49 +0000 (04:43 +0000)]
[AMDGPU] Eliminate no effect instructions before s_endpgm
Differential Revision: https://reviews.llvm.org/D36585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310987
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Dehao Chen [Wed, 16 Aug 2017 01:55:26 +0000 (01:55 +0000)]
Merge debug info when hoist then-else code to if.
Summary: When we move then-else code to if, we need to merge its debug info, otherwise the hoisted instruction may have inaccurate debug info attached.
Reviewers: aprantl, probinson, dblaikie, echristo, loladiro
Reviewed By: aprantl
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D36778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310985
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Derek Schuff [Wed, 16 Aug 2017 00:49:44 +0000 (00:49 +0000)]
[WebAssembly] Remove infinite loop from reg-stackify test
r310940 exposed reverse-unreachable code to some optimizers,
which caused some of the code in this test to be sunk, changing
the input to the pass and breaking the exptectations.
Since that change is irrelevant to this particular test, this change
just adds an exit node to work around the problem; the
test should really be more robust (or be an MIR test?) but this preserves
the existing test intent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310981
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Quentin Colombet [Wed, 16 Aug 2017 00:17:05 +0000 (00:17 +0000)]
[VirtRegRewriter] Properly model the register liveness on undef subreg definition
Undef subreg definition means that the content of the super register
doesn't matter at this point. While that's true for virtual registers,
this may not hold when replacing them with actual physical registers.
Indeed, some part of the physical register may be coalesced with the
related virtual register and thus, the values for those parts matter and
must be live.
The fix consists in checking whether or not subregs of the physical register
being assigned to an undef subreg definition are live through that def and
insert an implicit use if they are. Doing so, will keep them alive until
that point like they should be.
E.g., let vreg14 being assigned to R0_R1 then
%vreg14:gsub_0<def,read-undef> = COPY %R0 ; <-- R1 is still live here
%vreg14:gsub_1<def> = COPY %R1
Before this changes, the rewriter would change the code into:
%R0<def> = KILL %R0, %R0_R1<imp-def> ; <-- this tells R1 is redefined
%R1<def> = KILL %R1, %R0_R1<imp-def>, %R0_R1<imp-use> ; this value of this R1
; is believed to come
; from the previous
; instruction
Because of this invalid liveness, later pass could make wrong choices and in
particular clobber live register as it happened with the register scavenger in
llvm.org/PR34107
Now we would generate:
%R0<def> = KILL %R0, %R0_R1<imp-def>, %R0_R1<imp-use> ; This tells R1 needs to
; reach this point
%R1<def> = KILL %R1, %R0_R1<imp-def>, %R0_R1<imp-use>
The bug has been here forever, it got exposed recently because the register
scavenger got smarter.
Fixes llvm.org/PR34107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310979
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Kuba Mracek [Tue, 15 Aug 2017 23:41:34 +0000 (23:41 +0000)]
Revert archive-* tests from r310953, there were test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310974
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Craig Topper [Tue, 15 Aug 2017 22:48:41 +0000 (22:48 +0000)]
[InstCombine] Teach canEvaluateZExtd and canEvaluateTruncated to handle vector shifts with splat shift amount
We were only allowing ConstantInt before. This patch allows splat of ConstantInt too.
Differential Revision: https://reviews.llvm.org/D36763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310970
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Quentin Colombet [Tue, 15 Aug 2017 22:31:51 +0000 (22:31 +0000)]
Reapply "[GlobalISel] Remove the GISelAccessor API."
This reverts commit r310425, thus reapplying r310335 with a fix for link
issue of the AArch64 unittests on Linux bots when BUILD_SHARED_LIBS is ON.
Original commit message:
[GlobalISel] Remove the GISelAccessor API.
Its sole purpose was to avoid spreading around ifdefs related to
building global-isel. Since r309990, GlobalISel is not optional anymore,
thus, we can get rid of this mechanism all together.
NFC.
----
The fix for the link issue consists in adding the GlobalISel library in
the list of dependencies for the AArch64 unittests. This dependency
comes from the use of AArch64Subtarget that needs to know how
to destruct the GISel related APIs when being detroyed.
Thanks to Bill Seurer and Ahmed Bougacha for helping me reproducing and
understand the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310969
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Charles Saternos [Tue, 15 Aug 2017 22:23:44 +0000 (22:23 +0000)]
[ThinLTO] Fix ThinLTO crash while destroying context
Fix for PR32763
An assert that checks if a Ref was untracked fails during ThinLTO context cleanup. The issue is because lazy loading temporary nodes didn't properly track ValueAsMetadata nodes. This patch ensures that the temporary nodes are properly tracked when they're replaced with the value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310967
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Kuba Mracek [Tue, 15 Aug 2017 21:02:17 +0000 (21:02 +0000)]
Revert changes in r310953 for llvm-symbolizer.test. The change causes a test failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310956
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Tony Tye [Tue, 15 Aug 2017 20:47:41 +0000 (20:47 +0000)]
Update AMDGPUUsage.rst documentation:
1. Correct description of the kernel initial state for FLAT_SCRATCH_INIT.
2. Add link to GFX9 architecture documentation.
3. Update product names.
4. Rename note record from NT_AMD_AMDGPU_METADATA to NT_AMD_AMDGPU_HSA_METADATA and move description to the AMDHSA coding convention section.
5. Minor typo corrections.
Differential Revision: https://reviews.llvm.org/D36549
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310954
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Kuba Mracek [Tue, 15 Aug 2017 20:29:24 +0000 (20:29 +0000)]
[llvm] Get rid of "%T" expansions
The %T lit expansion expands to a common directory shared between all the tests in the same directory, which is unexpected and unintuitive, and more importantly, it's been a source of subtle race conditions and flaky tests. In https://reviews.llvm.org/D35396, it was agreed that it would be best to simply ban %T and only keep %t, which is unique to each test. When a test needs a temporary directory, it can just create one using mkdir %t.
This patch removes %T in llvm.
Differential Revision: https://reviews.llvm.org/D36495
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310953
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Amjad Aboud [Tue, 15 Aug 2017 19:33:14 +0000 (19:33 +0000)]
[InstCombine] Added support for (X >>s C) << C --> X & (-1 << C)
Differential Revision: https://reviews.llvm.org/D36743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310949
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Lang Hames [Tue, 15 Aug 2017 19:20:10 +0000 (19:20 +0000)]
[ORC][Kaleidoscope] Update Chapter 1 of BuildingAJIT to incorporate recent ORC
API changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310947
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Sanjay Patel [Tue, 15 Aug 2017 18:25:52 +0000 (18:25 +0000)]
[InstCombine] sink sext after ashr
Narrow ops are better for bit-tracking, and in the case of vectors,
may enable better codegen.
As the trunc test shows, this can allow follow-on simplifications.
There's a block of code in visitTrunc that deals with shifted ops
with FIXME comments. It may be possible to remove some of that now,
but I want to make sure there are no problems with this step first.
http://rise4fun.com/Alive/Y3a
Name: hoist_ashr_ahead_of_sext_1
%s = sext i8 %x to i32
%r = ashr i32 %s, 3 ; shift value is < than source bit width
=>
%a = ashr i8 %x, 3
%r = sext i8 %a to i32
Name: hoist_ashr_ahead_of_sext_2
%s = sext i8 %x to i32
%r = ashr i32 %s, 8 ; shift value is >= than source bit width
=>
%a = ashr i8 %x, 7 ; so clamp this shift value
%r = sext i8 %a to i32
Name: junc_the_trunc
%a = sext i16 %v to i32
%s = ashr i32 %a, 18
%t = trunc i32 %s to i16
=>
%t = ashr i16 %v, 15
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310942
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Jakub Kuderski [Tue, 15 Aug 2017 18:14:57 +0000 (18:14 +0000)]
[Dominators] Include infinite loops in PostDominatorTree
Summary:
This patch teaches PostDominatorTree about infinite loops. It is built on top of D29705 by @dberlin which includes a very detailed motivation for this change.
What's new is that the patch also teaches the incremental updater how to deal with reverse-unreachable regions and how to properly maintain and verify tree roots. Before that, the incremental algorithm sometimes ended up preserving reverse-unreachable regions after updates that wouldn't appear in the tree if it was constructed from scratch on the same CFG.
This patch makes the following assumptions:
- A sequence of updates should produce the same tree as a recalculating it.
- Any sequence of the same updates should lead to the same tree.
- Siblings and roots are unordered.
The last two properties are essential to efficiently perform batch updates in the future.
When it comes to the first one, we can decide later that the consistency between freshly built tree and an updated one doesn't matter match, as there are many correct ways to pick roots in infinite loops, and to relax this assumption. That should enable us to recalculate postdominators less frequently.
This patch is pretty conservative when it comes to incremental updates on reverse-unreachable regions and ends up recalculating the whole tree in many cases. It should be possible to improve the performance in many cases, if we decide that it's important enough.
That being said, my experiments showed that reverse-unreachable are very rare in the IR emitted by clang when bootstrapping clang. Here are the statistics I collected by analyzing IR between passes and after each removePredecessor call:
```
# functions: 52283
# samples: 337609
# reverse unreachable BBs: 216022
# BBs:
247840796
Percent reverse-unreachable: 0.
08716159869015269 %
Max(PercRevUnreachable) in a function: 87.
58620689655172 %
# > 25 % samples: 471 ( 0.
1395104988314885 % samples )
... in 145 ( 0.
27733680163724345 % functions )
```
Most of the reverse-unreachable regions come from invalid IR where it wouldn't be possible to construct a PostDomTree anyway.
I would like to commit this patch in the next week in order to be able to complete the work that depends on it before the end of my internship, so please don't wait long to voice your concerns :).
Reviewers: dberlin, sanjoy, grosser, brzycki, davide, chandlerc, hfinkel
Reviewed By: dberlin
Subscribers: nhaehnle, javed.absar, kparzysz, uabelho, jlebar, hiraditya, llvm-commits, dberlin, david2050
Differential Revision: https://reviews.llvm.org/D35851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310940
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Tom Stellard [Tue, 15 Aug 2017 18:11:56 +0000 (18:11 +0000)]
test-release.sh: Move test-suite setup to beginning of the script
Summary:
We want to catch failures early before do the full 3 stage build.
The goal here is to avoid running through the whole build process and have
it fail at the end (and not create the binary packages), just because
some prerequisites failed to install.
Reviewers: rovka, hans
Reviewed By: hans
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310939
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Lang Hames [Tue, 15 Aug 2017 18:10:19 +0000 (18:10 +0000)]
[ORC] Add case statements for AArch64 to the local stub and callback manager
creation functions.
This should allow lli to lazily execute code using OrcLazyJIT on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310938
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Sanjay Patel [Tue, 15 Aug 2017 17:41:31 +0000 (17:41 +0000)]
[InstCombine] add tests for sext+ashr; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310935
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Rui Ueyama [Tue, 15 Aug 2017 17:39:35 +0000 (17:39 +0000)]
Fix -Wunused-lambda-capture for Release build.
`I` and `this` are used only in assert or DEBUG, so they are unused
in Release build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310934
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George Rimar [Tue, 15 Aug 2017 16:42:21 +0000 (16:42 +0000)]
[llvm-dwarfdump] - Attemp to fix BB after r310915.
Now MIPS one is unhappy:
http://lab.llvm.org:8011/builders/llvm-mips-linux/builds/2221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310928
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Steven Wu [Tue, 15 Aug 2017 16:16:33 +0000 (16:16 +0000)]
[Doc] Update LangRef for new Module Flag Behavior
Summary:
Add the documentation for the new module flag behavior. The new
ModFlagBehavior is added in r303590.
Reviewers: tejohnson
Reviewed By: tejohnson
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310926
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George Rimar [Tue, 15 Aug 2017 15:54:43 +0000 (15:54 +0000)]
[llvm-dwarfdump] - Refactor section name/uniqueness gathering.
As was requested in D36313 thread,
with this patch section names and uniqueness calculated once,
and not every time when a range is dumped.
Differential revision: https://reviews.llvm.org/D36740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310923
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Daniel Sanders [Tue, 15 Aug 2017 15:10:31 +0000 (15:10 +0000)]
Revert r310919 - [globalisel][tablegen] Support zero-instruction emission.
As expected, this failed on the windows bots but the instrumentation showed
something interesting. The ADD8ri and INC8r rules are never directly compared
on the windows machines. That implies that the issue lies in transitivity of
the Compare predicate. I believe I've already verified that but maybe I missed
something.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310922
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Daniel Sanders [Tue, 15 Aug 2017 13:50:09 +0000 (13:50 +0000)]
Re-commit with some instrumentation: [globalisel][tablegen] Support zero-instruction emission.
Summary:
Support the case where an operand of a pattern is also the whole of the
result pattern. In this case the original result and all its uses must be
replaced by the operand. However, register class restrictions can require
a COPY. This patch handles both cases by always emitting the copy and
leaving it for the register allocator to optimize.
The previous commit failed on the windows bots and this one is likely to fail
on those same bots. However, the added instrumentation should reveal a particular
isHigherPriorityThan() evaluation which I'm expecting to expose that
these machines are weighing priority of two rules differently from the
non-windows machines.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D36084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310919
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George Rimar [Tue, 15 Aug 2017 13:26:12 +0000 (13:26 +0000)]
[DebugInfo] - Attemp to fix BB after r310915.
Not sure what BB does not like.
While building module 'LLVM_DebugInfo_DWARF' imported from /home/buildbot/modules-slave-2/clang-x86_64-linux-selfhost-modules-2/llvm.src/lib/DebugInfo/DWARF/DWARFAbbreviationDeclaration.cpp:10:
In file included from <module-includes>:7:
In file included from /home/buildbot/modules-slave-2/clang-x86_64-linux-selfhost-modules-2/llvm.src/include/llvm/DebugInfo/DWARF/DWARFContext.h:29:
/home/buildbot/modules-slave-2/clang-x86_64-linux-selfhost-modules-2/llvm.src/include/llvm/DebugInfo/DWARF/DWARFObject.h:30:17: error: declaration of 'object' must be imported from module 'LLVM_Object.Decompressor' before it is required
virtual const object::ObjectFile *getFile() const { return nullptr; }
^
/home/buildbot/modules-slave-2/clang-x86_64-linux-selfhost-modules-2/llvm.src/include/llvm/Object/Decompressor.h:18:11: note: previous declaration is here
namespace object {
http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/10766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310918
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Alex Bradbury [Tue, 15 Aug 2017 13:08:29 +0000 (13:08 +0000)]
[RISCV] Add RISCVInstPrinter and basic MC assembler tests
With the addition of RISCVInstPrinter, it is now possible to test the basic
operation of the RISCV MC layer.
Differential Revision: https://reviews.llvm.org/D23564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310917
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George Rimar [Tue, 15 Aug 2017 12:32:54 +0000 (12:32 +0000)]
[llvm-dwarfdump] - Print section name and index when dumping .debug_info ranges
Teaches llvm-dwarfdump to print section index and name of range
when it dumps .debug_info.
Differential revision: https://reviews.llvm.org/D36313
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310915
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Alex Bradbury [Tue, 15 Aug 2017 12:11:10 +0000 (12:11 +0000)]
[RISCV] Recognize new relocation types
This patch adds all RISC-V relocation types, as of binutils 2.29. Note that
R_RISCV32_PCREL is not currently documented in the RISC-V ELF PSABI.
Differential Revision: https://reviews.llvm.org/D36455
Patch by Chih-Mao Chen (@PkmX)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310914
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Ayal Zaks [Tue, 15 Aug 2017 08:32:59 +0000 (08:32 +0000)]
[LV] Minor savings to Sink casts to unravel first order recurrence
Two minor savings: avoid copying the SinkAfter map and avoid moving a cast if it
is not needed.
Differential Revision: https://reviews.llvm.org/D36408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310910
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Frederich Munch [Tue, 15 Aug 2017 02:25:36 +0000 (02:25 +0000)]
Propagate error in LazyEmittingLayer::removeModule.
Summary:
Besides being the better thing to do, not doing so will triggers an assert with LLVM_ENABLE_ABI_BREAKING_CHECKS.
Reviewers: lhames
Reviewed By: lhames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310906
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Dinar Temirbulatov [Tue, 15 Aug 2017 00:31:49 +0000 (00:31 +0000)]
[SLPVectorizer] Replace VL[0] to VL0 with assert, add propagateIRFlags extra parameter VL0,
replace E->Scalars[0] to VL0, NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310904
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Petr Hosek [Mon, 14 Aug 2017 23:37:31 +0000 (23:37 +0000)]
[CMake] Add install target for LLVMFuzzer
This allows including LLVMFuzzer as distribution component.
Differential Revision: https://reviews.llvm.org/D36540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310897
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Dehao Chen [Mon, 14 Aug 2017 23:25:21 +0000 (23:25 +0000)]
Add missing dependency in ICP. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310896
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Jessica Paquette [Mon, 14 Aug 2017 22:57:41 +0000 (22:57 +0000)]
[MachineOutliner] Only outline candidates of length >= 2
Since we don't factor in instruction lengths into outlining calculations
right now, it's never the case that a candidate could have length < 2.
Thus, we should quit early when we see such candidates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310894
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Craig Topper [Mon, 14 Aug 2017 22:11:43 +0000 (22:11 +0000)]
[InstSimplify] Teach decomposeBitTestICmp to handle non-canonical compares
This adds support non-canonical compare predicates. InstSimplify can't rely on canonicalization to have occurred.
Differential Revision: https://reviews.llvm.org/D36646
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310893
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Reid Kleckner [Mon, 14 Aug 2017 22:10:54 +0000 (22:10 +0000)]
Remove checks for debug info intrinsics in use lists, NFC
These haven't done anything since debug info intrinsics stopped
appearing in Value use lists in 2014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310892
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John Baldwin [Mon, 14 Aug 2017 21:49:38 +0000 (21:49 +0000)]
[MIPS] Implement support for -mstack-alignment.
Summary:
This is modeled on the implementation for x86 which stores the command line
option in a 'StackAlignOverride' field in MipsSubtarget and then uses this
to compute a 'stackAlignment' value in
MipsSubtarget::initializeSubtargetDependencies.
The stackAlignment() method in MipsSubTarget is renamed to getStackAlignment()
and returns the computed 'stackAlignment'.
Reviewers: sdardis
Reviewed By: sdardis
Subscribers: llvm-commits, arichardson
Differential Revision: https://reviews.llvm.org/D35874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310891
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Craig Topper [Mon, 14 Aug 2017 21:39:51 +0000 (21:39 +0000)]
Recommit r310869, "[InstSimplify][InstCombine] Modify the interface of decomposeBitTestICmp and use it in the InstSimplify"
This recommits r310869, with the moved files and no extra changes.
Original commit message:
This addresses a fixme in InstSimplify about using decomposeBitTest. This also fixes InstSimplify to handle ugt and ult compares too.
I've modified the interface a little to return only the APInt version of the mask that InstSimplify needs. InstCombine now has a small wrapper routine to create a Constant out of it. I've also dropped the returning of 0 since InstSimplify doesn't need that. So InstCombine creates a zero constant itself.
I also had to make decomposeBitTest support vectors since InstSimplify needs that.
As InstSimplify can't use something from the Transforms library, I've moved the CmpInstAnalysis code to the Analysis library.
Differential Revision: https://reviews.llvm.org/D36593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310889
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Chandler Carruth [Mon, 14 Aug 2017 21:25:00 +0000 (21:25 +0000)]
[InlineCost] Refactor the checks for different analyses to be a bit more
localized to the code that uses those analyses.
Technically, this can change behavior as we no longer require the
existence of the ProfileSummaryInfo analysis to use local profile
information via BFI. We didn't actually require the PSI to have an
interesting profile though, so this only really impacts the behavior in
non-default pass pipelines.
IMO, this makes it substantially less surprising how everything works --
before an analysis that wasn't actually used had to exist to trigger
*any* profile aware inlining. I think the new organization makes it more
obvious where various checks for profile signals happen.
Differential Revision: https://reviews.llvm.org/D36710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310888
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Andrew Kaylor [Mon, 14 Aug 2017 21:15:13 +0000 (21:15 +0000)]
Add strictfp attribute to prevent unwanted optimizations of libm calls
Differential Revision: https://reviews.llvm.org/D34163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310885
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