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Roland Levillain [Mon, 25 Jul 2016 14:57:22 +0000 (14:57 +0000)]
Merge \"Do not emit stack maps for runtime calls to ReadBarrierMarkRegX.\"
am:
de4cf16f46
Change-Id: I58975c1fa1cdc2627b5fdee0d84322b8282a6411
Roland Levillain [Mon, 25 Jul 2016 14:49:51 +0000 (14:49 +0000)]
Merge "Do not emit stack maps for runtime calls to ReadBarrierMarkRegX."
Andreas Gampe [Sat, 23 Jul 2016 06:11:47 +0000 (06:11 +0000)]
Merge \"Revert \"ART: Add dex2oat swap usage test\"\"
am:
c4aa896181
Change-Id: I61c6aa7d5057a49639312262bc74f9162c827a70
Treehugger Robot [Sat, 23 Jul 2016 06:04:13 +0000 (06:04 +0000)]
Merge "Revert "ART: Add dex2oat swap usage test""
Andreas Gampe [Sat, 23 Jul 2016 05:17:18 +0000 (05:17 +0000)]
Revert "ART: Add dex2oat swap usage test"
The test doesn't correctly exclude the target, as it will only work
on the host.
This reverts commit
ab2a54093386c85756fe78daedd11ff4408a5988.
Bug:
29259363
Change-Id: Ie50df2e6f0c63cb10359c3862ad44ee3c03d4e3b
Andreas Gampe [Fri, 22 Jul 2016 22:47:55 +0000 (22:47 +0000)]
Merge \"ART: Change run-*-tests to ANDROID_{HOST|PRODUCT}_OUT\"
am:
115c1de1f8
Change-Id: I6a977a1a3ed81c25ce20c43ee55a55c2028d20b1
Andreas Gampe [Fri, 22 Jul 2016 22:47:53 +0000 (22:47 +0000)]
Merge \"ART: Add dex2oat swap usage test\"
am:
da2b8dc3ed
Change-Id: I019cccda99f190384f57bf2e23909ed79a74dc2d
Treehugger Robot [Fri, 22 Jul 2016 22:32:08 +0000 (22:32 +0000)]
Merge "ART: Change run-*-tests to ANDROID_{HOST|PRODUCT}_OUT"
Treehugger Robot [Fri, 22 Jul 2016 22:31:37 +0000 (22:31 +0000)]
Merge "ART: Add dex2oat swap usage test"
Aart Bik [Fri, 22 Jul 2016 18:52:07 +0000 (18:52 +0000)]
Merge \"Combine offsets in loop-based dynamic BCE.\"
am:
7b922ff88b
Change-Id: I6889e535ce4ea69404562c95451bf82d70c35a23
Treehugger Robot [Fri, 22 Jul 2016 18:43:01 +0000 (18:43 +0000)]
Merge "Combine offsets in loop-based dynamic BCE."
Roland Levillain [Fri, 22 Jul 2016 16:10:06 +0000 (17:10 +0100)]
Do not emit stack maps for runtime calls to ReadBarrierMarkRegX.
* Boot image code size variation on Nexus 5X
(aosp_bullhead-userdebug build):
- total ARM64 framework Oat files size change:
115584120 bytes ->
109124728 bytes (-5.59%)
- total ARM framework Oat files size change:
97387728 bytes ->
92517584 (-5.00%)
Test: ART host and target (ARM, ARM64) tests.
Bug:
29506760
Bug:
12687968
Change-Id: I979d9fb2b4e09f4c0c7bf33af2cd91750a67f989
Aart Bik [Fri, 15 Jul 2016 00:19:43 +0000 (17:19 -0700)]
Combine offsets in loop-based dynamic BCE.
Rationale:
Similar to what I did recently for dom-based dynamic BCE, this
CL combines offsets for the tests generated for loop-based
dynamic BCE. For a set of n references, this reduces the
number of generated tests from 2*n+1 down to at most 4
(in some cases even less).
TEST: 530-checker-loops3
BUG=
27430379
Change-Id: Ic80c2563eaae23f514c1fd52965dd83bccb9d190
Vladimir Marko [Fri, 22 Jul 2016 17:06:32 +0000 (17:06 +0000)]
Merge \"ARM64/x86-64: Fix mterp fill-array-data-payload pointer calculation.\"
am:
9e27d02040
Change-Id: Ib9198592d068055b0caa2051072795cb77fc6a0f
Treehugger Robot [Fri, 22 Jul 2016 16:53:29 +0000 (16:53 +0000)]
Merge "ARM64/x86-64: Fix mterp fill-array-data-payload pointer calculation."
Vladimir Marko [Fri, 22 Jul 2016 09:52:24 +0000 (10:52 +0100)]
ARM64/x86-64: Fix mterp fill-array-data-payload pointer calculation.
Fix the pointer calculation to sign-extend the offset
instead of zero-extending it, just like we do for the switch
table pointer calculation. Clean up comments for the switch.
Test: Additional test in 412-new-array.
Change-Id: Ibb1d2d3fcb109f59280aca08de21e42edc4ce66b
Vladimir Marko [Fri, 22 Jul 2016 09:31:36 +0000 (09:31 +0000)]
Merge \"ARM64: Improve mterp cmpl/cmpg.\"
am:
41c7e2e6ac
Change-Id: I8abfa3377a1e884e46f28ce413a67e97492335e2
Vladimir Marko [Fri, 22 Jul 2016 09:24:41 +0000 (09:24 +0000)]
Merge "ARM64: Improve mterp cmpl/cmpg."
Andreas Gampe [Fri, 22 Jul 2016 00:03:12 +0000 (00:03 +0000)]
Merge changes I295c7876,Ib4b84b7b
am:
84413a7617
Change-Id: I8b32598a46cb589cdefa1937ba4b9b69926f25b9
Treehugger Robot [Thu, 21 Jul 2016 23:58:00 +0000 (23:58 +0000)]
Merge changes I295c7876,Ib4b84b7b
* changes:
ART: Remove PACKED from ArtMethod's ptr_sized_fields_
ART: Rename ArtMethod JNI field
Hiroshi Yamauchi [Thu, 21 Jul 2016 23:32:13 +0000 (23:32 +0000)]
Merge \"Use non-CAS thread flip root visitor.\"
am:
d4b7ad7135
Change-Id: I4c560952f5f4ed488d0a849feadf2a2d25e15a2b
Hiroshi Yamauchi [Thu, 21 Jul 2016 23:24:44 +0000 (23:24 +0000)]
Merge "Use non-CAS thread flip root visitor."
Andreas Gampe [Wed, 20 Jul 2016 01:27:17 +0000 (18:27 -0700)]
ART: Remove PACKED from ArtMethod's ptr_sized_fields_
Remove the PACKED(4) hack, as it's highly annoying when debugging
a 64-bit process. Instead, fix the actual offset and size computation
for cross-size accesses.
Test: m test-art-host
Change-Id: I295c78760b74b6a62946e76856f218b4eb159cdc
Andreas Gampe [Thu, 21 Jul 2016 22:36:22 +0000 (15:36 -0700)]
ART: Add dex2oat swap usage test
Add a test that checks that native alloc size goes down when using
swap, as an indication that we're actually effectively using swap.
Bug:
29259363
Test: m test-art-host-gtest-dex2oat_test
Change-Id: Ifa5aef1b97696309283de78be08699a6399a4d1d
Hiroshi Yamauchi [Thu, 21 Jul 2016 03:25:27 +0000 (20:25 -0700)]
Use non-CAS thread flip root visitor.
We don't need to use CAS to update the thread-local GC roots for the
thread flip.
Bug:
12687968
Bug:
29517059
Test: libartd.so boot. ART tests. Ritzperf EAAC.
Change-Id: Ia2acab824f756bd7d2ad501b2040233e0d394356
Andreas Gampe [Thu, 21 Jul 2016 18:32:42 +0000 (18:32 +0000)]
Merge \"ART: Make run-test temp dir consistent\"
am:
a8f4e9061a
Change-Id: I1d785103a7e4df2884384b0b482552a8e163e9f3
Andreas Gampe [Tue, 19 Jul 2016 15:06:07 +0000 (08:06 -0700)]
ART: Rename ArtMethod JNI field
The field is multi-purpose, rename it to data and clean up
accessors in preparation of more checks.
Test: m test-art-host
Change-Id: Ib4b84b7b1a51ca201544bc488ce8770aa858c7fd
Treehugger Robot [Thu, 21 Jul 2016 18:26:27 +0000 (18:26 +0000)]
Merge "ART: Make run-test temp dir consistent"
Mathieu Chartier [Thu, 21 Jul 2016 17:10:02 +0000 (17:10 +0000)]
Merge \"Add a way to measure read barrier slow paths\"
am:
d8b668fbb6
Change-Id: I010c834dc4c922e7986854cba12612823fa974b4
Andreas Gampe [Thu, 21 Jul 2016 04:09:29 +0000 (21:09 -0700)]
ART: Make run-test temp dir consistent
We use the username as a directory component in run-test. Use the
same when driven through the Makefile.
Drop the username in run-test when TMP_DIR is set.
Test: m test-art-host-run-test
Test: art/test/run-test --host 001-HelloWorld
Change-Id: I060997ffbd80cd4da30dd6ac8d3954641de3292b
Mathieu Chartier [Thu, 21 Jul 2016 16:52:44 +0000 (16:52 +0000)]
Merge "Add a way to measure read barrier slow paths"
Vladimir Marko [Thu, 21 Jul 2016 11:59:46 +0000 (12:59 +0100)]
ARM64: Improve mterp cmpl/cmpg.
Use CSET+CNEG instead of MOV+CNEG+CSEL. Prefer the
CNEG/CSET alias over the CSNEG/CSINC for readability.
Test: Run ART test suite on Nexus 9 with the interpreter.
Change-Id: I5c4fb0cf2c053904253e8e82f3e7e05c774b0583
Goran Jakovljevic [Thu, 21 Jul 2016 14:24:26 +0000 (14:24 +0000)]
Merge \"Change return type of artIsAssignableFromCode for MIPS64\"
am:
b78b3a8d93
Change-Id: Ifcc0f61101ab0a424273b97877fbb444864fdce9
Roland Levillain [Thu, 21 Jul 2016 14:24:23 +0000 (14:24 +0000)]
Merge \"Fix the definition of MACRO_LITERAL for OS X on x86-64.\"
am:
ed33b7357c
Change-Id: Ida4c2fd8c2918b77c72423fdda7cd7fb52c10aab
Treehugger Robot [Thu, 21 Jul 2016 14:19:33 +0000 (14:19 +0000)]
Merge "Change return type of artIsAssignableFromCode for MIPS64"
Roland Levillain [Thu, 21 Jul 2016 14:17:40 +0000 (14:17 +0000)]
Merge "Fix the definition of MACRO_LITERAL for OS X on x86-64."
Roland Levillain [Tue, 5 Jul 2016 17:55:32 +0000 (18:55 +0100)]
Fix the definition of MACRO_LITERAL for OS X on x86-64.
Test: "ART_USE_READ_BARRIER=true mmma art" on OS X.
Change-Id: Ia2d4c7a3eb7fec346ddfa4c7b0f7b700f1137344
Goran Jakovljevic [Thu, 21 Jul 2016 12:21:46 +0000 (14:21 +0200)]
Change return type of artIsAssignableFromCode for MIPS64
This has been missed by Ic505befc6c94e2dccbc8abf2b13d4c2d662e68d1.
This fixes MIPS64 build.
Bug:
30232671
Test: make -j 32 out/target/product/generic_mips64/obj/SHARED_LIBRARIES/libart_intermediates/arch/mips64/entrypoints_init_mips64.o
Change-Id: Iec89d25e2d38c6efc0d1025767d0ac2a8bdb7dcd
Roland Levillain [Thu, 21 Jul 2016 12:15:16 +0000 (12:15 +0000)]
Merge \"Move caller-saves saving/restoring to ReadBarrierMarkRegX.\"
am:
057361ca33
Change-Id: I91d856a7d188afb7f770beb6eb799351bfe9333d
Roland Levillain [Thu, 21 Jul 2016 12:11:15 +0000 (12:11 +0000)]
Merge "Move caller-saves saving/restoring to ReadBarrierMarkRegX."
Vladimir Marko [Thu, 21 Jul 2016 10:37:41 +0000 (10:37 +0000)]
Merge \"Clean up Class::FindStaticField().\"
am:
65ad9b3516
Change-Id: Ide965af3c183fe6f4bf1abd0c535ea2914522999
Vladimir Marko [Thu, 21 Jul 2016 10:33:13 +0000 (10:33 +0000)]
Merge "Clean up Class::FindStaticField()."
Roland Levillain [Wed, 20 Jul 2016 10:32:19 +0000 (11:32 +0100)]
Move caller-saves saving/restoring to ReadBarrierMarkRegX.
Instead of saving/restoring live caller-save registers
before/after the call to read barrier mark entry points
ReadBarrierMarkRegX, have these entry points save/restore
all the caller-save registers themselves (except register
rX, which contains the return value).
Also refactor the assembly code of these entry points
using macros.
* Boot image code size variation on Nexus 5X
(aosp_bullhead-userdebug build):
- total ARM64 framework Oat files size change:
119196792 bytes ->
115575920 bytes (-3.04%)
- total ARM framework Oat files size change:
100435212 bytes ->
97621188 bytes (-2.80%)
* Benchmarks (ARM64) score variations on Nexus 5X
(aosp_bullhead-userdebug build):
- RitzPerf (lower is better)
- average score difference: -2.71%
- CaffeineMark (higher is better)
- no real difference for most tests
(absolute variation lower than 1%)
- better score on the "Method" benchmark:
score variation 41253 -> 44891 (+8.82%)
Test: ART host and target (ARM, ARM64) tests.
Bug:
29506760
Bug:
12687968
Change-Id: I881bf73139a3f1c2bee9ffc6fc8c00f9a392afa6
Artem Serov [Thu, 21 Jul 2016 09:22:09 +0000 (09:22 +0000)]
Merge \"ARM: Port instr simplification of array accesses.\"
am:
a92938a17b
Change-Id: Ia08b62cc89dd2cfecf9c543ed75689f07baf8ced
Vladimir Marko [Thu, 21 Jul 2016 09:22:06 +0000 (09:22 +0000)]
Merge changes Ibcc11ce7,I9867dc11
am:
89b03e0cfb
Change-Id: I841c764e1c9a69778ce840ec025815d20e1a06ab
Vladimir Marko [Thu, 21 Jul 2016 09:17:15 +0000 (09:17 +0000)]
Merge "ARM: Port instr simplification of array accesses."
Artem Serov [Wed, 6 Jul 2016 15:23:04 +0000 (16:23 +0100)]
ARM: Port instr simplification of array accesses.
After changing the addressing mode for array accesses (in
https://android-review.googlesource.com/248406) the 'add'
instruction that calculates the base address for the array can be
shared across accesses to the same array.
Before https://android-review.googlesource.com/248406:
add IP, r[Array], r[Index0], LSL #2
ldr r0, [IP, #12]
add IP, r[Array], r[Index1], LSL #2
ldr r0, [IP, #12]
Before this CL:
add IP. r[Array], #12
ldr r0, [IP, r[Index0], LSL #2]
add IP. r[Array], #12
ldr r0, [IP, r[Index1], LSL #2]
After this CL:
add IP. r[Array], #12
ldr r0, [IP, r[Index0], LSL #2]
ldr r0, [IP, r[Index1], LSL #2]
Link to the original optimization:
https://android-review.googlesource.com/#/c/127310/
Test: Run ART test suite on Nexus 6.
Change-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f
Vladimir Marko [Thu, 21 Jul 2016 09:15:23 +0000 (09:15 +0000)]
Merge changes Ibcc11ce7,I9867dc11
* changes:
ARM64: Improve Mterp.
ARM64: Fix mterp switch table pointer calculation.
Mathieu Chartier [Thu, 14 Jul 2016 20:30:03 +0000 (13:30 -0700)]
Add a way to measure read barrier slow paths
If enabled, this option counts number of slow paths, measures the
total slow path time per GC and records the info into a histogram.
Also added support for systrace to see which threads are performing
slow paths.
Added runtime option -Xgc:measure to enable. The info is dumped
for SIGQUIT.
Test: Volantis boot with CC, test-art-host with CC, run EEAC with CC
and -Xgc:measure
Bug:
30162165
Change-Id: I3c2bdb4156065249c45695f13c77c0579bc8e57a
Matthew Gharrity [Thu, 21 Jul 2016 00:14:11 +0000 (00:14 +0000)]
Merge \"Revert \"Revert \"Refactor GetIMTIndex\"\"\"
am:
e4b1c86d13
Change-Id: I496ad384317e215aa09e1390079fdfe3f852723e
Treehugger Robot [Thu, 21 Jul 2016 00:04:52 +0000 (00:04 +0000)]
Merge "Revert "Revert "Refactor GetIMTIndex"""
Alex Light [Wed, 20 Jul 2016 22:16:34 +0000 (22:16 +0000)]
Merge \"Make stream tracing have a higher thread count on host\"
am:
ce1ba111bf
Change-Id: Ib482cc8e3eb49aac849a809fb4d47368abfffa77
Treehugger Robot [Wed, 20 Jul 2016 22:08:47 +0000 (22:08 +0000)]
Merge "Make stream tracing have a higher thread count on host"
Alex Light [Wed, 20 Jul 2016 17:43:39 +0000 (10:43 -0700)]
Make stream tracing have a higher thread count on host
Test: mma ART_TEST_TRACE_STREAM=true -j40 test-art-host-run-test-debug-prebuild-optimizing-relocate-stream-cms-checkjni-image-npictest-ndebuggable-001-HelloWorld32
Bug:
30229615
Change-Id: Id396f569b9e21ff764562005624aabc964d4e95a
Matthew Gharrity [Wed, 20 Jul 2016 20:42:58 +0000 (20:42 +0000)]
Merge \"Refactor register allocation to be pluggable\"
am:
8a759904d4
Change-Id: I7dcf31e96d0eb23f794da94c4268804ab22d82dc
Treehugger Robot [Wed, 20 Jul 2016 20:38:30 +0000 (20:38 +0000)]
Merge "Refactor register allocation to be pluggable"
Matthew Gharrity [Wed, 20 Jul 2016 19:48:24 +0000 (19:48 +0000)]
Merge \"Fix accidental pass-by-value\"
am:
27d99ed243
Change-Id: Iab0f6c30f77a0764a11ce094d05a79e81d28685e
Treehugger Robot [Wed, 20 Jul 2016 19:42:28 +0000 (19:42 +0000)]
Merge "Fix accidental pass-by-value"
Richard Uhler [Wed, 20 Jul 2016 18:28:17 +0000 (18:28 +0000)]
Merge changes I328ea51d,I577c5d02
am:
6c81dfeaef
Change-Id: I18b7d076b1db11560f4ee4488a5c4f5f8093ffa5
Treehugger Robot [Wed, 20 Jul 2016 18:22:10 +0000 (18:22 +0000)]
Merge changes I328ea51d,I577c5d02
* changes:
Compute oat and odex filenames eagerly.
Make a static OatFileAssistant::DexLocationToOatFileName function.
Vladimir Marko [Wed, 20 Jul 2016 13:25:30 +0000 (14:25 +0100)]
ARM64: Improve Mterp.
Several straight-forward optimizations:
- use ubfx instead of SHR+AND,
- do not mask shifting distance,
- use 64-bit LDRSH to avoid subsequent sign extension,
- use CBNZ instead of CMP+BNE for null checks,
- style: use SXTW alias instead of explicit SBFM.
Test: Run ART test suite on Nexus 9 with the interpreter.
Change-Id: Ibcc11ce7f455432ecb789f727da21f269f8370f0
Vladimir Marko [Wed, 20 Jul 2016 16:52:51 +0000 (17:52 +0100)]
ARM64: Fix mterp switch table pointer calculation.
Do not mix 32-bit and 64-bit registers with
add x0, xPC, w0, lsl #1
that ends up compiled as
add x0, xPC, w0, uxtx #1
instead of the required sxtx. Just sing-extend the offset
correctly in previous instructions.
Test: Additional test in 501-regression-packed-switch.
Change-Id: I9867dc1180743e98f9707a312241d2f5b726ca8c
Matthew Gharrity [Wed, 20 Jul 2016 17:13:45 +0000 (10:13 -0700)]
Fix accidental pass-by-value
Change-Id: I245111eabb43368875c1215ca4f3a1f1918492fe
Matthew Gharrity [Thu, 14 Jul 2016 20:24:00 +0000 (13:24 -0700)]
Refactor register allocation to be pluggable
Allow alternate register allocation strategies to be implemented
in subclasses of a common register allocation base class.
Test: m test-art-host
Change-Id: I7c5866aa9ddff8f53fcaf721bad47654ab221b4f
Andreas Gampe [Wed, 20 Jul 2016 12:07:24 +0000 (12:07 +0000)]
Merge \"ART: Change return types of field access entrypoints\"
am:
360b4b0137
Change-Id: I98f4f6ea89d48f5405da245c94ff7bddb0b5d588
Vladimir Marko [Wed, 20 Jul 2016 12:01:15 +0000 (12:01 +0000)]
Merge "ART: Change return types of field access entrypoints"
Nicolas Geoffray [Wed, 20 Jul 2016 10:59:18 +0000 (10:59 +0000)]
Merge \"Fix test after rename.\"
am:
522da11a6c
Change-Id: Iefbef3b21a47951c736522079a780884308a4dc5
Nicolas Geoffray [Wed, 20 Jul 2016 10:53:11 +0000 (10:53 +0000)]
Merge "Fix test after rename."
Nicolas Geoffray [Wed, 20 Jul 2016 10:49:47 +0000 (11:49 +0100)]
Fix test after rename.
bug:
29964720
Change-Id: I37cebc40ca83597b159eefbc492e8cc105996306
Andreas Gampe [Wed, 20 Jul 2016 05:34:53 +0000 (22:34 -0700)]
ART: Change return types of field access entrypoints
Ensure that return types guarantee full-width data as the compiled
code and mterp expect by using size_t and ssize_t.
This fixes Clang no longer sign-/zero-extending small return types.
Bug:
30232671
Test: m ART_TEST_RUN_TEST_NDEBUG=true ART_TEST_INTERPRETER=true test-art-host-run-test
Change-Id: Ic505befc6c94e2dccbc8abf2b13d4c2d662e68d1
Nicolas Geoffray [Wed, 20 Jul 2016 10:36:17 +0000 (10:36 +0000)]
Merge \"JIT: Don\'t update the dex cache of another class loader.\"
am:
79e7324514
Change-Id: Iebb37f437c9dfd2693e30b76d55eedc3754653c4
Nicolas Geoffray [Wed, 20 Jul 2016 10:30:09 +0000 (10:30 +0000)]
Merge "JIT: Don't update the dex cache of another class loader."
Artem Serov [Wed, 20 Jul 2016 09:28:14 +0000 (09:28 +0000)]
Merge \"ARM: Change mem address mode for array accesses.\"
am:
c17e6d3f0d
Change-Id: I2d7b575279de5633edb5cfe22167fcfd7cdd8267
Vladimir Marko [Wed, 20 Jul 2016 09:20:55 +0000 (09:20 +0000)]
Merge "ARM: Change mem address mode for array accesses."
Artem Serov [Mon, 11 Jul 2016 13:02:34 +0000 (14:02 +0100)]
ARM: Change mem address mode for array accesses.
Switch from:
add IP, r[Array], r[Index], LSL #2
ldr r0, [IP, #12]
To:
add IP. r[Array], #12
ldr r0, [IP, r[Index], LSL #2]
These is a base for the future TryExtractArrayAccessAddress
optimization port to arm.
Test: aosp_shamu-userdebug boots and passes "m test-art-target".
Change-Id: I6ab01ba3271a8f79599ddd91a6b63cd1b37d2d67
Matthew Gharrity [Wed, 20 Jul 2016 00:05:08 +0000 (00:05 +0000)]
Merge \"Refactor SSA deconstruction into its own class\"
am:
dc4f4d42aa
Change-Id: Ie844ec62bcea08ad24ac0a6682adbf632e4e69e3
Treehugger Robot [Wed, 20 Jul 2016 00:02:38 +0000 (00:02 +0000)]
Merge "Refactor SSA deconstruction into its own class"
Hiroshi Yamauchi [Tue, 19 Jul 2016 23:44:05 +0000 (23:44 +0000)]
Merge \"Tune the GC ergnomics for the read barrier config.\"
am:
0331aa7274
Change-Id: Ib31f3c99bee9236746b8ac5eb5615bd794abeb29
Pirama Arumuga Nainar [Tue, 19 Jul 2016 23:40:18 +0000 (23:40 +0000)]
Merge \"Disable warnings triggered in Clang r271374\"
am:
73e83ec579
Change-Id: I7badac5ae194cda9411ea2856a30e4add8fc1ed8
Treehugger Robot [Tue, 19 Jul 2016 22:07:57 +0000 (22:07 +0000)]
Merge "Tune the GC ergnomics for the read barrier config."
Stephen Hines [Tue, 19 Jul 2016 22:02:31 +0000 (22:02 +0000)]
Merge "Disable warnings triggered in Clang r271374"
Matthew Gharrity [Tue, 19 Jul 2016 21:32:52 +0000 (21:32 +0000)]
Revert "Revert "Refactor GetIMTIndex""
Originally reverted in order to revert
https://android-review.googlesource.com/#/c/244190/
but can now be merged again.
This reverts commit
d4ceecc85a5aab2ec23ea1bd010692ba8c8aaa0c.
Test: m test-art-host
Change-Id: Id9205f2b77a378fc0f06088e78c66e81a49f712d
Matthew Gharrity [Mon, 18 Jul 2016 20:38:44 +0000 (13:38 -0700)]
Refactor SSA deconstruction into its own class
Test: m test-art-host
Change-Id: Ie82c2802f76f27512ef922ba583caeccf5675063
Pirama Arumuga Nainar [Tue, 28 Jun 2016 17:51:10 +0000 (10:51 -0700)]
Disable warnings triggered in Clang r271374
http://b/
28149048
http://b/
29823425
Disable -Wconstant-conversion and -Wundefined-var-template. The second
bug above tracks that these warnings get reenabled.
Test: Tested build, boot and common usage for Arm, Arm64, x86, x86_64,
Mips images in AOSP and internal branch.
Change-Id: Iea20cf6b5dbec3247b55cf8130f88202e786e367
Hiroshi Yamauchi [Tue, 19 Jul 2016 00:07:26 +0000 (17:07 -0700)]
Tune the GC ergnomics for the read barrier config.
Add 1.0 to the heap growth multiplier for the read barrier config, which
reduces the GC frequency down to roughly the same as CMS in one of the
jank tests.
Bug:
29517059
Bug:
12687968
Test: ART run-tests.
Change-Id: I1302a2f17e862f152d2f92bc06a65c9e6defcba0
Nicolas Geoffray [Tue, 19 Jul 2016 16:06:23 +0000 (17:06 +0100)]
JIT: Don't update the dex cache of another class loader.
This only works for properly delegating class loaders. But Java allows
non-delegating ones :(
bug:
29964720
Change-Id: I8b785e6cdfe9a2b77322521a02b8e59ec332ad83
test:612-jit-dex-cache
Richard Uhler [Tue, 19 Apr 2016 20:24:41 +0000 (13:24 -0700)]
Compute oat and odex filenames eagerly.
Because we almost always need both of them anyway, and they aren't
expensive to compute.
Test: oat file assistant tests.
Change-Id: I328ea51da6eb8700329f829a0458b02e12d1ee9e
Richard Uhler [Tue, 19 Apr 2016 20:08:04 +0000 (13:08 -0700)]
Make a static OatFileAssistant::DexLocationToOatFileName function.
So that you can figure out an oat file name without instantiating an
OatFileAssistant object.
Test: oat file assistant tests.
Change-Id: I577c5d02225f926086e9833d45b88d8a92db52fa
Artem Serov [Tue, 19 Jul 2016 12:42:42 +0000 (12:42 +0000)]
Merge \"ARM: Fix shifted register offset mem address mode for load signed.\"
am:
bae13af2fc
Change-Id: I0c647d242f865e8a67dce0ef17388e7113a2f6a7
Vladimir Marko [Tue, 19 Jul 2016 12:37:33 +0000 (12:37 +0000)]
Merge "ARM: Fix shifted register offset mem address mode for load signed."
Artem Serov [Mon, 11 Jul 2016 13:00:46 +0000 (14:00 +0100)]
ARM: Fix shifted register offset mem address mode for load signed.
For example 'ldrsh r0, [sp, r1, LSL #2]' previously
was assembled as 'ldrh'.
Test: New test in assembler_thumb2_test.cc .
Change-Id: I1d30724f0c2745b131876bffefdc0a780d76f6a1
Mathieu Chartier [Mon, 18 Jul 2016 23:04:22 +0000 (23:04 +0000)]
Merge \"Do allocation fence before pushing on allocation stack\"
am:
2be946bbf9
Change-Id: I9506c94419d6fcddeba63264fbc75c83ac1c4ffa
Treehugger Robot [Mon, 18 Jul 2016 22:53:44 +0000 (22:53 +0000)]
Merge "Do allocation fence before pushing on allocation stack"
Andreas Gampe [Mon, 18 Jul 2016 21:56:56 +0000 (14:56 -0700)]
ART: Change run-*-tests to ANDROID_{HOST|PRODUCT}_OUT
Use ANDROID_{HOST|PRODUCT}_OUT to allow OUT_DIR and OUT_DIR_COMMON_BASE
usage.
Change-Id: Ia091b9be5153518ef58fc7686cb77669e7c1ca54
Test: art/tools/run-jdwp-tests
Test: art/tools/run-libcore-tests --mode=host
Mathieu Chartier [Mon, 18 Jul 2016 18:11:45 +0000 (11:11 -0700)]
Do allocation fence before pushing on allocation stack
Heap::VisitObjects relies on having valid classes for objects in
the allocation stack. If the writes reorder, the thread calling
VisitObjects could see the free list pointer instead of the class
of the object. I believe this is causing crashes in VisitObjects.
Bug:
28790624
Test: Volantis booted
Change-Id: I0f2d4097de1ef3f5caf670ecc977d4d6837872ca
Matthew Gharrity [Mon, 18 Jul 2016 19:47:48 +0000 (19:47 +0000)]
Merge \"Rename current register allocator implementation\"
am:
0c67ddaff8
Change-Id: I7adac5a5f5a9ba63fcb0097d94b31ede77597e98
Treehugger Robot [Mon, 18 Jul 2016 19:35:11 +0000 (19:35 +0000)]
Merge "Rename current register allocator implementation"
Andreas Gampe [Mon, 18 Jul 2016 18:57:44 +0000 (18:57 +0000)]
Merge \"ART: Fix run-test script\"
am:
64a73d790d
Change-Id: I9dd051ba4a63c536a1a45ac7a30bc80cd380f5ff
Treehugger Robot [Mon, 18 Jul 2016 18:49:56 +0000 (18:49 +0000)]
Merge "ART: Fix run-test script"
Andreas Gampe [Sat, 25 Jun 2016 05:30:29 +0000 (22:30 -0700)]
ART: Fix run-test script
Don't assume out is under BUILD_TOP.
Test: run-test with OUT_DIR_COMMON_BASE set
Change-Id: Iba408e807e6a15ff60de54d6d4d653814d4b11d0