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Sam Clegg [Wed, 3 Apr 2019 02:30:35 +0000 (02:30 +0000)]
Fix TargetLibraryInfoTest.ValidProto after rL357552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357559
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Matt Arsenault [Wed, 3 Apr 2019 01:58:57 +0000 (01:58 +0000)]
AMDGPU: Assume ECC is enabled by default if supported
The test should really be checking for the property directly in the
code object headers, but there are problems with this. I don't see
this directly represented in the text form, and for the binary
emission this is depending on a function level subtarget feature to
emit a global flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357558
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Alon Zakai [Wed, 3 Apr 2019 01:08:35 +0000 (01:08 +0000)]
[WebAssembly] Add Emscripten OS definition + small_printf
The Emscripten OS provides a definition of __EMSCRIPTEN__, and also that it
supports iprintf optimizations.
Also define small_printf optimizations, which is a printf with float support
but not long double (which in wasm can be useful since long doubles are 128
bit and force linking of float128 emulation code). This part is based on
sunfish's https://reviews.llvm.org/D57620 (which can't land yet since
the WASI integration isn't ready yet).
Differential Revision: https://reviews.llvm.org/D60167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357552
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Matt Arsenault [Wed, 3 Apr 2019 00:25:06 +0000 (00:25 +0000)]
InstSimplify: Fold round intrinsics from sitofp/uitofp
https://godbolt.org/z/gEMRZb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357549
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Sam Clegg [Wed, 3 Apr 2019 00:17:29 +0000 (00:17 +0000)]
[WebAssembly] Remove unneeded target operand flags
This change is in preparation for the addition of new target
operand flags for new relocation types. Have a symbol type as part
of the flag set makes it harder to use and AFAICT these are serving
no purpose.
Differential Revision: https://reviews.llvm.org/D60014
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357548
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Craig Topper [Wed, 3 Apr 2019 00:05:03 +0000 (00:05 +0000)]
[X86] Update the test case for v4i1 bitselect in combine-bitselect.ll to not have an infinite loop in IR.
In fact we don't even need a loop at all. I backed out the bug fix this was testing for and verified that this new case hit the same issue.
This should stop D59626 from deleting some of this code by realizing it was dead due to the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357544
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Craig Topper [Wed, 3 Apr 2019 00:04:57 +0000 (00:04 +0000)]
[X86] Autogenerate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357543
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Matt Arsenault [Wed, 3 Apr 2019 00:01:05 +0000 (00:01 +0000)]
AMDGPU: Remove unnecessary subtarget get
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357542
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Matt Arsenault [Wed, 3 Apr 2019 00:01:03 +0000 (00:01 +0000)]
AMDGPU: Fix names for generation features
We should overall stop using these, but the uppercase name didn't
work. Any feature string is converted to lowercase, so these
could never be found in the table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357541
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Matt Arsenault [Wed, 3 Apr 2019 00:00:58 +0000 (00:00 +0000)]
AMDGPU: Don't use the default cpu in a few tests
Avoids unnecessary test changes in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357539
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Jessica Paquette [Tue, 2 Apr 2019 22:46:31 +0000 (22:46 +0000)]
[GlobalISel] Add IRTranslator support for llvm.stacksave and llvm.stackrestore
Also update arm64-irtranslator.ll.
Differential Revision: https://reviews.llvm.org/D60140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357538
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Stanislav Mekhanoshin [Tue, 2 Apr 2019 22:44:46 +0000 (22:44 +0000)]
X86: regenerate speculative-load-hardening-indirect.ll tests. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357537
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Reid Kleckner [Tue, 2 Apr 2019 22:11:58 +0000 (22:11 +0000)]
[COFF] Reduce the size of Chunk and SectionChunk, NFC
Summary:
Reorder the fields in both to use padding more efficiently, and add more
comments on the purpose of the fields.
Replace `std::vector<SectionChunk*> AssociativeChildren` with a
singly-linked list. This avoids the separate vector allocation to list
associative children, and shrinks the 3 pointers used for the typically
empty vector down to 1.
In the end, this reduces the sum of heap allocations used to link
browser_tests.exe with NO PDB by 13.10%, going from 2,248,728 KB to
1,954,071 KB of heap. These numbers exclude memory mapped files, which
are of course a significant factor in LLD's memory usage.
Reviewers: ruiu, mstorsjo, aganea
Subscribers: jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59797
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357535
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Craig Topper [Tue, 2 Apr 2019 20:52:16 +0000 (20:52 +0000)]
[X86] Mark the default case of the X86InstrInfo::convertToThreeAddress switch as unreachable.
This function should only be called with instructions that are really convertible. And all
convertible instructions need to be handled by the switch. So nothing should use the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357529
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Craig Topper [Tue, 2 Apr 2019 20:52:10 +0000 (20:52 +0000)]
[X86] Check MI.isConvertibleTo3Addr() before calling convertToThreeAddress in X86FixupLEAs.
X86FixupLEAs just assumes convertToThreeAddress will return nullptr for any instruction that isn't convertible.
But the code in convertToThreeAddress for X86 assumes that any instruction coming in has at least 2 operands and that the second one is a register. But those properties aren't guaranteed of all instructions. We should check the instruction property first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357528
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Craig Topper [Tue, 2 Apr 2019 20:52:04 +0000 (20:52 +0000)]
[TableGen] Properly calculate the minimum size needed or ConvertFn in GenAsmmatcher.inc files
We were using the number of Matchables rather than the number of rows in the converter table.
This only matters for a few of the targets where the number of matchables is more than 255, but the number of converters is less than 255. Many of the targets have more than 256 converters. So already required a uint16_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357527
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Sanjay Patel [Tue, 2 Apr 2019 20:24:06 +0000 (20:24 +0000)]
[x86] add more tests for FP scalarization; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357523
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David Bolvansky [Tue, 2 Apr 2019 20:21:26 +0000 (20:21 +0000)]
[InstCombine] Added tests for PR41337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357522
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David Bolvansky [Tue, 2 Apr 2019 20:13:28 +0000 (20:13 +0000)]
[InstCombine] Simplify ctlz/cttz with bitreverse
Summary: Fixes PR41273
Reviewers: spatel
Reviewed By: spatel
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357521
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Jessica Paquette [Tue, 2 Apr 2019 19:57:26 +0000 (19:57 +0000)]
[AArch64][GlobalISel] Select llvm.aarch64.stlxr(i64, i64*)
This adds partial instruction selection support for llvm.aarch64.stlxr. It also
factors out selection for G_INTRINSIC_W_SIDE_EFFECTS into its own function. The
new function removes the restriction that the intrinsic ID on the
G_INTRINSIC_W_SIDE_EFFECTS be on operand 0.
Also add a test, and add a GISel line to arm64-ldxr-stxr.ll.
Differential Revision: https://reviews.llvm.org/D60100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357518
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Rainer Orth [Tue, 2 Apr 2019 18:38:23 +0000 (18:38 +0000)]
[FileCheck] Fix FileCheck.cpp compilation on Solaris
Both LLVM 8.0.0 and current trunk fail to compile on Solaris with GCC 8.1.0:
/vol/llvm/src/llvm/dist/utils/FileCheck/FileCheck.cpp: In function ‘void DumpAnnotatedInput(llvm::raw_ostream&, const llvm::FileCheckRequest&, llvm::StringRef, std::vector<InputAnnotation>&, unsigned int)’:
/vol/llvm/src/llvm/dist/utils/FileCheck/FileCheck.cpp:408:41: error: call of overloaded ‘log10(unsigned int&)’ is ambiguous
unsigned LineNoWidth = log10(LineCount) + 1;
^
In file included from /vol/gcc-8/lib/gcc/i386-pc-solaris2.11/8.1.0/include-fixed/math.h:24,
from /vol/gcc-8/include/c++/8.1.0/cmath:45,
from /vol/llvm/src/llvm/dist/include/llvm-c/DataTypes.h:28,
from /vol/llvm/src/llvm/dist/include/llvm/Support/DataTypes.h:16,
from /vol/llvm/src/llvm/dist/include/llvm/ADT/Hashing.h:47,
from /vol/llvm/src/llvm/dist/include/llvm/ADT/ArrayRef.h:12,
from /vol/llvm/src/llvm/dist/include/llvm/Support/CommandLine.h:22,
from /vol/llvm/src/llvm/dist/utils/FileCheck/FileCheck.cpp:18:
/vol/gcc-8/lib/gcc/i386-pc-solaris2.11/8.1.0/include-fixed/iso/math_iso.h:209:21: note: candidate: ‘long double std::log10(long double)’
inline long double log10(long double __X) { return __log10l(__X); }
^~~~~
/vol/gcc-8/lib/gcc/i386-pc-solaris2.11/8.1.0/include-fixed/iso/math_iso.h:170:15: note: candidate: ‘float std::log10(float)’
inline float log10(float __X) { return __log10f(__X); }
^~~~~
/vol/gcc-8/lib/gcc/i386-pc-solaris2.11/8.1.0/include-fixed/iso/math_iso.h:70:15: note: candidate: ‘double std::log10(double)’
extern double log10 __P((double));
^~~~~
Fixed by using std::log10 instead, which allowed the compilation on i386-pc-solaris2.11
and sparc-sun-solaris2.11 to continue.
Differential Revision: https://reviews.llvm.org/D60043
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357509
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David Bolvansky [Tue, 2 Apr 2019 18:33:54 +0000 (18:33 +0000)]
[InstCombine] Added tests for PR41273
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357508
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Francis Visoiu Mistrih [Tue, 2 Apr 2019 17:48:55 +0000 (17:48 +0000)]
[Remarks][NFCI] Remove useless include
Remarks.h only uses LLVMBool, which comes from llvm-c/Types.h. Nothing
from llvm-c/Core.h is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357503
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Vedant Kumar [Tue, 2 Apr 2019 17:42:17 +0000 (17:42 +0000)]
[ArgPromotion] Set debug location at updated callsites
Set the correct debug location on instructions which load arguments in
preparation for a call to an arg-promoted function.
This prevents location cascade from misattributing the line/scope of one
of these loads to the location of the instruction preceding the call.
Differential Revision: https://reviews.llvm.org/D60113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357500
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Vedant Kumar [Tue, 2 Apr 2019 17:28:34 +0000 (17:28 +0000)]
[DebugInfo] Fix pr41180 : Loop Vectorization Debugify Failure
Bug: https://bugs.llvm.org/show_bug.cgi?id=41180
In the bug test case the debug location was missing for the cmp instruction in
the "middle block" BB. This patch fixes the bug by copying the debug location
from the cmp of the scalar loop's terminator branch, if it exists.
The patch also fixes the debug location on the subsequent branch instruction.
It was previously using the location of the of the original loop's pre-header
block terminator. Both of these instructions will now map to the source line of
the conditional branch in the original loop.
A regression test has been added that covers these issues.
Patch by Orlando Cazalet-Hyams!
Differential Revision: https://reviews.llvm.org/D59944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357499
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Sanjay Patel [Tue, 2 Apr 2019 17:20:54 +0000 (17:20 +0000)]
[DAGCombiner] reduce code duplication; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357498
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Craig Topper [Tue, 2 Apr 2019 17:13:03 +0000 (17:13 +0000)]
[X86] Allow FixupLEAs to form INC/DEC under OptSize not just MinSize
This matches our usual INC/DEC heuristic used during isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357497
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Stefan Pintilie [Tue, 2 Apr 2019 16:56:01 +0000 (16:56 +0000)]
[PowerPC] Fix reversed bit issue in DCMX mask for "xvtstdcdp" and "xvtstdcsp" P9 implementation
Did experiments on power 9 machine, checked the outputs for NaN & Infinity+
cases with corresponding DCMX bit set. Confirmed the DCMX mask bit for NaN and
infinity+ are reversed.
This patch fixes the issue.
Patch by Victor Huang.
Differential Revision: https://reviews.llvm.org/D59384
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357494
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Philip Reames [Tue, 2 Apr 2019 16:51:43 +0000 (16:51 +0000)]
[WideableCond] Fix a nasty bug in detection of "explicit guards"
The code was failing to actually check for the presence of the call to widenable_condition. The whole point of specifying the widenable_condition intrinsic was allowing widening transforms. A normal branch is not widenable. A normal branch leading to a deopt is not widenable (in general).
I added a test case via LoopPredication, but GuardWidening has an analogous bug. Those are the only two passes actually using this utility just yet. Noticed while working on LoopPredication for non-widenable branches; POC in D60111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357493
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Jordan Rupprecht [Tue, 2 Apr 2019 16:49:56 +0000 (16:49 +0000)]
[llvm-objcopy] Change SHT_NOBITS to SHT_PROBITS for some --set-section-flags
Summary:
Some flags accepted by --set-section-flags and --rename-section can change a SHT_NOBITS section to a SHT_PROGBITS section. Note that none of them can change a SHT_PROGBITS to SHT_NOBITS.
The full list (found via experimentation of individually setting each flag) that does this is: contents, load, noload, code, data, rom, and debug.
This was found by testing llvm-objcopy with the gnu binutils test suite, specifically this test case: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob;f=binutils/testsuite/binutils-all/copy-1.d;h=
f2b0d9e90df738c2891b4d5c7b62f62894b556ca;hb=HEAD
Reviewers: jhenderson, grimar, jakehehrlich, alexshap, espindola
Reviewed By: jhenderson
Subscribers: emaste, arichardson, MaskRay, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59958
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357492
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Simon Pilgrim [Tue, 2 Apr 2019 16:27:11 +0000 (16:27 +0000)]
[SLP] reorderInputsAccordingToOpcode is const method. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357490
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Fangrui Song [Tue, 2 Apr 2019 16:15:46 +0000 (16:15 +0000)]
[BPF] Replace fstream and sstream with line_iterator
Summary: This makes libLLVMBPFCodeGen.so 1128 bytes smaller for my build.
Reviewers: yonghong-song
Reviewed By: yonghong-song
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357489
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Shoaib Meenai [Tue, 2 Apr 2019 15:58:05 +0000 (15:58 +0000)]
[llvm-shlib] Fix cross-compilation for LLVM-C
When we're cross-compiling, build and use a native llvm-nm instead of
attempting to use the one from the target's build tree.
A nice follow-up would be to add a cache variable to allow specifying a
path to an external native llvm-nm instead of building one ourselves,
similar to LLVM_TABLEGEN and LLVM_CONFIG_PATH.
Differential Revision: https://reviews.llvm.org/D60025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357487
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Shoaib Meenai [Tue, 2 Apr 2019 15:58:03 +0000 (15:58 +0000)]
[cmake] Add function for building native tool
Instead of duplicating functionality for building native versions of
tblgen and llvm-config, add a function to set up a native tool build.
This will also be used for llvm-nm in a follow-up.
This should be NFC for tblgen, besides the slightly different COMMENT
for the custom command (it'll display the tablegen target name instead
of always saying TableGen). For the native llvm-config, it's a behavior
change in that we'll use llvm_ExternalProject_BuildCmd instead of
constructing the build command manually, always build in Release, and
reference the correct binary path for multi-config generators. I believe
all of these changes to be bug fixes.
Differential Revision: https://reviews.llvm.org/D60024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357486
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Joseph Tremoulet [Tue, 2 Apr 2019 15:48:58 +0000 (15:48 +0000)]
[SimplifyCFG] Don't split musttail call from ret
Summary:
When inserting an `unreachable` after a noreturn call, we must ensure
that it's not a musttail call to avoid breaking the IR invariants for
musttail calls.
Reviewers: fedor.sergeev, majnemer
Reviewed By: majnemer
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357485
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Taewook Oh [Tue, 2 Apr 2019 15:48:21 +0000 (15:48 +0000)]
[SampleProfile] Repeat indirect call promotion only when the target is actually hot.
Summary: It is possible that multiple indirect call targets have been promoted for a single callsite from the profiled binary. Current implementation repeats promotion for all these targets as far as the callsite itself is hot (the callsite is assumed to be hot if any one of these targets was "hot" during the profiling). However, even when one of the ICPed target is hot other targets may not, and we should not repeat promotion for "cold" targets.
Reviewers: danielcdh, wmi
Subscribers: hiraditya, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357484
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Joseph Tremoulet [Tue, 2 Apr 2019 15:47:11 +0000 (15:47 +0000)]
[PruneEH] Don't split musttail call from ret
Summary:
When inserting an `unreachable` after a noreturn call, we must ensure
that it's not a musttail call to avoid breaking the IR invariants for
musttail calls.
Reviewers: fedor.sergeev, majnemer
Reviewed By: majnemer
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357483
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Jonas Paulsson [Tue, 2 Apr 2019 15:36:30 +0000 (15:36 +0000)]
[SystemZ] Improve instruction selection of 64 bit shifts and rotates.
For shift and rotate instructions that only use the last 6 bits of the shift
amount, a shift amount of (x*64-s) can be substituted with (-s). This saves
one instruction and a register:
lhi %r1, 64
sr %r1, %r3
sllg %r2, %r2, 0(%r1)
=>
lcr %r1, %r3
sllg %r2, %r2, 0(%r1)
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357481
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Brian Gesiak [Tue, 2 Apr 2019 14:57:56 +0000 (14:57 +0000)]
[Transforms] Redundant getValueOperand (NFC)
`StoreInst::getValueOperand` is identical to `getOperand(0)`, so the call to
`getOperand(0)` can be replaced. Further, `SI->getValueOperand` is redundantly
called just a few lines down, despite its return value being stored in variable
`DV`. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357479
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Nico Weber [Tue, 2 Apr 2019 14:44:34 +0000 (14:44 +0000)]
gn build: Merge r357469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357477
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Nico Weber [Tue, 2 Apr 2019 14:39:34 +0000 (14:39 +0000)]
gn build: Add build files for non-framework xpc clangd bits
Differential Revision: https://reviews.llvm.org/D60124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357476
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James Henderson [Tue, 2 Apr 2019 14:11:13 +0000 (14:11 +0000)]
[llvm-objcopy]Allow llvm-objcopy to be used on an ELF file with no section headers
This patch fixes https://bugs.llvm.org/show_bug.cgi?id=41293 and
https://bugs.llvm.org/show_bug.cgi?id=41045. llvm-objcopy assumed that
it could always read a section header string table. This isn't the case
when the sections were previously all stripped, and the e_shstrndx field
was set to 0. This patch fixes this. It also fixes a double space in an
error message relating to this issue, and prevents llvm-objcopy from
adding extra space for non-existent section headers, meaning that
--strip-sections on the output of a previous --strip-sections run
produces identical output, simplifying the test.
Reviewed by: rupprecht, grimar
Differential Revision: https://reviews.llvm.org/D59989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357475
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Simon Atanasyan [Tue, 2 Apr 2019 13:57:38 +0000 (13:57 +0000)]
[mips] Remove the override of the `isMachineVerifierClean()`
All issues found by machine verifier in MIPS target have been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357473
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Simon Atanasyan [Tue, 2 Apr 2019 13:57:32 +0000 (13:57 +0000)]
[mips] Use AltOrders to prevent using odd FP-registers
To disable using of odd floating-point registers (O32 ABI and
-mno-odd-spreg command line option) such registers and their
super-registers added to the set of reserved registers. In general, it
works. But there is at least one problem - in case of enabled machine
verifier pass some floating-point tests failed because live ranges of
register units that are reserved is not empty and verification pass
failed with "Live segment doesn't end at a valid instruction" error
message.
There is D35985 patch which tries to solve the problem by explicit
removing of register units. This solution did not get approval.
I would like to use another approach for prevent using odd floating
point registers - define `AltOrders` and `AltOrderSelect` for MIPS
floating point register classes. Such `AltOrders` contains reduced set
of registers. At first glance, such solution does not break any test
cases and allows enabling machine instruction verification for all MIPS
test cases.
Differential Revision: http://reviews.llvm.org/D59799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357472
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Michael Liao [Tue, 2 Apr 2019 13:01:45 +0000 (13:01 +0000)]
[ObjectYAML] Fix build issue
- ObjectYAML depends on Object as minidump support adds additional
dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357471
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Alex Bradbury [Tue, 2 Apr 2019 12:47:20 +0000 (12:47 +0000)]
[RISCV] Support assembling @plt symbol operands
This patch allows symbols appended with @plt to parse and assemble with the
R_RISCV_CALL_PLT relocation.
Differential Revision: https://reviews.llvm.org/D55335
Patch by Lewis Revill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357470
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Pavel Labath [Tue, 2 Apr 2019 11:58:37 +0000 (11:58 +0000)]
Add minidump support to obj2yaml
Summary:
This patch adds the code needed to parse a minidump file into the
MinidumpYAML model, and the necessary glue code so that obj2yaml can
recognise the minidump files and process them.
Reviewers: jhenderson, zturner, clayborg
Subscribers: mgorny, lldb-commits, amccarth, markmentovai, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357469
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Simon Pilgrim [Tue, 2 Apr 2019 10:31:00 +0000 (10:31 +0000)]
[X86][AVX] Add test case showing failure to fold broadcast load if its also used as a scalar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357465
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Sander de Smalen [Tue, 2 Apr 2019 09:46:52 +0000 (09:46 +0000)]
Enforce StackID definition in PEI
There are various places in LLVM where the definition of StackID is not
properly honoured, for example in PEI where objects with a StackID > 0 are
allocated on the default stack (StackID0). This patch enforces that PEI
only considers allocating objects to StackID 0.
Reviewers: arsenm, thegameg, MatzeB
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D60062
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357460
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Fangrui Song [Tue, 2 Apr 2019 09:25:31 +0000 (09:25 +0000)]
[Internalize] Replace uses of std::set with DenseSet
This makes it faster and saves 104 bytes for my build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357458
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Fangrui Song [Tue, 2 Apr 2019 09:11:18 +0000 (09:11 +0000)]
[Internalize] Replace fstream with line_iterator for -internalize-public-api-file
This makes my libLLVMipo.so.9svn smaller by 360 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357457
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Hans Wennborg [Tue, 2 Apr 2019 08:01:38 +0000 (08:01 +0000)]
SimplifyCFG SinkCommonCodeFromPredecessors: Also sink function calls without used results (PR41259)
The code was previously checking that candidates for sinking had exactly
one use or were a store instruction (which can't have uses). This meant
we could sink call instructions only if they had a use.
That limitation seemed a bit arbitrary, so this patch changes it to
"instruction has zero or one use" which seems more natural and removes
the need to special-case stores.
Differential revision: https://reviews.llvm.org/D59936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357452
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Philip Reames [Tue, 2 Apr 2019 02:42:57 +0000 (02:42 +0000)]
[LoopPredication] Simplify widenable condition handling [NFC]
The code doesn't actually need any of the information about the widenable condition at this level. The only thing we need is to ensure the WC call is the last thing anded in, and even that is a quirk we should really look to remove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357448
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Nick Lewycky [Tue, 2 Apr 2019 01:05:48 +0000 (01:05 +0000)]
Add an optional list of blocks to avoid when looking for a path in isPotentiallyReachable.
The leads to some ambiguous overloads, so update three callers.
Differential Revision: https://reviews.llvm.org/D60085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357447
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Craig Topper [Tue, 2 Apr 2019 00:54:22 +0000 (00:54 +0000)]
[X86] Add test cases to fixup-lea.ll for optsize and no size optimization. Add +/-slow-incdec command lines
We only form inc/dec in FixupLEAs under minsize today, but all other locations in the compiler for inc/dec with optsize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357446
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Craig Topper [Tue, 2 Apr 2019 00:54:15 +0000 (00:54 +0000)]
[X86] Autogenerate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357445
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Craig Topper [Tue, 2 Apr 2019 00:50:58 +0000 (00:50 +0000)]
[X86] Use unsigned type for opcodes throughout X86FixupLEAs.
All of the interfaces related to opcode in MachineInstr and MCInstrInfo refer to opcodes as unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357444
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Matt Arsenault [Tue, 2 Apr 2019 00:46:19 +0000 (00:46 +0000)]
InstSimplify: Add missing case from r357386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357443
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Michael Liao [Tue, 2 Apr 2019 00:36:37 +0000 (00:36 +0000)]
[AMDGPU] Add more test cases of D59608.
Summary: - Add more test cases.
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60071
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357442
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Matt Arsenault [Tue, 2 Apr 2019 00:36:04 +0000 (00:36 +0000)]
AMDGPU: Fix test filename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357441
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Eli Friedman [Tue, 2 Apr 2019 00:01:23 +0000 (00:01 +0000)]
[ARM] Optimize expressions like "return x != 0;" for Thumb1.
There's an existing optimization for x != C, but somehow it was missing
a special case for 0.
While I'm here, also cleaned up the code/comments a bit: the second
value produced by the MERGE_VALUES was actually dead, since a CMOV only
produces one result.
Differential Revision: https://reviews.llvm.org/D59616
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357437
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Eli Friedman [Mon, 1 Apr 2019 23:55:57 +0000 (23:55 +0000)]
[ARM] Don't try to create "push {r12, lr}" in Thumb1 at -Oz.
It's a little tricky to make this issue show up because
prologue/epilogue emission normally likes to push at least two
registers... but it doesn't when lr is force-spilled due to function
length. Not sure if that really makes sense, but I decided not to touch
it for now.
Differential Revision: https://reviews.llvm.org/D59385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357436
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Philip Reames [Mon, 1 Apr 2019 22:39:54 +0000 (22:39 +0000)]
[LoopPred] Rename a variable to simply a future patch [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357433
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Jessica Paquette [Mon, 1 Apr 2019 22:19:13 +0000 (22:19 +0000)]
[AArch64][GlobalISe] Select STRQui for stores into v264s instead of scalarizing
This improves selection for vector stores into v2s64s. Before we just
scalarized them, but we can just use a STRQui instead.
Differential Revision: https://reviews.llvm.org/D60083
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357432
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Nick Lewycky [Mon, 1 Apr 2019 20:37:56 +0000 (20:37 +0000)]
[NFC] Remove dead parameter "FreeInLoop", fix some typos and trailing whitespace.
Differential Revision: https://reviews.llvm.org/D60084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357427
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Nick Lewycky [Mon, 1 Apr 2019 20:03:16 +0000 (20:03 +0000)]
Not all blocks are reachable from entry. Don't assume they are.
Fixes a bug in isPotentiallyReachable, noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357425
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Craig Topper [Mon, 1 Apr 2019 19:08:15 +0000 (19:08 +0000)]
[X86] Classify the AVX512 rounding control operand as X86::OPERAND_ROUNDING_CONTROL instead of MCOI::OPERAND_IMMEDIATE. Add an assert on legal values of rounding control in the encoder and remove an explicit mask.
This should allow llvm-exegesis to intelligently constrain the rounding mode.
The mask in the encoder shouldn't be necessary any more. We used to allow codegen to use 8-11 for rounding mode and the assembler would use 0-3 to mean the same thing so we masked here and in the printer. Codegen now matches the assembler and the printer was updated, but I forgot to update the encoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357419
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Yi Kong [Mon, 1 Apr 2019 18:12:43 +0000 (18:12 +0000)]
[llvm-objcopy] Add --keep-symbols option
Differential Revision: https://reviews.llvm.org/D60054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357418
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Simon Pilgrim [Mon, 1 Apr 2019 17:48:03 +0000 (17:48 +0000)]
[SLP] getVectorElementSize and isTreeTinyAndNotFullyVectorizable are const methods. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357416
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Simon Pilgrim [Mon, 1 Apr 2019 17:32:46 +0000 (17:32 +0000)]
[SLP] getGatherCost and isFullyVectorizableTinyTree are const methods. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357414
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Caroline Tice [Mon, 1 Apr 2019 16:29:40 +0000 (16:29 +0000)]
Commit accidentally omitted test case.
This test case was approved as part of
https://reviews.llvm.org/D49434, but was accidentally
omitted from the final commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357409
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Philip Reames [Mon, 1 Apr 2019 16:26:08 +0000 (16:26 +0000)]
[LoopPred] Be uniform about proving generated conditions
We'd been optimizing the case where the predicate was obviously true, do the same for the false case. Mostly just for completeness sake, but also may improve compile time in loops which will exit through the guard. Such loops are presumed rare in fastpath code, but may be present down untaken paths, so optimizing for them is still useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357408
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Bixia Zheng [Mon, 1 Apr 2019 16:10:26 +0000 (16:10 +0000)]
[NVPTX] Fix the codegen for llvm.round.
Summary:
Previously, we translate llvm.round to PTX cvt.rni, which rounds to the
even interger when the source is equidistant between two integers. This
is not correct as llvm.round should round away from zero. This change
replaces llvm.round with a round away from zero implementation through
target specific custom lowering.
Modify a few affected tests to not check for cvt.rni. Instead, we check
for the use of a few constants used in implementing round. We are also
adding CUDA runnable tests to check for the values produced by
llvm.round to test-suites/External/CUDA.
Reviewers: tra
Subscribers: jholewinski, sanjoy, jlebar, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357407
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Philip Reames [Mon, 1 Apr 2019 16:05:15 +0000 (16:05 +0000)]
[LoopPred] Delete the old condition expressions if unused
LoopPredication was replacing the original condition, but leaving the instructions to compute the old conditions around. This would get cleaned up by other passes of course, but we might as well do it eagerly. That also makes the test output less confusing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357406
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Philip Reames [Mon, 1 Apr 2019 15:35:30 +0000 (15:35 +0000)]
[Tests] Autogen all the LoopPredication tests
I'm about to make some changes to the pass which cause widespread - but uninteresting - test diffs. Prepare the tests for easy updating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357404
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Philip Reames [Mon, 1 Apr 2019 15:32:07 +0000 (15:32 +0000)]
[Tests] Add tests for a possible loop predication transform variant
As highlighted by tests, if one of the operands is loop variant, but guaranteed to have the same value on all iterations, we have a missed oppurtunity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357403
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Neil Henning [Mon, 1 Apr 2019 15:19:52 +0000 (15:19 +0000)]
[AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.
This change incorporates an effort by Connor Abbot to change how we deal
with WWM operations potentially trashing valid values in inactive lanes.
Previously, the SIFixWWMLiveness pass would work out which registers
were being trashed within WWM regions, and ensure that the register
allocator did not have any values it was depending on resident in those
registers if the WWM section would trash them. This worked perfectly
well, but would cause sometimes severe register pressure when the WWM
section resided before divergent control flow (or at least that is where
I mostly observed it).
This fix instead runs through the WWM sections and pre allocates some
registers for WWM. It then reserves these registers so that the register
allocator cannot use them. This results in a significant register
saving on some WWM shaders I'm working with (130 -> 104 VGPRs, with just
this change!).
Differential Revision: https://reviews.llvm.org/D59295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357400
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Nico Weber [Mon, 1 Apr 2019 14:59:50 +0000 (14:59 +0000)]
gn build: Merge r357383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357398
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David Spickett [Mon, 1 Apr 2019 14:56:37 +0000 (14:56 +0000)]
[AArch64] Add v8.5-a Memory Tagging STZGM instruction
This instruction writes a block of allocation tags
and stores zero to the associated data locations.
It differs from STGM by 1 bit and has the same
arguments.
The specification can be found here:
https://developer.arm.com/docs/ddi0596/c
Differential Revision: https://reviews.llvm.org/D60065
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357397
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Alex Bradbury [Mon, 1 Apr 2019 14:53:17 +0000 (14:53 +0000)]
[RISCV] Attach VK_RISCV_CALL to symbols upon creation
This patch replaces the addition of VK_RISCV_CALL in RISCVMCCodeEmitter by
creating the RISCVMCExpr when tail/call are parsed, or in the codegen case
when the callee symbols are created.
This required adding a new CallSymbol operand to allow only adding
VK_RISCV_CALL to tail/call instructions.
This patch will allow further expansion of parsing and codegen to easily
include PLT symbols which must generate the R_RISCV_CALL_PLT relocation.
Differential Revision: https://reviews.llvm.org/D55560
Patch by Lewis Revill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357396
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David Spickett [Mon, 1 Apr 2019 14:52:18 +0000 (14:52 +0000)]
[AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions
The STGV/LDGV instructions were replaced with
STGM/LDGM. The encodings remain the same but there
is no longer writeback so there are no unpredictable
encodings to check for.
The specfication can be found here:
https://developer.arm.com/docs/ddi0596/c
Differential Revision: https://reviews.llvm.org/D60064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357395
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Alex Bradbury [Mon, 1 Apr 2019 14:42:56 +0000 (14:42 +0000)]
[RISCV] Generate address sequences suitable for mcmodel=medium
This patch adds an implementation of a PC-relative addressing sequence to be
used when -mcmodel=medium is specified. With absolute addressing, a 'medium'
codemodel may cause addresses to be out of range. This is because while
'medium' implies a 2 GiB addressing range, this 2 GiB can be at any offset as
opposed to 'small', which implies the first 2 GiB only.
Note that LLVM/Clang currently specifies code models differently to GCC, where
small and medium imply the same functionality as GCC's medlow and medany
respectively.
Differential Revision: https://reviews.llvm.org/D54143
Patch by Lewis Revill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357393
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David Spickett [Mon, 1 Apr 2019 14:41:14 +0000 (14:41 +0000)]
[AArch64] Add v8.5-a Memory Tagging GMID_EL1 register
The latest version of the MTE spec added a system
register 'GMID_EL1'. It contains the block size used
by the LDGM and STGM instructions and is read only.
The specification can be found here:
https://developer.arm.com/docs/ddi0596/c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357392
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Mikael Holmen [Mon, 1 Apr 2019 14:10:10 +0000 (14:10 +0000)]
[InstCombine] Handle vector gep with scalar argument in evaluateInDifferentElementOrder
Summary:
This fixes PR41270.
The recursive function evaluateInDifferentElementOrder expects to be called
on a vector Value, so when we call it on a vector GEP's arguments, we must
first check that the argument is indeed a vector.
Reviewers: reames, spatel
Reviewed By: spatel
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60058
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357389
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Matt Arsenault [Mon, 1 Apr 2019 14:08:26 +0000 (14:08 +0000)]
X86: Fix override warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357388
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Mikael Holmen [Mon, 1 Apr 2019 14:06:45 +0000 (14:06 +0000)]
Revert "[InstCombine] Handle vector gep with scalar argument in evaluateInDifferentElementOrder"
This reverts commit
75216a6dbcfe5fb55039ef06a07e419fa875f4a5.
I'll recommit with a better commit message with reference to the
phabricator review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357387
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Matt Arsenault [Mon, 1 Apr 2019 14:03:44 +0000 (14:03 +0000)]
InstSimplify: Add baseline test for upcoming change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357386
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Mikael Holmen [Mon, 1 Apr 2019 13:48:56 +0000 (13:48 +0000)]
[InstCombine] Handle vector gep with scalar argument in evaluateInDifferentElementOrder
This fixes PR41270.
The recursive function evaluateInDifferentElementOrder expects to be called
on a vector Value, so when we call it on a vector GEP's arguments, we must
first check that the argument is indeed a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357385
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Clement Courbet [Mon, 1 Apr 2019 13:48:50 +0000 (13:48 +0000)]
[X86] Make post-ra scheduling macrofusion-aware.
Subscribers: MatzeB, arsenm, jvesely, nhaehnle, hiraditya, javed.absar, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357384
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Sanjay Patel [Mon, 1 Apr 2019 13:36:40 +0000 (13:36 +0000)]
[InstCombine] eliminate commuted select-shuffles + binop (PR41304)
If we have a commutable vector binop with inverted select-shuffles,
we don't care about the order of the operands in each vector lane:
LHS = shuffle V1, V2, <0, 5, 6, 3>
RHS = shuffle V2, V1, <0, 5, 6, 3>
LHS + RHS --> <V1[0]+V2[0], V2[1]+V1[1], V2[2]+V1[2], V1[3]+V2[3]> --> V1 + V2
PR41304:
https://bugs.llvm.org/show_bug.cgi?id=41304
...is currently titled as an SLP enhancement, but at least for the
given example, we can reduce that in instcombine because we are just
eliminating shuffles.
As noted in the TODO, this could be generalized, but I haven't thought
through those patterns completely, so this is limited to what appears
to be always safe.
Differential Revision: https://reviews.llvm.org/D60048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357382
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Clement Courbet [Mon, 1 Apr 2019 13:18:34 +0000 (13:18 +0000)]
[X86MacroFusion][NFC] Add more tests.
In preparation for D59688.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357381
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Krasimir Georgiev [Mon, 1 Apr 2019 11:42:54 +0000 (11:42 +0000)]
[X86] Fix a test from r357317
Summary:
The missing `<` causes the lld command to override the test file, which fails in
environments marking the test files as readonly.
Reviewers: bkramer
Reviewed By: bkramer
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357380
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Simon Pilgrim [Mon, 1 Apr 2019 10:54:04 +0000 (10:54 +0000)]
[X86][SSE] Add fcmp constant folding tests
Initial test coverage for D60006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357379
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Luis Marques [Mon, 1 Apr 2019 09:54:14 +0000 (09:54 +0000)]
[RISCV] Add seto pattern expansion
Adds a `seto` pattern expansion. Without it the lowerings of `fcmp one` and
`fcmp ord` would be inefficient due to an unoptimized double negation.
Differential Revision: https://reviews.llvm.org/D59699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357378
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Craig Topper [Mon, 1 Apr 2019 05:26:12 +0000 (05:26 +0000)]
[X86] Use ISD::INTRINSIC_VOID in getTgtMemIntrinsic for truncating stores and scatter intrinsics.
This is the appropriate opcode for only having a chain output. Though I'm not
sure it matters much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357375
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Alex Bradbury [Mon, 1 Apr 2019 02:38:27 +0000 (02:38 +0000)]
[RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation)
A pcrel_lo will point to the associated pcrel_hi fixup which in turn points to
the real target. RISCVMCExpr::evaluatePCRelLo will work around this
indirection in order to allow the fixup to be evaluate properly. However, if
relocations are forced (e.g. due to linker relaxation is enabled) then its
evaluation is undesired and will result in a relocation with the wrong target.
This patch modifies evaluatePCRelLo so it will not try to evaluate if the
fixup will be forced as a relocation. A new helper method is added to
RISCVAsmBackend to query this.
Differential Revision: https://reviews.llvm.org/D59686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357374
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Nico Weber [Sun, 31 Mar 2019 16:49:54 +0000 (16:49 +0000)]
gn build: Add build files for most clang-tools-extra unit tests
Differential Revision: https://reviews.llvm.org/D60038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357369
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Sanjay Patel [Sun, 31 Mar 2019 15:45:47 +0000 (15:45 +0000)]
[InstCombine] add tests for inverted select-shuffles + binop (PR41304); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357368
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Sanjay Patel [Sun, 31 Mar 2019 15:11:34 +0000 (15:11 +0000)]
[x86] allow movmsk with 2-element reductions
One motivation for making this change is that the lack of using movmsk is likely
a main source of perf difference between clang and gcc on the C-Ray benchmark as
shown here:
https://www.phoronix.com/scan.php?page=article&item=gcc-clang-2019&num=5
...but this change alone isn't enough to solve that problem.
The 'all-of' examples show what is likely the worst case trade-off: we end up with
an extra instruction (or 2 if we count the 'xor' register clearing). The 'any-of'
examples look clearly better using movmsk because we've traded 2 vector instructions
for 2 scalar instructions, and movmsk may have better timing than the generic 'movq'.
If we examine the llvm-mca output for these cases, it appears that even though the
'all-of' movmsk variant looks worse on paper, it would perform better on both
Haswell and Jaguar.
$ llvm-mca -mcpu=haswell no_movmsk.s -timeline
Iterations: 100
Instructions: 400
Total Cycles: 504
Total uOps: 400
Dispatch Width: 4
uOps Per Cycle: 0.79
IPC: 0.79
Block RThroughput: 1.0
$ llvm-mca -mcpu=haswell movmsk.s -timeline
Iterations: 100
Instructions: 600
Total Cycles: 358
Total uOps: 600
Dispatch Width: 4
uOps Per Cycle: 1.68
IPC: 1.68
Block RThroughput: 1.5
$ llvm-mca -mcpu=btver2 no_movmsk.s -timeline
Iterations: 100
Instructions: 400
Total Cycles: 407
Total uOps: 400
Dispatch Width: 2
uOps Per Cycle: 0.98
IPC: 0.98
Block RThroughput: 2.0
$ llvm-mca -mcpu=btver2 movmsk.s -timeline
Iterations: 100
Instructions: 600
Total Cycles: 311
Total uOps: 600
Dispatch Width: 2
uOps Per Cycle: 1.93
IPC: 1.93
Block RThroughput: 3.0
Finally, there may be CPUs where movmsk is horribly slow (old AMD small cores?), but if
that's true, then we're also almost certainly making the wrong transform already for
reductions with >2 elements, so that should be fixed independently.
Differential Revision: https://reviews.llvm.org/D59997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357367
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Sanjay Patel [Sun, 31 Mar 2019 15:01:30 +0000 (15:01 +0000)]
[InstCombine] canonicalize select shuffles by commuting
In PR41304:
https://bugs.llvm.org/show_bug.cgi?id=41304
...we have a case where we want to fold a binop of select-shuffle (blended) values.
Rather than try to match commuted variants of the pattern, we can canonicalize the
shuffles and check for mask equality with commuted operands.
We don't produce arbitrary shuffle masks in instcombine, but select-shuffles are a
special case that the backend is required to handle because we already canonicalize
vector select to this shuffle form.
So there should be no codegen difference from this change. It's possible that this
improves CSE in IR though.
Differential Revision: https://reviews.llvm.org/D60016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357366
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