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Ian Rogers [Wed, 28 May 2014 19:47:01 +0000 (19:47 +0000)]
Merge "ART: Print and dump functionalities per pass"
Mathieu Chartier [Wed, 28 May 2014 19:38:53 +0000 (19:38 +0000)]
Merge "Don't create bump pointer spaces unless necessary."
Bill Buzbee [Wed, 28 May 2014 19:32:41 +0000 (19:32 +0000)]
Merge "x86_64: Support r8-r15, xmm8-xmm15 in assembler"
Mathieu Chartier [Tue, 27 May 2014 17:10:11 +0000 (10:10 -0700)]
Don't create bump pointer spaces unless necessary.
We now only create these spaces if the foreground or background
collector is a moving collector.
Bug:
13564922
Bug:
14059466
Change-Id: I9f83c7881bc28423b78d5249c8e8854add91b60c
Hiroshi Yamauchi [Wed, 28 May 2014 19:20:28 +0000 (19:20 +0000)]
Merge "Add read barriers to the weak roots in the intern table."
Hiroshi Yamauchi [Sat, 24 May 2014 02:58:15 +0000 (19:58 -0700)]
Add read barriers to the weak roots in the intern table.
Bug:
12687968
Change-Id: I424f1df76a7e3d7154fb9f3c951c973d19bd640f
Hiroshi Yamauchi [Wed, 28 May 2014 18:04:31 +0000 (18:04 +0000)]
Merge "Allocate large enough space bitmaps for malloc spaces."
Brian Carlstrom [Wed, 28 May 2014 17:34:38 +0000 (17:34 +0000)]
Merge "Add option to specify compiler executable."
Bill Buzbee [Wed, 28 May 2014 17:33:50 +0000 (17:33 +0000)]
Merge "x86_64: Add 64-bit version of instructions in asm"
Dmitry Petrochenko [Wed, 30 Apr 2014 06:40:19 +0000 (13:40 +0700)]
x86_64: Support r8-r15, xmm8-xmm15 in assembler
Added REX support. The TARGET_REX_SUPPORT should be used during build.
Change-Id: I82b457ff5085c8192ad873923bd939fbb91022ce
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Jeff Hao [Wed, 28 May 2014 15:42:18 +0000 (15:42 +0000)]
Merge "Fix method tracing's handling of shadow frames on startup."
Tsu Chiang Chuang [Thu, 22 May 2014 17:22:25 +0000 (10:22 -0700)]
Add option to specify compiler executable.
Change-Id: I973da5e74be5a62461caacbc708288fb95e1b99b
Jeff Hao [Wed, 28 May 2014 01:25:47 +0000 (18:25 -0700)]
Fix method tracing's handling of shadow frames on startup.
Bug:
15142926
Change-Id: I7d7896ec3f62f46a43578f536292db6e219d83f0
Ian Rogers [Tue, 27 May 2014 23:00:36 +0000 (23:00 +0000)]
Merge "Fix the problem of not shutting down the profiler in ART properly"
Bill Buzbee [Tue, 27 May 2014 21:49:36 +0000 (21:49 +0000)]
Merge "Set the type of a RegStorage correctly"
Andreas Gampe [Tue, 27 May 2014 21:47:10 +0000 (21:47 +0000)]
Merge "ART: Fix sharpening across dex files"
buzbee [Tue, 27 May 2014 21:43:47 +0000 (21:43 +0000)]
Merge "Art compiler: remove unnecessary sqrt call"
Andreas Gampe [Tue, 27 May 2014 21:43:03 +0000 (14:43 -0700)]
ART: Fix sharpening across dex files
Bug:
15196336
Change-Id: If4301bcddce0ddbc60bb33403e4a76eed35bcb2f
buzbee [Tue, 27 May 2014 20:59:04 +0000 (13:59 -0700)]
Art compiler: remove unnecessary sqrt call
For reasons lost in the mists of time, the Dalvik JIT tested
the results of an inlined sqrt for NaN on Arm targets, and then
called an out-of-line routine to recompute if true. The Quick
compiler inherited this behavior. It is not necessary, and the CL
purges it (along with the out-of-line sqrt entrypoint).
Change-Id: I8c8fa6feacf9b7c3b9e190dfc6f728932fd948c6
buzbee [Tue, 27 May 2014 20:18:06 +0000 (20:18 +0000)]
Merge "Quick compiler: generalize NarrowRegLoc()"
Mark Mendell [Tue, 27 May 2014 19:52:21 +0000 (15:52 -0400)]
Set the type of a RegStorage correctly
This will be used as a FP value, so call the right function to create
the RegStorage.
Change-Id: I2bd832746afac509d20f195a7770f2fbd215cbd7
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Dmitry Petrochenko [Mon, 19 May 2014 21:03:46 +0000 (04:03 +0700)]
x86_64: Add 64-bit version of instructions in asm
Add missed 64-bit versions of instructions.
Change-Id: I8151484d909dff487cb7e521494a0be249a42214
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Jean Christophe Beyler [Tue, 29 Apr 2014 20:42:08 +0000 (13:42 -0700)]
ART: Print and dump functionalities per pass
LOG is a great logging tool but sometimes a pass has some debugging text it
want to be able to turn on/off easily.
By going via a print_pass flag, we can actually turn it on/off easily per pass
when debugging/instrumenting.
- Added a pass printer to help debug messages for future passes.
- Added a print_pass flag in CompilationUnit to filter out messages.
At the same time, did a similar system for dumping the CFG.
- Also moved some API into public from protected.
Change-Id: Ie0e89a8fc773e8583f3e4ffd6e4bd2eebdbb2bf4
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
Brian Carlstrom [Tue, 27 May 2014 18:39:03 +0000 (18:39 +0000)]
Merge "Workaround apparent clang compilation issue"
Brian Carlstrom [Tue, 27 May 2014 18:14:12 +0000 (11:14 -0700)]
Workaround apparent clang compilation issue
Bug:
15014252
(cherry picked from commit
ec80e7e1506e7099210399626b46cb8183534e70)
Change-Id: I159d66764749e41d2a97e0912f796085b4fdb6e1
Bill Buzbee [Tue, 27 May 2014 18:08:40 +0000 (18:08 +0000)]
Merge "AArch64: Add suspend check in managed code."
Bill Buzbee [Tue, 27 May 2014 18:08:25 +0000 (18:08 +0000)]
Merge "ART: Better SSA Allocation when recreating SSA"
Bill Buzbee [Tue, 27 May 2014 18:08:11 +0000 (18:08 +0000)]
Merge "AArch64: Enable FLOAT and DOUBLE opcodes"
Wei Jin [Wed, 21 May 2014 23:07:40 +0000 (16:07 -0700)]
Fix the problem of not shutting down the profiler in ART properly
This CL fixes the problem of not saving the last batch of profile data to the
external file when the runtime exits before the end of the current iteration of
profile sampling. This problem was fixed by shutting down the ART profiler
when the runtime exits and allowing the profiler to write the last batch of
data even it was signaled to shut down. This CL increases the precision of
profile data and fixes the bug that no data is saved if the duration of profile
sampling specified by VM arguments (by default 20 seconds) is longer than the
length of a single execution because the profiler was never signaled when the
runtime exits.
Change-Id: I7cc4805b7e2a22a990d04a5b9724ad1d931d7152
Signed-off-by: Wei Jin <wejin@google.com>
Jean Christophe Beyler [Thu, 1 May 2014 22:36:22 +0000 (15:36 -0700)]
ART: Better SSA Allocation when recreating SSA
The SSA calculation is not allocation friendly. This makes the
SSARepresentation remember how much is allocated and not reallocate
if SSA should be recalculated.
Also added some allocation friendly code for the dominance code.
Change-Id: Icd5586b7e2fefae8e1535975ab400b1ca95b500f
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Serban Constantinescu [Fri, 23 May 2014 16:38:18 +0000 (17:38 +0100)]
AArch64: Enable FLOAT and DOUBLE opcodes
This patch enables all the DOUBLE and FLOAT opcodes except for REM ones.
It has been tested and passes all Dalvik tests except for:
failed: 018-stack-overflow[pid=1076]
failed: 107-int-math2[pid=1593]
Change-Id: I581f219bde354e3402aa3ad6e24ef15566da5f78
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Brian Carlstrom [Mon, 26 May 2014 16:57:58 +0000 (16:57 +0000)]
Merge "Fix x86_64 test failures."
Nicolas Geoffray [Mon, 26 May 2014 13:01:46 +0000 (14:01 +0100)]
Fix x86_64 test failures.
Change-Id: I97b3d1755d2e205ca7423248a2af37f1875d5116
Nicolas Geoffray [Mon, 26 May 2014 10:53:44 +0000 (10:53 +0000)]
Merge "Add a linear scan register allocator to the optimizing compiler."
Nicolas Geoffray [Thu, 22 May 2014 11:50:17 +0000 (12:50 +0100)]
Add a linear scan register allocator to the optimizing compiler.
This is a "by-the-book" implementation. It currently only deals
with allocating registers, with no hint optimizations.
The changes remaining to make it functional are:
- Allocate spill slots.
- Resolution and placements of Move instructions.
- Connect it to the code generator.
Change-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4
Brian Carlstrom [Mon, 26 May 2014 05:44:55 +0000 (05:44 +0000)]
Merge "Make DexFile content read only before running DexFileVerifier"
Brian Carlstrom [Sun, 25 May 2014 23:08:51 +0000 (16:08 -0700)]
Make DexFile content read only before running DexFileVerifier
(cherry picked from commit
98725444129efe2b1b51c87740860caadaef2bf7)
Change-Id: I18a932b2f19d44b820232f4d4e9c358df20ab364
Zheng Xu [Fri, 23 May 2014 03:52:42 +0000 (11:52 +0800)]
AArch64: Add suspend check in managed code.
TODO: Remove x19 in the frame in runtime, generic jni, compiled jni.
Change-Id: Ibdc292c9e7adb3a5d3eff353c22f60ffc101f549
Brian Carlstrom [Sun, 25 May 2014 23:30:49 +0000 (23:30 +0000)]
Merge "Add TARGET_2ND_ARCH support for dump-oat-boot"
buzbee [Sun, 25 May 2014 22:10:52 +0000 (15:10 -0700)]
Quick compiler: generalize NarrowRegLoc()
Some of the RegStorage utilites (DoubleToLowSingle(),
DoubleToHighSingle(), etc.) worked only for targets which
which treat double precision registers as a pair of aliased
single precision registers.
This CL elminates those utilities, and replaces them with
a new RegisterInfo utility that will search an aliased register
set and return the member matching the required storage
configuration (if it exists).
Change-Id: Iff5de10f467d20a56e1a89df9fbf30d1cf63c240
Brian Carlstrom [Sun, 25 May 2014 21:38:17 +0000 (14:38 -0700)]
Add TARGET_2ND_ARCH support for dump-oat-boot
Change-Id: I87f1742f401af37893d336074c53dee92993b769
Brian Carlstrom [Sun, 25 May 2014 21:14:29 +0000 (21:14 +0000)]
Merge "Fix ExtractToMemMap to show original zip file name in ashmem"
Bill Buzbee [Sat, 24 May 2014 16:01:22 +0000 (16:01 +0000)]
Merge "x86_64: Rebase on top of "64-bit temp register support""
Bill Buzbee [Sat, 24 May 2014 15:35:09 +0000 (15:35 +0000)]
Merge "Implement all vector instructions for X86"
Mark Mendell [Thu, 22 May 2014 13:52:36 +0000 (09:52 -0400)]
Implement all vector instructions for X86
Add X86 code generation for the vector operations. Added support for
X86 disassembler for the new instructions.
Change-Id: I72b48f5efa3a516a16bb1dd4bdb5c9270a8db53a
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
buzbee [Sat, 24 May 2014 13:15:42 +0000 (13:15 +0000)]
Merge "Quick compiler: fix register clobbering."
buzbee [Fri, 23 May 2014 23:04:08 +0000 (16:04 -0700)]
Quick compiler: fix register clobbering.
Ensure all aliased children of a register set are clobbered
when any member is clobbered. Additionally, use a clobbering
mask to avoid clobbering non-overlapping siblings.
Change-Id: Ic0d88a30f3e5b7a359396f6541d602739fa3124a
Hiroshi Yamauchi [Sat, 24 May 2014 04:27:30 +0000 (21:27 -0700)]
Allocate large enough space bitmaps for malloc spaces.
Fix a bug that we don't allocate space bitmaps for a malloc space that
are large enough to cover the non-growth-limited capacity.
Change-Id: I2e99a70eb8cddc284dffafa2d2afcc2f0c9074c7
Dmitry Petrochenko [Thu, 22 May 2014 05:26:50 +0000 (12:26 +0700)]
x86_64: Rebase on top of "64-bit temp register support"
Added the 64-bit core/temp register definition, fixed RegisterPool
creation for x86_64 so that 64-bit core/temps are NOT used for now.
The long arithmetic still operates with register pair on x86_64 and
it is a subject for change in a separate patch.
Change-Id: I2be06d5aefaf80141983bc9d8ed8a2ee24c2b21b
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Mathieu Chartier [Sat, 24 May 2014 00:07:47 +0000 (00:07 +0000)]
Merge "Improve invalid large object free dumping."
Mathieu Chartier [Fri, 23 May 2014 23:42:20 +0000 (16:42 -0700)]
Improve invalid large object free dumping.
Bug:
14974497
Change-Id: I30f99d693151ee5ae1f7b3d420519a0b1b21b2f4
Mathieu Chartier [Fri, 23 May 2014 23:30:35 +0000 (23:30 +0000)]
Merge "Add reserve area to allocation stacks."
Bill Buzbee [Fri, 23 May 2014 23:02:20 +0000 (23:02 +0000)]
Merge "Revert "ART: Better SSA Allocation when recreating SSA""
Bill Buzbee [Fri, 23 May 2014 23:00:22 +0000 (23:00 +0000)]
Revert "ART: Better SSA Allocation when recreating SSA"
Temporarily reverting until memory footprint cost of adding a vreg to ssa entrance map on every applicable MIR node can be assessed..
This reverts commit
cb73fb35e5f7c575ed491c0c8e2d2b1a0a22ea2e.
Change-Id: Ia9c03bfc5d365ad8d8b949e870f1e3bcda7f9a54
Ian Rogers [Fri, 23 May 2014 22:45:34 +0000 (22:45 +0000)]
Merge "ART: Better SSA Allocation when recreating SSA"
Ian Rogers [Fri, 23 May 2014 22:38:35 +0000 (22:38 +0000)]
Merge "ART: BasicBlock API Implementation"
Jean Christophe Beyler [Mon, 12 May 2014 06:36:41 +0000 (23:36 -0700)]
ART: BasicBlock API Implementation
- Adding BasicBlock Utility functions.
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
Change-Id: Ia264b4e68a9a56441ca143f1d98e5a333cf87b29
Ian Rogers [Fri, 23 May 2014 21:47:48 +0000 (21:47 +0000)]
Merge "[MIPS] Remove warnings about use of at register"
Mathieu Chartier [Fri, 23 May 2014 21:10:42 +0000 (21:10 +0000)]
Merge "Revert "Revert "Fix an outstanding compaction bug in interpreter."""
Brian Carlstrom [Fri, 23 May 2014 09:47:28 +0000 (02:47 -0700)]
Fix ExtractToMemMap to show original zip file name in ashmem
(cherry picked from commit
1fca8e91f32dc8b13d3129b7ef4a0194839736e6)
Change-Id: Id7d22600496b090ac32150c8c6424da89964b6be
Mathieu Chartier [Thu, 22 May 2014 23:48:55 +0000 (16:48 -0700)]
Revert "Revert "Fix an outstanding compaction bug in interpreter.""
Fixed the generic trampoline to not use ToJObject when unnecessary.
Bug:
15167269
This reverts commit
3bdb873122964da7937eb070cbcf2ef638a8e459.
Change-Id: I0525d0e0f3afb753c770e1572070a0fa22b02271
Chris Dearman [Fri, 23 May 2014 17:47:01 +0000 (10:47 -0700)]
[MIPS] Remove warnings about use of at register
Also, don't restore k0 and k1 as part of long jump as they are reserved for
kernel usage.
Change-Id: I4eec9eb5d21de96ca79f2cef9407a0e19c9c2178
Ian Rogers [Fri, 23 May 2014 19:06:24 +0000 (19:06 +0000)]
Merge "ART: refactor x86/x86-64 entrypoints"
Ian Rogers [Fri, 23 May 2014 18:51:20 +0000 (18:51 +0000)]
Merge "Extra debug output for a failing lock check."
Ian Rogers [Fri, 23 May 2014 18:39:11 +0000 (11:39 -0700)]
Extra debug output for a failing lock check.
Change-Id: If4abae535a875a06f4fa4203e6aabc1169b1f38e
Ian Rogers [Fri, 23 May 2014 18:18:07 +0000 (18:18 +0000)]
Merge "ART: API to dex instructions"
Mathieu Chartier [Fri, 23 May 2014 17:54:50 +0000 (10:54 -0700)]
Add reserve area to allocation stacks.
This fixes an issue with heap verification which was caused when
the allocation stack overflowed. This resulted in heap verification
failures since we were storing the newly allocated object in a
handle scope without having it be live either in the live bitmap
or allocation stack. We now push the object in the reserve area
before we do a GC due to allocation stack overflow.
Change-Id: I83b42c4b3250d7eaab1b49e53066e21c8656a740
Ian Rogers [Fri, 23 May 2014 18:14:40 +0000 (18:14 +0000)]
Merge "Make the specification of when we need precise constants more precise."
Ian Rogers [Fri, 23 May 2014 18:03:11 +0000 (18:03 +0000)]
Merge "ART: Added print indices back to BitVector Dumper"
Ian Rogers [Fri, 23 May 2014 17:54:28 +0000 (17:54 +0000)]
Merge "x86_64: Fix 079-Phantom hang with QCG enabled"
Vladimir Marko [Fri, 23 May 2014 17:45:19 +0000 (17:45 +0000)]
Merge "Fix style issue."
Vladimir Marko [Fri, 23 May 2014 17:43:51 +0000 (18:43 +0100)]
Fix style issue.
Change-Id: I2044e01c68265c33e7fa6057efa7b6c7ac41ada4
Ian Rogers [Fri, 23 May 2014 17:43:43 +0000 (10:43 -0700)]
Make the specification of when we need precise constants more precise.
Means that oatdump output showing values for deoptimization actually reflects
what we see at runtime.
Also, doesn't do precise in the case of determining methods and fields for the
quickened case, which may be an occasional performance win.
Change-Id: I62c7fb244f7996ba9d52e7a7ce75c046b663fa17
Vladimir Marko [Fri, 23 May 2014 17:22:59 +0000 (17:22 +0000)]
Merge "Rewrite BitVector index iterator."
Jean Christophe Beyler [Thu, 22 May 2014 22:43:50 +0000 (15:43 -0700)]
ART: Added print indices back to BitVector Dumper
- Added an API to get the indices set instead of 001...0 format
Change-Id: I75841e41ca9b7ef77a0717715669dbe12506d6a1
Signed-Off-By: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Vladimir Marko [Fri, 23 May 2014 14:16:44 +0000 (15:16 +0100)]
Rewrite BitVector index iterator.
The BitVector::Iterator was not iterating over the bits but
rather over indexes of the set bits. Therefore, we rename it
to IndexIterator and provide a BitVector::Indexes() to get
a container-style interface with begin() and end() for range
based for loops.
Also, simplify InsertPhiNodes where the tmp_blocks isn't
needed since the phi_nodes and input_blocks cannot lose any
blocks in subsequent iterations, so we can do the Union()
directly in those bit vectors and we need to repeat the loop
only if we have new input_blocks, rather than on phi_nodes
change. And move the temporary bit vectors to scoped arena.
Change-Id: I6cb87a2f60724eeef67c6aaa34b36ed5acde6d43
Vladimir Marko [Fri, 23 May 2014 15:44:19 +0000 (15:44 +0000)]
Merge "Remove obsolete pass_driver.cc ."
Vladimir Marko [Fri, 23 May 2014 15:39:12 +0000 (16:39 +0100)]
Remove obsolete pass_driver.cc .
Obsoleted by https://android-review.googlesource.com/93433 .
Change-Id: I01865d17160fdc698f43c61fa4f5642d0f1391d9
Bill Buzbee [Fri, 23 May 2014 12:20:13 +0000 (12:20 +0000)]
Merge "x86_64: Disable optimizations on x86_64"
Bill Buzbee [Fri, 23 May 2014 12:19:59 +0000 (12:19 +0000)]
Merge "x86_64: Disable all intrinsics"
Alexei Zavjalov [Fri, 23 May 2014 10:51:59 +0000 (17:51 +0700)]
ART: refactor x86/x86-64 entrypoints
This patch:
- removes unused stubs in x86/64 runtimes (art_quick_l2d, art_quick_l2f
and art_quick_idivmod)
- replaces art_quick_fmod, art_quick_fmodf and art_quick_is_assignable
entrypoints in x86-64 to the direct calls
- removes art_quick_indexof stub in x86-64
Change-Id: I6141c5c73b0b449fa3b866068b101e0be211b93e
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
Vladimir Marko [Fri, 23 May 2014 10:50:39 +0000 (10:50 +0000)]
Merge "Fix InternTable::Lookup()/Remove() for hash code collisions."
Nicolas Geoffray [Fri, 23 May 2014 09:41:38 +0000 (09:41 +0000)]
Merge "Add virtual destructor to please one of our compilers."
Nicolas Geoffray [Fri, 23 May 2014 09:40:42 +0000 (10:40 +0100)]
Add virtual destructor to please one of our compilers.
Change-Id: I931d130caa75ab90b677e14f1a2d0c438c43ed4f
Calin Juravle [Fri, 23 May 2014 09:38:09 +0000 (09:38 +0000)]
Merge "Fix profile-backoff usage message"
Dmitry Petrochenko [Fri, 16 May 2014 06:24:40 +0000 (13:24 +0700)]
x86_64: Fix 079-Phantom hang with QCG enabled
The 079 test creates "sWatcher" thread. In case of unexpected failure
(e.g. Exception thrown) the sWatcher thread remains alive and it
blocks VM shutdown. We mark the sWarcher thread as daemon and
let VM to stop that thread during shutdown cause by unexpected error.
Change-Id: I0cb0b8bbeb15de47b72ddae1a32fcfea3ef8720e
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Dmitry Petrochenko [Thu, 8 May 2014 05:20:24 +0000 (12:20 +0700)]
x86_64: Disable all intrinsics
Intrinsics are subject to rework for x86_64 and disabled for now.
Change-Id: Ice67db083fe43dc4faa9276faf02234a4a24f207
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Dmitry Petrochenko [Fri, 16 May 2014 11:36:39 +0000 (18:36 +0700)]
x86_64: Disable optimizations on x86_64
This patch disables all QCG optimizations as ARM64 does.
Optimizations are subject to step-by-step enabling according
to test results.
Change-Id: Idd6e10f3b67e8c0f1f029bb26a0e9bf40061aeac
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Nicolas Geoffray [Fri, 23 May 2014 09:15:16 +0000 (09:15 +0000)]
Merge "Forgot these files from last commit."
Nicolas Geoffray [Fri, 23 May 2014 09:14:19 +0000 (10:14 +0100)]
Forgot these files from last commit.
Change-Id: I9ab7975daa5ed7aae6bff8730bb63fb48a798ea8
Nicolas Geoffray [Fri, 23 May 2014 09:03:36 +0000 (09:03 +0000)]
Merge "Import Dart's parallel move resolver."
Nicolas Geoffray [Thu, 22 May 2014 17:32:45 +0000 (18:32 +0100)]
Import Dart's parallel move resolver.
And write a few tests while at it.
A parallel move resolver will be needed for performing multiple moves
that are conceptually parallel, for example moves at a block
exit that branches to a block with phi nodes.
Change-Id: Ib95b247b4fc3f2c2fcab3b8c8d032abbd6104cd7
Sebastien Hertz [Fri, 23 May 2014 08:36:20 +0000 (08:36 +0000)]
Merge "Add a check for null thread before trying to suspend"
Bill Buzbee [Fri, 23 May 2014 05:27:41 +0000 (05:27 +0000)]
Merge "x86: For integer ALU operation handle v+=v case"
Serguei Katkov [Mon, 19 May 2014 08:45:42 +0000 (15:45 +0700)]
x86: For integer ALU operation handle v+=v case
When destination and operand are the same Virtual Register
we should ensure that destination RegLocation is updated after
operand is loaded with LoadValue in physical register.
Change-Id: I59da106471b0c494203af01c99583f51dbc0f9ee
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Bill Buzbee [Fri, 23 May 2014 02:56:02 +0000 (02:56 +0000)]
Merge "Create two CompilerTemp for a wide compiler temp"
Chao-ying Fu [Fri, 23 May 2014 00:25:02 +0000 (17:25 -0700)]
Create two CompilerTemp for a wide compiler temp
We create a new CompilerTemp for the high part of
a wide compiler temp to fix counting compiler temps.
Otherwise, assertion failures may happen inside
GetNumUsedCompilerTemps(), if there are any wide compiler temps.
Previously, we never ask for a wide compiler temp, such that
we don't hit the issue.
Change-Id: I9e79ad15e4192665b9d8a9dae5a5453496e48a79
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Brian Carlstrom [Thu, 22 May 2014 22:51:11 +0000 (22:51 +0000)]
Merge "Update dump-oat-* and oatdump for new image file layout"
Bill Buzbee [Thu, 22 May 2014 22:37:49 +0000 (22:37 +0000)]
Merge "AArch64: Enable LONG_* and INT_* opcodes."
Mathieu Chartier [Thu, 22 May 2014 22:07:37 +0000 (22:07 +0000)]
Merge "Revert "Fix an outstanding compaction bug in interpreter.""