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Simon Pilgrim [Mon, 30 Oct 2017 19:31:08 +0000 (19:31 +0000)]
[SelectionDAG] Add VSELECT demanded elts support to computeKnownBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316947
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Zvi Rackover [Mon, 30 Oct 2017 19:29:15 +0000 (19:29 +0000)]
X86 Tests: Update the variable-index permute tests with FP types. NFC.
These cases will be addressed in a future update to D39126.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316946
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Simon Pilgrim [Mon, 30 Oct 2017 19:19:58 +0000 (19:19 +0000)]
[X86][SSE] Add another computeKnownBits test showing missing VSELECT demandedelts support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316945
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Simon Pilgrim [Mon, 30 Oct 2017 19:08:21 +0000 (19:08 +0000)]
[SelectionDAG] Add VSELECT support to computeKnownBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316944
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Simon Pilgrim [Mon, 30 Oct 2017 18:48:31 +0000 (18:48 +0000)]
[X86][SSE] computeKnownBits tests showing missing VSELECT demandedelts support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316940
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Simon Pilgrim [Mon, 30 Oct 2017 18:37:27 +0000 (18:37 +0000)]
[X86][AVX512] Cleanup scheduler tests - split GENERIC and SKX targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316938
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Simon Pilgrim [Mon, 30 Oct 2017 17:53:51 +0000 (17:53 +0000)]
[SelectionDAG] Add SELECT demanded elts support to ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316933
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Simon Pilgrim [Mon, 30 Oct 2017 17:46:50 +0000 (17:46 +0000)]
[X86][SSE] ComputeNumSignBits tests showing missing VSELECT demandedelts support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316932
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Simon Pilgrim [Mon, 30 Oct 2017 17:24:40 +0000 (17:24 +0000)]
[MC] Split out register def/use idx calls to make debugging simpler. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316927
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Simon Pilgrim [Mon, 30 Oct 2017 17:23:17 +0000 (17:23 +0000)]
[X86][AVX] Add missing vcvtpd2dq/vcvtps2dq scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316926
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Simon Pilgrim [Mon, 30 Oct 2017 17:20:50 +0000 (17:20 +0000)]
[X86][SSE] Add clflush scheduling test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316925
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Jina Nahias [Mon, 30 Oct 2017 16:37:28 +0000 (16:37 +0000)]
[X86][AVX512] Adding a pattern for broadcastm intrinsic.
Differential Revision: https://reviews.llvm.org/D38312
Change-Id: I71c8605a8e4c98013ef25289694afc5cfd46bb0b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316921
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Rafael Espindola [Mon, 30 Oct 2017 16:32:31 +0000 (16:32 +0000)]
Move isDSOLocal check and add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316920
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Fangrui Song [Mon, 30 Oct 2017 16:03:44 +0000 (16:03 +0000)]
[PPC CodeGen] Fix the bitreverse.i64 intrinsic.
Summary: The two 32-bit words were swapped. Update a test omitted in reverted r316270.
Reviewers: jtony, aaron.ballman
Subscribers: nemanjai, kbarton
Differential Revision: https://reviews.llvm.org/D39163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316916
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Craig Topper [Mon, 30 Oct 2017 14:51:37 +0000 (14:51 +0000)]
[X86] Make sure we don't create locked inc/dec instructions when the carry flag is being used.
Summary:
INC/DEC don't update the carry flag so we need to make sure we don't try to use it.
This patch introduces new X86ISD opcodes for locked INC/DEC. Teaches lowerAtomicArithWithLOCK to emit these nodes if INC/DEC is not slow or the function is being optimized for size. An additional flag is added that allows the INC/DEC to be disabled if the caller determines that the carry flag is being requested.
The test_sub_1_cmp_1_setcc_ugt test is currently showing this bug. The other test case changes are recovering cases that were regressed in r316860.
This should fully fix PR35068 finishing the fix started in r316860.
Reviewers: RKSimon, zvi, spatel
Reviewed By: zvi
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316913
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Craig Topper [Mon, 30 Oct 2017 14:50:11 +0000 (14:50 +0000)]
[X86] Remove AVX512 early out from X86FastISel::X86SelectCmp.
This shouldn't be needed anymore since i1 isn't a legal type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316912
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Craig Topper [Mon, 30 Oct 2017 14:50:10 +0000 (14:50 +0000)]
[X86] Regenerate test using update_llc_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316911
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Sanjay Patel [Mon, 30 Oct 2017 14:34:30 +0000 (14:34 +0000)]
[PassManager, SimplifyCFG] add test for PR34603 / D38566; NFC
Sinking common insts and converting to select early can inhibit better folds in other passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316908
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Yaxun Liu [Mon, 30 Oct 2017 14:30:28 +0000 (14:30 +0000)]
[AMDGPU] Emit metadata for hidden arguments for kernel enqueue
Identifies kernels which performs device side kernel enqueues and emit
metadata for the associated hidden kernel arguments. Such kernels are
marked with calls-enqueue-kernel function attribute by
AMDGPUOpenCLEnqueueKernelLowering pass and later on
hidden kernel arguments metadata HiddenDefaultQueue and
HiddenCompletionAction are emitted for them.
Differential Revision: https://reviews.llvm.org/D39255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316907
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Clement Courbet [Mon, 30 Oct 2017 14:19:33 +0000 (14:19 +0000)]
[CodeGen][ExpandMemcmp] Allow memcmp to expand to vector loads (2).
- Targets that want to support memcmp expansions now return the list of
supported load sizes.
- Expansion codegen does not assume that all power-of-two load sizes
smaller than the max load size are valid. For examples, this is not the
case for x86(32bit)+sse2.
Fixes PR34887.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316905
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Krzysztof Parzyszek [Mon, 30 Oct 2017 14:11:52 +0000 (14:11 +0000)]
[Hexagon] Allow the RDF optimizations to be run in .mir testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316904
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Javed Absar [Mon, 30 Oct 2017 13:51:56 +0000 (13:51 +0000)]
[GlobalISel|ARM] : Allow legalizing G_FSUB
Adding support for VSUB.
Reviewed by: @rovka
Differential Revision: https://reviews.llvm.org/D39261
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316902
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Andrew V. Tischenko [Mon, 30 Oct 2017 12:02:06 +0000 (12:02 +0000)]
Invalid used of 'w' suffix on push and pop using 64-bit register.
Differential Revision: https://reviews.llvm.org/D38626
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316898
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Diana Picus [Mon, 30 Oct 2017 11:58:09 +0000 (11:58 +0000)]
[ARM GlobalISel] Fixup r316572. NFC
Just missed a few spots...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316897
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Jina Nahias [Mon, 30 Oct 2017 10:35:53 +0000 (10:35 +0000)]
Revert "[X86][AVX512] Adding a pattern for broadcastm intrinsic."
This reverts commit r316890.
Change-Id: I683cceee9848ef309b452293086b1f26a941950d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316894
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Florian Hahn [Mon, 30 Oct 2017 10:07:42 +0000 (10:07 +0000)]
Recommit r315288: [SCCP] Propagate integer range info for parameters in IPSCCP.
This version of the patch includes a fix addressing a stage2 LTO buildbot
failure and addressed some additional nits.
Original commit message:
This updates the SCCP solver to use of the ValueElement lattice for
parameters, which provides integer range information. The range
information is used to remove unneeded icmp instructions.
For the following function, f() can be optimized to ret i32 2 with
this change
source_filename = "sccp.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: norecurse nounwind readnone uwtable
define i32 @main() local_unnamed_addr #0 {
entry:
%call = tail call fastcc i32 @f(i32 1)
%call1 = tail call fastcc i32 @f(i32 47)
%add3 = add nsw i32 %call, %call1
ret i32 %add3
}
; Function Attrs: noinline norecurse nounwind readnone uwtable
define internal fastcc i32 @f(i32 %x) unnamed_addr #1 {
entry:
%c1 = icmp sle i32 %x, 100
%cmp = icmp sgt i32 %x, 300
%. = select i1 %cmp, i32 1, i32 2
ret i32 %.
}
attributes #1 = { noinline }
Reviewers: davide, sanjoy, efriedma, dberlin
Reviewed By: davide, dberlin
Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits
Differential Revision: https://reviews.llvm.org/D36656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316891
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Jina Nahias [Mon, 30 Oct 2017 09:59:52 +0000 (09:59 +0000)]
[X86][AVX512] Adding a pattern for broadcastm intrinsic.
Differential Revision: https://reviews.llvm.org/D38312
Change-Id: I6551fb13879e098aed74de410e29815cf37d9ab5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316890
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Max Kazantsev [Mon, 30 Oct 2017 09:35:16 +0000 (09:35 +0000)]
[IRCE][NFC] Store Length as SCEV in RangeCheck instead of Value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316889
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Florian Hahn [Mon, 30 Oct 2017 09:21:50 +0000 (09:21 +0000)]
Revert r316887 to fix buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316888
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Florian Hahn [Mon, 30 Oct 2017 09:04:18 +0000 (09:04 +0000)]
Recommit r315288: [SCCP] Propagate integer range info for parameters in IPSCCP.
This version of the patch includes a fix addressing a stage2 LTO buildbot
failure and addressed some additional nits.
Original commit message:
This updates the SCCP solver to use of the ValueElement lattice for
parameters, which provides integer range information. The range
information is used to remove unneeded icmp instructions.
For the following function, f() can be optimized to ret i32 2 with
this change
source_filename = "sccp.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: norecurse nounwind readnone uwtable
define i32 @main() local_unnamed_addr #0 {
entry:
%call = tail call fastcc i32 @f(i32 1)
%call1 = tail call fastcc i32 @f(i32 47)
%add3 = add nsw i32 %call, %call1
ret i32 %add3
}
; Function Attrs: noinline norecurse nounwind readnone uwtable
define internal fastcc i32 @f(i32 %x) unnamed_addr #1 {
entry:
%c1 = icmp sle i32 %x, 100
%cmp = icmp sgt i32 %x, 300
%. = select i1 %cmp, i32 1, i32 2
ret i32 %.
}
attributes #1 = { noinline }
Reviewers: davide, sanjoy, efriedma, dberlin
Reviewed By: davide, dberlin
Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits
Differential Revision: https://reviews.llvm.org/D36656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316887
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Max Kazantsev [Mon, 30 Oct 2017 04:48:34 +0000 (04:48 +0000)]
[GVN][NFC] Mark instruction for deletion instead of immediate erasing in LoadPRE
It is done to uniformly handle instructions removal.
Differential Revision: https://reviews.llvm.org/D39369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316884
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Craig Topper [Mon, 30 Oct 2017 04:39:18 +0000 (04:39 +0000)]
[X86] Rearrange code in X86InstrInfo.cpp to put all the foldMemoryOperandImpl methods together without partial/undef register handling in the middle. NFC
I have a future patch that wants to make use of the one of the partial functions in one of the earlier memory folding methods and the current ordering prevents that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316883
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Craig Topper [Mon, 30 Oct 2017 03:35:44 +0000 (03:35 +0000)]
[X86] Simplify code by removing an unnecessary temporary variable. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316882
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Craig Topper [Mon, 30 Oct 2017 03:35:43 +0000 (03:35 +0000)]
[X86] Move some EVEX->VEX code to a helper function to prepare for a future patch. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316881
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Simon Pilgrim [Sun, 29 Oct 2017 22:03:37 +0000 (22:03 +0000)]
[SelectionDAG] Add SEXT/AND/XOR/Or demanded elts support to ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316875
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Simon Pilgrim [Sun, 29 Oct 2017 21:35:28 +0000 (21:35 +0000)]
[X86][SSE] Split ComputeNumSignBits SEXT/AND/XOR/OR demandedelts test
Max depth was being exceeded which could prevent some combines working
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316871
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Sanjay Patel [Sun, 29 Oct 2017 20:49:31 +0000 (20:49 +0000)]
[(new) Pass Manager] instantiate SimplifyCFG with the same options as the old PM
The old PM sets the options of what used to be known as "latesimplifycfg" on the
instantiation after the vectorizers have run, so that's what we'redoing here.
FWIW, there's a later SimplifyCFGPass instantiation in both PMs where we do not
set the "late" options. I'm not sure if that's intentional or not.
Differential Revision: https://reviews.llvm.org/D39407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316869
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Simon Pilgrim [Sun, 29 Oct 2017 20:49:27 +0000 (20:49 +0000)]
[X86][SSE] ComputeNumSignBits tests showing missing SEXT/AND/XOR/OR demandedelts support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316868
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Simon Pilgrim [Sun, 29 Oct 2017 18:19:37 +0000 (18:19 +0000)]
[SelectionDAG] Add SRA/SHL demanded elts support to ComputeNumSignBits
Introduce a isConstOrDemandedConstSplat helper function that can recognise a constant splat build vector for at least the demanded elts we care about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316866
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Simon Pilgrim [Sun, 29 Oct 2017 18:01:31 +0000 (18:01 +0000)]
[X86][SSE] ComputeNumSignBits tests showing missing SHL/SRA demandedelts support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316865
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Craig Topper [Sun, 29 Oct 2017 17:15:09 +0000 (17:15 +0000)]
[X86] Add a slow-incdec command line to atomic-eflags-reuse.ll
I believe the test_sub_1_cmp_1_setcc_ugt test case is being miscompiled in the fast inc/dec case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316864
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Craig Topper [Sun, 29 Oct 2017 06:51:04 +0000 (06:51 +0000)]
[X86] Remove combine that turns X86ISD::LSUB into X86ISD::LADD. Update patterns that depended on this.
If the carry flag is being used, this transformation isn't safe.
This does prevent some test cases from using DEC now, but I'll try to look into that separately.
Fixes PR35068.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316860
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Craig Topper [Sun, 29 Oct 2017 06:51:02 +0000 (06:51 +0000)]
[X86] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316859
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Craig Topper [Sun, 29 Oct 2017 05:14:26 +0000 (05:14 +0000)]
[X86] Use the extended vector register classes in fast isel with AVX512F/VL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316857
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Craig Topper [Sun, 29 Oct 2017 02:50:31 +0000 (02:50 +0000)]
[X86] Add AVX512 support to X86FastISel::X86SelectFPExt and X86FastISel::X86SelectFPTrunc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316856
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Craig Topper [Sun, 29 Oct 2017 02:25:48 +0000 (02:25 +0000)]
[X86] Use update_llc_test_checks.py to regenerate fast-isel-int-float-conversion.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316855
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Craig Topper [Sun, 29 Oct 2017 02:18:43 +0000 (02:18 +0000)]
[X86] Use update_llc_test_checks.py to regenerate fast-isel-fptrunc-fpext.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316854
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Craig Topper [Sun, 29 Oct 2017 02:18:41 +0000 (02:18 +0000)]
[X86] Add AVX512 support to X86FastISel::X86MaterializeFP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316853
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Craig Topper [Sat, 28 Oct 2017 23:10:13 +0000 (23:10 +0000)]
[X86] Remove invalid code from LowerVSELECT.
This code attempted to say that v8i16/v16i16 VSELECT is legal if BWI and VLX are enabled, but the only way we could reach this point is if the condition was not a vXi1 type. Which means it really wasn't legal.
We don't have any tests that exercise this code. So I'm hoping it wasn't really reachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316851
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Simon Pilgrim [Sat, 28 Oct 2017 22:10:40 +0000 (22:10 +0000)]
[SelectionDAG] Add support for INSERT_SUBVECTOR to computeKnownBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316847
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Simon Pilgrim [Sat, 28 Oct 2017 20:51:27 +0000 (20:51 +0000)]
[X86][SSE] Combine 128-bit target shuffles to PACKSS/PACKUS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316845
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Simon Pilgrim [Sat, 28 Oct 2017 20:27:22 +0000 (20:27 +0000)]
[X86][SSE] Split off matchVectorShuffleWithPACK. NFCI.
Split matchVectorShuffleWithPACK from lowerVectorShuffleWithPACK so that we can reuse it for target shuffle combines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316844
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Craig Topper [Sat, 28 Oct 2017 19:56:57 +0000 (19:56 +0000)]
[X86] Fix a mistake in the X86ISelDAGToDAG.cpp code for MUL8r/IMUL8r.
I think this code is unreachable due to some promotions that occur elsewhere. I'll look into that to be sure, but for now I thought I should at least fix the obvious typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316840
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Craig Topper [Sat, 28 Oct 2017 19:56:56 +0000 (19:56 +0000)]
[X86] Replace some default cases in X86SelectShift with llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316839
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Saleem Abdulrasool [Sat, 28 Oct 2017 19:15:05 +0000 (19:15 +0000)]
ADT: add a helper to check if the Triple is ARM64
Add a trivial helper for checking if the architecture is AArch64 Little
Endian or Big Endian.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316837
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Sanjay Patel [Sat, 28 Oct 2017 18:43:07 +0000 (18:43 +0000)]
[SimplifyCFG] use pass options and remove the latesimplifycfg pass
This is no-functional-change-intended.
This is repackaging the functionality of D30333 (defer switch-to-lookup-tables) and
D35411 (defer folding unconditional branches) with pass parameters rather than a named
"latesimplifycfg" pass. Now that we have individual options to control the functionality,
we could decouple when these fire (but that's an independent patch if desired).
The next planned step would be to add another option bit to disable the sinking transform
mentioned in D38566. This should also make it clear that the new pass manager needs to
be updated to limit simplifycfg in the same way as the old pass manager.
Differential Revision: https://reviews.llvm.org/D38631
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316835
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Simon Pilgrim [Sat, 28 Oct 2017 17:59:56 +0000 (17:59 +0000)]
[X86][SSE] Rename truncateVectorCompareWithPACKSS to truncateVectorWithPACKSS. NFC.
We no longer rely on the vector source being a comparison result, just have sufficient sign bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316834
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Craig Topper [Sat, 28 Oct 2017 17:37:51 +0000 (17:37 +0000)]
[X86] Correct the alignments on the aligned test cases in fast-isel-vecload.ll to make sure they test selection of aligned loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316833
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Simon Pilgrim [Sat, 28 Oct 2017 14:27:53 +0000 (14:27 +0000)]
[SelectionDAG] Support 'bit preserving' floating points bitcasts on computeKnownBits/ComputeNumSignBits
For cases where we know the floating point representations match the bitcasted integer equivalent, allow bitcasting to these types.
This is especially useful for the X86 floating point compare results which return all/zero bits but as a floating point type.
Differential Revision: https://reviews.llvm.org/D39289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316831
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Craig Topper [Sat, 28 Oct 2017 06:31:48 +0000 (06:31 +0000)]
[X86] Add avx command lines to fast-isel-constpool.ll to improve coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316829
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Craig Topper [Sat, 28 Oct 2017 06:31:46 +0000 (06:31 +0000)]
[X86] Use update_llc_test_checks.py to regenerate fast-isel-constpool.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316828
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Craig Topper [Sat, 28 Oct 2017 06:10:03 +0000 (06:10 +0000)]
[X86] Add a fast-isel test for the i8 pseudo cmov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316827
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Craig Topper [Sat, 28 Oct 2017 05:52:23 +0000 (05:52 +0000)]
[X86] Remove unneeded MVT::i1 related code from fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316825
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Haicheng Wu [Sat, 28 Oct 2017 02:27:14 +0000 (02:27 +0000)]
[ConstantFold] Fix a crash when folding a GEP that has vector index
LLVM crashes when factoring out an out-of-bound index into preceding dimension
and the preceding dimension uses vector index. Simply bail out now when this
case happens.
Differential Revision: https://reviews.llvm.org/D38677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316824
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Craig Topper [Sat, 28 Oct 2017 02:03:59 +0000 (02:03 +0000)]
[X86] Add avx command lines to two fast-isel tests to get coverage of selecting vucomiss/vucomisd.
The selection of these shows up as a code coverage hole when looking at the llvm-cov link on llvm.org
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316823
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Craig Topper [Sat, 28 Oct 2017 02:03:58 +0000 (02:03 +0000)]
[X86] Use update_llc_test_checks.py to regenerate fast-isel-select-cmov2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316822
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Craig Topper [Sat, 28 Oct 2017 00:36:58 +0000 (00:36 +0000)]
[PartialInlineLibCalls] Teach PartialInlineLibCalls to honor nobuiltin, properly check the function signature, and check TLI::has
Summary:
We shouldn't do this transformation if the function is marked nobuitlin.
We were only checking that the return type is floating point, we really should be checking the argument types and argument count as well. This can be accomplished by using the other version of getLibFunc that takes the Function and not just the name.
We should also be checking TLI::has since sqrtf is a macro on Windows.
Fixes PR32559.
Reviewers: hfinkel, spatel, davide, efriedma
Reviewed By: davide, efriedma
Subscribers: efriedma, llvm-commits, eraman
Differential Revision: https://reviews.llvm.org/D39381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316819
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Eugene Zelenko [Sat, 28 Oct 2017 00:24:26 +0000 (00:24 +0000)]
[ADT] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316818
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Tom Stellard [Fri, 27 Oct 2017 23:57:41 +0000 (23:57 +0000)]
AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D38439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316815
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Bob Haarman [Fri, 27 Oct 2017 23:41:17 +0000 (23:41 +0000)]
[support] remove tautological comparison in Support/Windows/Path.inc
Summary:
The removed code checks that we are able to handle a 64-bit number, but
the code we're calling takes two dwords (for a total of 64 bits), so this
is always true.
Reviewers: zturner, rnk, majnemer, compnerd
Reviewed By: zturner
Subscribers: amccarth, hiraditya, lebedev.ri, llvm-commits
Differential Revision: https://reviews.llvm.org/D39263
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316814
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Jake Ehrlich [Fri, 27 Oct 2017 23:39:31 +0000 (23:39 +0000)]
Revert "Add support for writing 64-bit symbol tables for archives when offsets become too large for 32-bit"
This reverts commit r316805.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316813
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Jake Ehrlich [Fri, 27 Oct 2017 22:26:37 +0000 (22:26 +0000)]
Add support for writing 64-bit symbol tables for archives when offsets become too large for 32-bit
This should fix https://bugs.llvm.org//show_bug.cgi?id=34189
This change makes it so that if writing a K_GNU style archive, you need
to output a > 32-bit offset it should output in K_GNU64 style instead.
Differential Revision: https://reviews.llvm.org/D36812
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316805
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Krzysztof Parzyszek [Fri, 27 Oct 2017 22:24:49 +0000 (22:24 +0000)]
[Hexagon] Adjust patterns to reflect instruction selection preferences
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316804
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David Blaikie [Fri, 27 Oct 2017 22:12:46 +0000 (22:12 +0000)]
Add a few missing headers for modularization/IWYU/etc
Several cases where class definitions are required for DenseMap pointer
traits handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316803
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Guozhi Wei [Fri, 27 Oct 2017 21:54:24 +0000 (21:54 +0000)]
[DAGCombine] Don't combine sext with extload if sextload is not supported and extload has multi users
In function DAGCombiner::visitSIGN_EXTEND_INREG, sext can be combined with extload even if sextload is not supported by target, then
if sext is the only user of extload, there is no big difference, no harm no benefit.
if extload has more than one user, the combined sextload may block extload from combining with other zext, causes extra zext instructions generated. As demonstrated by the attached test case.
This patch add the constraint that when sextload is not supported by target, sext can only be combined with extload if it is the only user of extload.
Differential Revision: https://reviews.llvm.org/D39108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316802
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Jake Ehrlich [Fri, 27 Oct 2017 21:47:38 +0000 (21:47 +0000)]
Make 32-bit member offset in Archive::Symbol::getMember 64-bit
When accessing a member for a symbol with an offset greater than 2^32 -
1 the current Archive::Symbol::getMember implementation will overflow
and cause unexpected behavior. This change simply fixes that. In
particular if you call "llvm-nm --print-armap" on an archive that has
this behavior you'll get an error.
Differential Revision: https://reviews.llvm.org/D39379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316801
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Rafael Espindola [Fri, 27 Oct 2017 21:18:48 +0000 (21:18 +0000)]
Handle undefined weak hidden symbols on all architectures.
We were handling the non-hidden case in lib/Target/TargetMachine.cpp,
but the hidden case was handled in architecture dependent code and
only X86_64 and AArch64 were covered.
While it is true that some code sequences in some ABIs might be able
to produce the correct value at runtime, that doesn't seem to be the
common case.
I left the AArch64 code in place since it also forces a got access for
non-pic code. It is not clear if that is needed, but it is probably
better to change that in another commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316799
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Zachary Turner [Fri, 27 Oct 2017 21:12:28 +0000 (21:12 +0000)]
Force #define GTEST_LANG_CXX11.
gtest depends on this #define to determine whether it can
use various classes like std::tuple, or whether it has to fall
back to experimental classes in the std::tr1 namespace. The
check in the current version of gtest relies on the value of
the `__cplusplus` macro, but MSVC provides a non-conformant
value of this macro, making it effectively impossible to detect
C++11. In short, LLVM compiled with MSVC has been silently
using the tr1 versions of several classes since the beginning of
time.
This would normally be pretty benign, except that in the latest
preview of MSVC they have marked all of the tr1 classes
deprecated, so it spews thousands of warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316798
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Craig Topper [Fri, 27 Oct 2017 21:00:59 +0000 (21:00 +0000)]
[X86] Remove fast-isel code for handling i8 shifts. This is handled by auto generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316797
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Craig Topper [Fri, 27 Oct 2017 21:00:56 +0000 (21:00 +0000)]
[X86] Add fast-isel tests for integer shifts. We definitely had no coverage of i16 and i32/i64 are only tested by larger tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316796
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Artur Gainullin [Fri, 27 Oct 2017 20:53:41 +0000 (20:53 +0000)]
Improve clamp recognition in ValueTracking.
Summary:
ValueTracking was recognizing not all variations of clamp. Swapping of
true value and false value of select was added to fix this problem. The
first patch was reverted because it caused miscompile in NVPTX target.
Added corresponding test cases.
Reviewers: spatel, majnemer, efriedma, reames
Subscribers: llvm-commits, jholewinski
Differential Revision: https://reviews.llvm.org/D39240
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316795
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Craig Topper [Fri, 27 Oct 2017 20:13:10 +0000 (20:13 +0000)]
[X86] Teach fastisel to use VLX VMOVNTDQA for v4f64 and 256-bit integers when available.
This looks to have been missed from r280682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316790
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Craig Topper [Fri, 27 Oct 2017 20:13:06 +0000 (20:13 +0000)]
[X86] Add avx512vl command line to fast-isel-nontemporal.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316789
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Vlad Tsyrklevich [Fri, 27 Oct 2017 19:15:13 +0000 (19:15 +0000)]
Fix llvm-special-case-list-fuzzer regexp exception
Summary:
Original oss-fuzz report:
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3727#c2
The minimized test case that causes this failure:
5b 5b 5b 3d 47 53 00 5b 3d 5d 5b 5d 0a [[[=GS.[=][].
Note the string "=GS\x00". The failure happens because the code is
searching the string against an array of known collated names. "GS\x00"
is a hit, but since len takes into account an extra NUL byte, indexing
into cp->name[len] goes one byte past it's allocated memory. Fix this to
use a strlen(cp->name) comparison to account for NUL bytes in the input.
Reviewers: pcc
Reviewed By: pcc
Subscribers: hctim, kcc
Differential Revision: https://reviews.llvm.org/D39380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316786
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Krzysztof Parzyszek [Fri, 27 Oct 2017 18:52:28 +0000 (18:52 +0000)]
[Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cpp
Making sure that an instruction has fewer operands than required, then
attempting to access one out of range is going to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316785
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Simon Pilgrim [Fri, 27 Oct 2017 18:14:12 +0000 (18:14 +0000)]
[X86][SSE] Add tests for inserting all-bits (-1) into a vector
We should be able to do this by re-materializing an all-bits vector and then blending with it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316779
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Peter Collingbourne [Fri, 27 Oct 2017 17:49:40 +0000 (17:49 +0000)]
ELF: Add support for emitting dynamic relocations in the Android relocation packing format.
The Android relocation packing format is a more compact
format for dynamic relocations in executables and DSOs
that is based on delta encoding and SLEBs. An overview
of the format can be found in the Android source code:
https://android.googlesource.com/platform/bionic/+/refs/heads/master/tools/relocation_packer/src/delta_encoder.h
This patch implements relocation packing using that format.
This implementation uses a more intelligent algorithm for compressing
relative relocations than Android's own relocation packer. As a
result it can generally create smaller relocation sections than
that packer. If I link Chromium for Android targeting ARM32 I get a
.rel.dyn of size 174693 bytes, as compared to 371832 bytes with gold
and the Android packer.
Differential Revision: https://reviews.llvm.org/D39152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316775
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Simon Pilgrim [Fri, 27 Oct 2017 16:34:58 +0000 (16:34 +0000)]
[X86][F16C] Fix btver2 AGU pipe scheduling
Use the store AGU for stores, and the load AGU needs to be the first pipe for loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316771
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Artur Pilipenko [Fri, 27 Oct 2017 14:46:17 +0000 (14:46 +0000)]
[LoopPredication] Handle the case when the guard and the latch IV have different offsets
This is a follow up change for D37569.
Currently the transformation is limited to the case when:
* The loop has a single latch with the condition of the form: ++i <pred> latchLimit, where <pred> is u<, u<=, s<, or s<=.
* The step of the IV used in the latch condition is 1.
* The IV of the latch condition is the same as the post increment IV of the guard condition.
* The guard condition is of the form i u< guardLimit.
This patch enables the transform in the case when the latch is
latchStart + i <pred> latchLimit, where <pred> is u<, u<=, s<, or s<=.
And the guard is
guardStart + i u< guardLimit
Reviewed By: anna
Differential Revision: https://reviews.llvm.org/D39097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316768
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Clement Courbet [Fri, 27 Oct 2017 13:34:41 +0000 (13:34 +0000)]
[CodeGen] Fix -Wunused-private-field warning on lld-x86_64-darwin13.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316765
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Clement Courbet [Fri, 27 Oct 2017 12:34:18 +0000 (12:34 +0000)]
[CodeGen][ExpandMemCmp][NFC] Simplify load sequence generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316763
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whitequark [Fri, 27 Oct 2017 11:51:40 +0000 (11:51 +0000)]
[LLVM-C] Publicly expose getters of MetadataType, TokenType
Patch by Robert Widmann.
Expose getters for MetadataType and TokenType publicly in the C API.
Discovered a need for these while trying to wrap the intrinsics API.
Differential Revision: https://reviews.llvm.org/D38809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316762
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George Rimar [Fri, 27 Oct 2017 10:58:04 +0000 (10:58 +0000)]
Fix BB after r316756 "[llvm-dwarfdump] - Teach verifier to report broken DWARF expressions."
Bot:
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/6255
Changed format of this message by mistake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316757
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George Rimar [Fri, 27 Oct 2017 10:42:04 +0000 (10:42 +0000)]
[llvm-dwarfdump] - Teach verifier to report broken DWARF expressions.
Patch improves next things:
* Fixes assert/crash in getOpDesc when giving it a invalid expression op code.
* DWARFExpression::print() called DWARFExpression::Operation::getEndOffset() which
returned and used uninitialized field EndOffset. Patch fixes that.
* Teaches verifier to verify DW_AT_location and error out on broken expressions.
Differential revision: https://reviews.llvm.org/D39294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316756
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Matt Arsenault [Fri, 27 Oct 2017 09:06:07 +0000 (09:06 +0000)]
DAG: Fold fma (fneg x), K, y -> fma x, -K, y
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316753
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Clement Courbet [Fri, 27 Oct 2017 08:33:51 +0000 (08:33 +0000)]
[CodeGen][ExpandMemcmp][NFC] Make tests more complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316749
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Max Kazantsev [Fri, 27 Oct 2017 08:19:35 +0000 (08:19 +0000)]
[GVN][NFC] Refactor loop iteration with foreach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316748
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NAKAMURA Takumi [Fri, 27 Oct 2017 05:45:11 +0000 (05:45 +0000)]
llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h: Fix -fmodules build introduced in rL316715.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316743
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Max Kazantsev [Fri, 27 Oct 2017 04:17:44 +0000 (04:17 +0000)]
Revert rL316568 because of sudden performance drop on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316739
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Sean Fertile [Fri, 27 Oct 2017 04:02:51 +0000 (04:02 +0000)]
Add subclass data to the FoldingSetNode for MemIntrinsicSDNodes.
Not having the subclass data on an MemIntrinsicSDNodes means it was possible
to try to fold 2 nodes with the same operands but differing MMO flags. This
would trip an assertion when trying to refine the alignment between the 2
MachineMemOperands.
Differential Revision: https://reviews.llvm.org/D38898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316737
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