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Tapani Pälli [Tue, 23 Jan 2018 12:01:00 +0000 (14:01 +0200)]
anv: implement VK_EXT_global_priority extension
v2: add ANV_CONTEXT_REALTIME_PRIORITY (Chris)
use unreachable with unknown priority (Samuel)
v3: add stubs in gem_stubs.c (Emil)
use priority defines from gen_defines.h
v4: cleanup, add anv_gem_set_context_param (Jason)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> (v2)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (v3)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tapani Pälli [Mon, 22 Jan 2018 06:22:53 +0000 (08:22 +0200)]
i965: use context priority definitions from gen_defines.h
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tapani Pälli [Mon, 22 Jan 2018 06:17:50 +0000 (08:17 +0200)]
intel: add new common header gen_defines.h
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Christian König [Mon, 26 Feb 2018 13:13:28 +0000 (14:13 +0100)]
winsys/amdgpu: request high addresses
We now have hopefully fixed all bugs regarding high addresses on Vega10 and
Raven. Start to use the high range to make room for SVM in the low
range.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Mon, 26 Feb 2018 11:14:35 +0000 (12:14 +0100)]
ac/shader: move scanning some info about input PS declarations
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Samuel Iglesias Gonsálvez [Mon, 29 Jan 2018 12:46:28 +0000 (13:46 +0100)]
glsl/linker: fix bug when checking precision qualifier
According to GLSL ES 3.2 spec, see table in 9.2.1 "Linked Shaders"
section, the precision qualifier should match for uniform variables.
This also applies to previous GLSL ES 3.x specs.
This 'if' checks the condition for uniform variables, while for UBOs
it is checked in link_interface_blocks.cpp.
Fixes:
b50b82b8a553
("glsl/es31: precision qualifier doesn't need to match in shader interface block members")
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Samuel Iglesias Gonsálvez [Mon, 26 Feb 2018 07:26:24 +0000 (08:26 +0100)]
anv: set maxResourceSize to the respective value for each generation
v2:
- Add the proper values to gen9+ (Jason)
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Wed, 28 Feb 2018 04:37:45 +0000 (04:37 +0000)]
r600: partly revert disabling tiling for 1d texture.
Previously we had a check for 1d of narrow 2D textures, however
narrow 2d textures caused gpu hangs, but it was correct for 1d
textures.
This fixes a bunch of 1D image piglits for me.
Fixes:
7b8e1c089d (r600/texture: drop lowering 1d/2d images to linear.)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Wed, 28 Feb 2018 03:33:55 +0000 (14:33 +1100)]
nir: fix interger divide by zero crash during constant folding
From the GLSL 4.60 spec Section 5.9 (Expressions):
"Dividing by zero does not cause an exception but does result in
an unspecified value."
Fixes:
89285e4d47a6 "nir: add new constant folding infrastructure"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105271
Ilia Mirkin [Tue, 27 Feb 2018 00:31:12 +0000 (19:31 -0500)]
st/mesa: ensure that images don't try to reference non-existent levels
Ideally the st_finalize_texture call would take care of that, but it
doesn't seem to with KHR-GL45.shader_image_size.advanced-nonMS-*. This
assertion makes sure that no such values are passed to the driver.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Tue, 27 Feb 2018 23:53:51 +0000 (09:53 +1000)]
ac/radv: move load base vertex abi setup to vertex shader.
This was segfaulting:
dEQP-VK.memory.pipeline_barrier.host_write_index_buffer.1024
Fixes:
8de6f797070 (ac/radeonsi: add load_base_vertex() to the abi)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 27 Feb 2018 02:34:54 +0000 (12:34 +1000)]
ac/shader: fix vertex input with components.
This fixes:
dEQP-VK.glsl.440.linkage.varying.component.*
Fixes:
1c57a6da5e3 (ac/shader: scan vertex inputs usage mask)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 27 Feb 2018 04:31:31 +0000 (14:31 +1000)]
radv: remove device pointer from buffer.
This is never used.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Tue, 27 Feb 2018 08:19:21 +0000 (19:19 +1100)]
nir: add lower_ldexp to nir compiler options
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 27 Feb 2018 08:37:59 +0000 (19:37 +1100)]
ac: implement nir_op_ldexp
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 27 Feb 2018 05:08:40 +0000 (16:08 +1100)]
ac: fix nir_op_fdd{x,y} handling
radeonsi, i965 and anv all treat fdd{x,y} opcodes the same as
fdd{x,y}_coarse by default. The SPIR-V spec lets the implementation
decide how it should be handled and radv was previously going
for the higher quality option. Here we change the shared amd
code to match how nir_op_fdd{x,y} is expected to be handled
by the other NIR drivers.
Fixes piglit test:
./bin/arb_shader_texture_lod-texgrad -auto
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 26 Feb 2018 11:11:53 +0000 (22:11 +1100)]
ac/radeonsi: add load_base_vertex() to the abi
Fixes the following piglit tests:
./bin/arb_shader_draw_parameters-basevertex basevertex -auto -fbo
./bin/arb_shader_draw_parameters-basevertex basevertex-baseinstance -auto -fbo
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 26 Feb 2018 10:59:43 +0000 (21:59 +1100)]
radeonsi: create get_base_vertex() helper
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 27 Feb 2018 01:48:11 +0000 (12:48 +1100)]
radeonsi/nir: disable vertex_id_zero_based lowering
The lowering is incompatible with how the radeonsi backend works.
Fixes piglit test:
./bin/arb_shader_draw_parameters-basevertex vertexid-zerobased -auto
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 27 Feb 2018 01:47:00 +0000 (12:47 +1100)]
ac: add support for handling nir_intrinsic_load_vertex_id
This will be used by radeonsi.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 26 Feb 2018 05:12:41 +0000 (16:12 +1100)]
ac: fix f2b and i2b for doubles
Without this llvm was asserting in debug builds.
V2: use LLVMConstNull()
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Francisco Jerez [Fri, 26 Jan 2018 19:48:02 +0000 (11:48 -0800)]
intel/ir: Fix invalid type aliasing with undefined behavior in test_eu_compact.
test_fuzz_compact_instruction() was attempting to modify the uint64_t
data array of a brw_inst through a pointer to uint32_t, which has
undefined behavior. This was causing the test_eu_compact unit test to
fail mysteriously for me on GCC 7 with some additional
harmless-looking changes I had applied to my tree, which happened to
affect the order instructions are emitted by GCC causing the bit
twiddling to be done after the clear_pad_bits() call which is supposed
to overwrite the same data through a pointer of different type,
leading to data corruption. A similar failure has been reported by
Vinson Lee on the master branch built with GCC 8.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105052
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Sun, 25 Feb 2018 02:37:34 +0000 (18:37 -0800)]
util/bitset: Make C++ wrapper trivially constructible.
In order to fix a build failure on compilers not implementing
unrestricted unions, which is a C++11 feature.
v2: Provide signed integer comparison and assignment operators instead
of BITSET_WORD ones to avoid spurious ambiguity warnings on
comparisons with a signed integer literal.
Fixes:
ba79a90fb52e1e81fb "glsl: Switch ast_type_qualifier to a 128-bit bitset."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105238
Tested-by: Roland Scheidegger <sroland@vmware.com>
Tested-By: George Kyriazis <george.kyriazis@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jordan Justen [Sat, 10 Feb 2018 03:06:43 +0000 (19:06 -0800)]
intel/tools: Use gen_device_name_to_pci_device_id in aubinator
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Jordan Justen [Sat, 10 Feb 2018 03:06:12 +0000 (19:06 -0800)]
intel/common: Add gen_device_name_to_pci_device_id
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Jordan Justen [Sat, 10 Feb 2018 02:38:28 +0000 (18:38 -0800)]
intel/vulkan: Support INTEL_DEVID_OVERRIDE environment variable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Jordan Justen [Sat, 10 Feb 2018 02:48:18 +0000 (18:48 -0800)]
i965: Use gen_get_pci_device_id_override
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Jordan Justen [Sat, 10 Feb 2018 01:12:05 +0000 (17:12 -0800)]
intel/common: Add gen_get_pci_device_id_override
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Jordan Justen [Sat, 10 Feb 2018 02:36:43 +0000 (18:36 -0800)]
intel/vulkan: Support INTEL_NO_HW environment variable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Harish Krupo [Tue, 27 Feb 2018 06:44:00 +0000 (12:14 +0530)]
android: fix source files path for libmesa_anv_gen11
Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Fri, 23 Feb 2018 17:08:45 +0000 (17:08 +0000)]
meson: avoid changing types for the dri3 option
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Fri, 23 Feb 2018 17:08:20 +0000 (17:08 +0000)]
meson: simplify the gbm option code, and avoid changing types
v2: drop gallium comment (Dylan)
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Samuel Pitoiset [Mon, 26 Feb 2018 13:05:05 +0000 (14:05 +0100)]
ac/nir: clean up a hack about rounding 2nd coord component
It's basically just the opposite, and it only makes sense to
round the layer for 2D texture arrays.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Ilia Mirkin [Mon, 5 Feb 2018 05:15:58 +0000 (00:15 -0500)]
nvc0: collapse output slots to have adjacent registers
The hardware skips over unallocated slots, so we have to make sure those
registers are packed together.
Fixes KHR-GL45.enhanced_layouts.fragment_data_location_api
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Karol Herbst <kherbst@redhat.com>
Dave Airlie [Mon, 26 Feb 2018 20:51:55 +0000 (20:51 +0000)]
radv: expose async compute on SI
It looks like we had all the pieces in place for this,
just never tested it and turned it on.
I don't see any CTS regressions and the computeshader
demo runs.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 25 Feb 2018 23:23:45 +0000 (23:23 +0000)]
radv: merge tess rings into a single bo
Inspired by a passing commit to radeonsi.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Emil Velikov [Tue, 27 Feb 2018 00:32:14 +0000 (00:32 +0000)]
docs: update calendar, add news and link release notes to 17.3.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Tue, 27 Feb 2018 00:28:54 +0000 (00:28 +0000)]
docs: add sha256 checksums for 17.3.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
b00880973eeab5d29413eb8a27707f62904723ea)
Emil Velikov [Tue, 27 Feb 2018 00:18:33 +0000 (00:18 +0000)]
docs: add release notes for 17.3.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
b3e5a3f35bfe5b69758ceb90f93fffbee01a5682)
Dylan Baker [Mon, 26 Feb 2018 16:43:54 +0000 (08:43 -0800)]
meson: fix building without GL
libgl will be undefined _glx, so move that check inside the
`if with_glx != 'disabled'` block.
v2: - Simplify commit message (Eric, Emil)
Fixes:
5c460337fd9c109 ("meson: Fix GL and EGL pkg-config files with glvnd")
Reported-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
CC: Daniel Stone <daniels@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Untested-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Lionel Landwerlin [Thu, 22 Feb 2018 13:41:10 +0000 (13:41 +0000)]
intel: aubinator_error_decode: fix segfault on missing register
Some register might be missing in our genxmls. Don't try to decode
them.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Engestrom [Fri, 23 Feb 2018 17:02:08 +0000 (17:02 +0000)]
*-symbol-check: use correct `nm` path when cross-compiling
Inspired-by: a similar patch for libdrm by Heiko Becker
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Karol Herbst [Tue, 5 Dec 2017 10:09:54 +0000 (11:09 +0100)]
nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107
currently while insterting barriers, writes and reads to FILE_FLAGS aren't
considered. This can lead to WaR hazards in some situations.
With the previous commit fixes shaders with intstructions like this:
mad u32 $r2 $r4 $r11 $r2
mad u32 { $r5 $c0 } $r4 $r10 $r6
mad (SUBOP:1) u32 $r3 $r4 $r10 $r2 $c0
Affects OpenCL CTS tests on Maxwell+:
basic/test_basic intmath_long
basic/test_basic intmath_long2
basic/test_basic intmath_long4
v2: only put barriers on instructions which actually read flags
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Karol Herbst [Tue, 5 Dec 2017 09:32:25 +0000 (10:32 +0100)]
nvir/gm107: iterate over all defs in SchedDataCalculatorGM107::findFirstUse
In the sched data calculator we have to track first use of defs by iterating
over all defs of an instruction, not just the first one.
v2: fix minGRP and maxGRP values
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Samuel Pitoiset [Fri, 23 Feb 2018 13:21:06 +0000 (14:21 +0100)]
ac/nir: use ordered float comparisons except for not equal
Original patch from Timothy Arceri, I have just fixed the
not equal case locally.
This fixes one important rendering issue in Wolfenstein 2
(the cutscene transition issue).
RadeonSI uses the same ordered comparisons, so I guess that
what we should do as well.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104302
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104905
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Mauro Rossi [Sun, 4 Feb 2018 21:57:11 +0000 (22:57 +0100)]
android: vulkan/util: add dependency on libnativewindow for O and later
Similar to
90dd6e5 ("Android: egl: add dependency on libnativewindow")
Fixes the following building error:
In file included from out/target/product/x86_64/obj_x86/STATIC_LIBRARIES/libmesa_vulkan_util_intermediates/util/vk_enum_to_str.c:26:
external/mesa/include/vulkan/vk_android_native_buffer.h:22:10: fatal error: 'system/window.h' file not found
^~~~~~~~~~~~~~~~~
1 error generated.
Cc: "18.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Mauro Rossi [Mon, 26 Feb 2018 12:42:47 +0000 (14:42 +0200)]
android: anv: add dependency on libnativewindow for O and later
Similar to
90dd6e5 ("Android: egl: add dependency on libnativewindow")
Fixes the following building errors:
In file included from external/mesa/src/intel/vulkan/gen7_cmd_buffer.c:30:
In file included from external/mesa/src/intel/vulkan/anv_private.h:72:
external/mesa/include/vulkan/vk_android_native_buffer.h:22:10: fatal
error: 'system/window.h' file not found
^~~~~~~~~~~~~~~~~
1 error generated.
...
In file included from external/mesa/src/intel/vulkan/anv_gem.c:32:
In file included from external/mesa/src/intel/vulkan/anv_private.h:72:
external/mesa/include/vulkan/vk_android_native_buffer.h:22:10: fatal
error: 'system/window.h' file not found
^~~~~~~~~~~~~~~~~
1 error generated.
Cc: "18.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Mauro Rossi [Sun, 4 Feb 2018 21:57:09 +0000 (22:57 +0100)]
android: anv/extensions: fix generated sources build
Building rules are aligned to automake ones
The correct script to build anv_extensions.{c,h} is anv_extensions_gen.py
Generation rules for anv_extensions.c requires --out-c option
Generation rules for anv_extensions.h were missing
Necessary include paths are added to avoid following build errors:
cp: cannot stat '.../gen/STATIC_LIBRARIES/libmesa_vulkan_common_intermediates/vulkan/anv_extensions.c':
No such file or directory
In file included from external/mesa/src/intel/vulkan/anv_gem.c:32:
external/mesa/src/intel/vulkan/anv_private.h:75:10: fatal error: 'anv_extensions.h' file not found
^~~~~~~~~~~~~~~~~~
1 error generated.
In file included from external/mesa/src/intel/vulkan/anv_batch_chain.c:30:
external/mesa/src/intel/vulkan/anv_private.h:75:10: fatal error: 'anv_extensions.h' file not found
^~~~~~~~~~~~~~~~~~
1 error generated.
Fixes:
dd088d4bec7 ("anv/extensions: Generate a header file with extension tables")
Cc: "18.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Marek Olšák [Thu, 8 Feb 2018 16:26:16 +0000 (17:26 +0100)]
radeonsi: remove 2 unused user SGPRs from merged TES-GS with 32-bit pointers
The effect of the last 13 commits on user SGPR counts:
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 8 Oct 2017 17:38:37 +0000 (19:38 +0200)]
radeonsi: make SI_SGPR_VERTEX_BUFFERS the last user SGPR input
so that it can be removed and replaced with inline VBO descriptors,
and the pointer can be packed in unused bits of VBO descriptors.
This also removes the pointer from merged TES-GS where it's useless.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 7 Feb 2018 00:11:10 +0000 (01:11 +0100)]
radeonsi: set correct num_input_sgprs for VS prolog in merged shaders
We need to take num_input_sgprs from VS, not the second shader.
No apps suffered from this.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 7 Feb 2018 00:09:32 +0000 (01:09 +0100)]
radeonsi: allow fewer input SGPRs in 2nd shader of merged shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 3 Feb 2018 15:10:25 +0000 (16:10 +0100)]
radeonsi: don't use struct si_descriptors for vertex buffer descriptors
VBO descriptor code will change a lot one day.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Daniel Stone [Thu, 22 Feb 2018 09:22:36 +0000 (09:22 +0000)]
build: Move wayland-scanner check into platform
Also only check for wayland-scanner if building for the Wayland
platform.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes:
bfa22266cd4d ("vulkan/wsi/wayland: Add support for zwp_dmabuf")
Cc: Emil Velikov <emil.velikov@collabora.co.uk>
Reported-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105211
Daniel Stone [Thu, 22 Feb 2018 09:21:00 +0000 (09:21 +0000)]
build: Move wayland-protocols check into platform
In line with wayland-client and wayland-server, move the check for
wayland-protocols into the wayland platform branch.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes:
bfa22266cd4d ("vulkan/wsi/wayland: Add support for zwp_dmabuf")
Cc: Emil Velikov <emil.velikov@collabora.co.uk>
Reported-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105211
Daniel Stone [Fri, 23 Feb 2018 11:15:11 +0000 (11:15 +0000)]
vulkan/wsi/wayland: Move Wayland protocol from BUILT_SOURCES
autotools wants to have the BUILT_SOURCES ready as soon as it enters the
directory, even if they are not used. This meant the build failed if
wayland-protocols was not available on the system, even if it was not
enabled.
As BUILT_SOURCES cannot be used in a conditional (cf.
166852ee957f), do
the same thing as EGL and manually encode the dependencies in the
Makefile.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes:
bfa22266cd4d ("vulkan/wsi/wayland: Add support for zwp_dmabuf")
Cc: Emil Velikov <emil.velikov@collabora.co.uk>
Reported-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105211
Dave Airlie [Mon, 26 Feb 2018 01:05:45 +0000 (11:05 +1000)]
r600: fix tgsi clock last setting
On cayman this was hitting an assert later, which probably wasn't
see on non-cayman due to having the t slot.
Fixes:
9041730d1 (r600: add support for ARB_shader_clock.)
Dave Airlie [Mon, 26 Feb 2018 01:05:26 +0000 (11:05 +1000)]
r600: add time lo/hi debugging output.
This just adds the these to the debug prints.
Timothy Arceri [Fri, 23 Feb 2018 06:00:01 +0000 (17:00 +1100)]
radeonsi/nir: enable lowering of fpow
Lowering fpow in NIR rather than LLVM can be beneficial.
Polaris results:
Totals from affected shaders:
SGPRS: 124928 -> 124896 (-0.03 %)
VGPRS: 68616 -> 68332 (-0.41 %)
Spilled SGPRs: 394 -> 413 (4.82 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size:
3668912 ->
3658368 (-0.29 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 18575 -> 18593 (0.10 %)
Wait states: 0 -> 0 (0.00 %)
Fixes:
d6b753920677 "ac/nir: remove emission of nir_op_fpow"
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Fri, 23 Feb 2018 05:42:04 +0000 (16:42 +1100)]
ac: make use of ac_get_llvm_num_components() helper
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 23 Feb 2018 02:46:27 +0000 (13:46 +1100)]
gallium/tgsi: remove is_msaa_sampler array from tgsi_shader_info
Seems to have not been used since
16be87c90429
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Mon, 26 Feb 2018 00:36:49 +0000 (11:36 +1100)]
radeonsi/nir: fix loading of doubles for tess varyings
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 26 Feb 2018 00:36:11 +0000 (11:36 +1100)]
radeonsi/nir: fix lds store in tcs outputs handling
We were ignoring the channel offset.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Gert Wollny [Sat, 24 Feb 2018 10:31:22 +0000 (11:31 +0100)]
r600: Take ALU_EXTENDED into account when evaluating jump offsets
ALU_EXTENDED needs 4 DWORDS instead of the usual 2, hence if the last ALU
clause within a IF-JUMP or ELSE branch is ALU_EXTENDED the target jump
offset needs to be adjusted accordingly.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104654
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Francisco Jerez [Sat, 24 Feb 2018 02:35:59 +0000 (18:35 -0800)]
mesa: Expose EXT_shader_framebuffer_fetch(_non_coherent) on desktop and embedded GL.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 23:55:13 +0000 (15:55 -0800)]
glsl: Silence warnings when reading from a framebuffer fetch output.
Framebuffer fetch outputs are implicitly initialized upon entry to the
fragment shader.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Wed, 14 Feb 2018 19:53:49 +0000 (11:53 -0800)]
glsl: Specify framebuffer fetch coherency mode in lower_blend_equation_advanced().
This requires passing an extra argument to the lowering pass because
the KHR_blend_equation_advanced specification doesn't seem to define
any mechanism for the implementation to determine at compile-time
whether coherent blending can ever be used (not even an "#extension
KHR_blend_equation_advanced_coherent" directive seems to be required
in the shader source AFAICT).
In the long run we'll probably want to do state-dependent recompiles
based on the value of ctx->Color.BlendCoherent, but right now there
would be no benefit from that because the only driver that supports
coherent framebuffer fetch is i965 on SKL+ hardware, which are unable
to support the non-coherent path for the moment because of texture
layout issues, so framebuffer fetch coherency is always enabled for
them.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 23:54:33 +0000 (15:54 -0800)]
glsl: Add support for the framebuffer fetch layout(noncoherent) qualifier.
This allows the application to request framebuffer fetch coherency
with per-fragment output granularity. Coherent framebuffer fetch
outputs (which is the default if no qualifier is present for
compatibility with older versions of the EXT_shader_framebuffer_fetch
extension) will have ir_variable_data::memory_coherent set to true.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 23:26:45 +0000 (15:26 -0800)]
glsl: Allow layout token for EXT_shader_framebuffer_fetch_non_coherent.
EXT_shader_framebuffer_fetch_non_coherent requires layout qualifiers
even on GL(ES) 2.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 23:24:39 +0000 (15:24 -0800)]
glsl: Initialize ir_variable_data::fb_fetch_output earlier for GL(ES) 2.
At the same point where it is initialized on GL(ES) 3.0+ so we can
implement some common layout qualifier handling in a future commit.
Until now the fb_fetch_output flag would be inherited from the
original implicit gl_LastFragData declaration at a later point in the
AST to GLSL IR translation.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 22:54:27 +0000 (14:54 -0800)]
glsl: Replace MESA_shader_framebuffer_fetch extension flags with EXT ones.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 22:18:15 +0000 (14:18 -0800)]
glsl: Switch ast_type_qualifier to a 128-bit bitset.
This should end the drought of bits in the ast_type_qualifier object.
The bitset_t type works pretty much as a drop-in replacement for the
current uint64_t bitset.
The only catch is that the bitset_t type as defined in the previous
commit doesn't have a trivial constructor (because it has a
user-defined constructor), so it cannot be used as union member
without providing a user-defined constructor for the union (which
causes it in turn to be non-trivially constructible). This annoyance
could be easily addressed in C++11 by declaring the default
constructor of bitset_t to be the implicitly defined one -- IMO one
more reason to drop support for GCC 4.2-4.3.
The other minor change was required because glsl_parser_extras.cpp was
hard-coding the type of bitset temporaries as uint64_t, which (unlike
would have been the case if the uint64_t had been replaced with
e.g. an __int128) would otherwise have caused a build failure, because
the boolean conversion operator of bitset_t is marked explicit (if
C++11 is available), so the bitset won't be silently truncated down to
1 bit in order to use it to initialize the uint64_t temporaries
(yikes).
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 22:09:24 +0000 (14:09 -0800)]
util/bitset: Add C++ wrapper for static-size bitsets.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Tue, 13 Feb 2018 00:32:20 +0000 (16:32 -0800)]
util: Add EXPLICIT_CONVERSION macro.
This can be used to specify that a C++ conversion operator is not
meant to be used for implicit conversions, which can lead to
unintended loss of information in some cases. Implemented as a macro
in order to keep old GCC versions happy.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 22:48:20 +0000 (14:48 -0800)]
mesa: Implement glFramebufferFetchBarrierEXT entry point.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 22:46:39 +0000 (14:46 -0800)]
glapi: Update XML for last revision of EXT_shader_framebuffer_fetch.
Desktop GL is now supported, and there is an additional entry-point
for EXT_shader_framebuffer_fetch_non_coherent.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 22:31:32 +0000 (14:31 -0800)]
mesa: Rename MESA_shader_framebuffer_fetch gl_extensions bits to EXT.
The changes I had originally planned for the MESA_shader_framebuffer_fetch
extension have been merged into the EXT spec, there's no point in keeping
MESA_shader_framebuffer_fetch extension enables.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Mon, 12 Feb 2018 22:23:25 +0000 (14:23 -0800)]
mesa: Rename dd_function_table::BlendBarrier to match latest EXT spec.
This GL entry point was renamed to glFramebufferFetchBarrier() in the
EXT extension on request from Khronos members. Update the Mesa
codebase to match the latest spec.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Francisco Jerez [Tue, 13 Feb 2018 22:16:03 +0000 (14:16 -0800)]
i965: Fix KHR_blend_equation_advanced with some render targets.
This reverts two bogus and seemingly useless changes from the commits
referenced below, which broke KHR_blend_equation_advanced (and
EXT_shader_framebuffer_fetch_non_coherent which wasn't exposed yet)
for any kind of render target surface that would cause the
get_isl_surf() call in brw_emit_surface_state() to do anything useful
(notice how the result of get_isl_surf() is completely ignored by the
caller right now), as was the case while using those extensions with
1D array or 3D framebuffers in particular.
Fixes:
f5859b45b1686e8116380d87 "i965/miptree: Switch remaining surfaces to isl"
Fixes:
bf24c3539e4b6989512968ca "i965/miptree: Clean-up unused"
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Marek Olšák [Sat, 3 Feb 2018 14:47:08 +0000 (15:47 +0100)]
radeonsi: remove si_descriptors parameter from emit_shader_pointer functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 3 Feb 2018 03:00:57 +0000 (04:00 +0100)]
radeonsi: preload the tess offchip ring in TES
so that it's not done multiple times in branches
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 3 Feb 2018 02:19:25 +0000 (03:19 +0100)]
radeonsi: move tess ring address into TCS_OUT_LAYOUT, removes 2 TCS user SGPRs
TCS_OUT_LAYOUT has 13 unused bits. That's enough for a 32-bit address
aligned to 512KB. Hey, it's a 13-bit pointer!
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Feb 2018 20:35:20 +0000 (21:35 +0100)]
radeonsi: move 2nd-shader descriptor pointers into s[0:1]
If 32-bit pointers are supported, both pointers can be moved into s[0:1]
and then ESGS has exactly the same user data SGPR declarations as VS.
If 32-bit pointers are not supported, only one pointer can be moved into
s[0:1]. In that case, the 2nd pointer is moved before TCS constants,
so that the location is the same in HS and GS.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 7 Feb 2018 00:31:33 +0000 (01:31 +0100)]
radeonsi: change si_descriptors::shader_userdata_offset type to short
We will want to use SH registers outside of user data SGPRs, like the GFX9
special SGPRs.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 3 Feb 2018 01:03:08 +0000 (02:03 +0100)]
radeonsi: put both tessellation rings into 1 buffer
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 3 Feb 2018 00:51:53 +0000 (01:51 +0100)]
radeonsi: move tessellation ring info into si_screen
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Feb 2018 20:04:57 +0000 (21:04 +0100)]
radeonsi: move TCS_OUT_LAYOUT.PatchVerticesIn to lower bits
For a later patch.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Karol Herbst [Fri, 23 Feb 2018 21:51:05 +0000 (22:51 +0100)]
nvir: dont optimize mad with subops to shladd
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
James Legg [Thu, 22 Feb 2018 16:57:53 +0000 (16:57 +0000)]
radv: Really use correct HTILE expanded words.
When transitioning to an htile compressed depth format, Set the full
depth range, so later rasterization can pass HiZ. Previously, for depth
only formats, the depth range was set to 0 to 0. This caused unwanted
HiZ rejections with a VK_FORMAT_D16_UNORM depth buffer
(VK_FORMAT_D32_SFLOAT was not affected somehow).
These values are derived from PAL [0], since I can't find the
specification describing the htile values.
[0] https://github.com/GPUOpen-Drivers/pal/blob/
5cba4ecbda9452773f59692f5915301e7db4a183/src/core/hw/gfxip/gfx9/gfx9MaskRam.cpp#L1500
CC: Dave Airlie <airlied@redhat.com>
CC: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Fixes:
5158603182fe7435 "radv: Use correct HTILE expanded words."
Mauro Rossi [Fri, 23 Feb 2018 22:33:37 +0000 (23:33 +0100)]
radv/extensions: fix c_vk_version for patch == None
Similar to
cb0d1ba156 ("anv/extensions: Fix VkVersion::c_vk_version for patch == None")
fixes the following building errors:
out/target/product/x86_64/obj_x86/STATIC_LIBRARIES/libmesa_radv_common_intermediates/radv_entrypoints.c:1161:48:
error: use of undeclared identifier 'None'; did you mean 'long'?
return instance && VK_MAKE_VERSION(1, 0, None) <= core_version;
^~~~
long
external/mesa/include/vulkan/vulkan.h:34:43: note: expanded from macro 'VK_MAKE_VERSION'
(((major) << 22) | ((minor) << 12) | (patch))
^
...
fatal error: too many errors emitted, stopping now [-ferror-limit=]
20 errors generated.
Fixes:
e72ad05c1d ("radv: Return NULL for entrypoints when not supported.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Anholt [Thu, 2 Nov 2017 23:59:10 +0000 (16:59 -0700)]
broadcom/vc5: Fix layout of 3D textures.
Cube maps are entire miptrees repeated, while 3D textures have each level
have all of its layers next to each other. Fixes tex3d and
tex-miplevel-selection GL2:texture() 3D.
Eric Anholt [Fri, 23 Feb 2018 17:10:36 +0000 (09:10 -0800)]
broadcom/vc5: Ignore unused usage flags in is_format_supported.
Like for vc4, the new DISPLAY_TARGET flag ended up causing no formats to
match. Just drop the whole retval == usage thing and return early when we
hit a known unsupported case.
Fixes:
f7604d8af521 ("st/dri: only expose config formats that are display targets")
Eric Anholt [Fri, 23 Feb 2018 22:55:51 +0000 (14:55 -0800)]
gbm: Fix the alpha masks in the GBM format table.
Once GBM started looking at the values of the alpha masks, ARGB/ABGR
wouldn't match any more because we had both A and R in the low bits.
Fixes:
2ed344645d65 ("gbm/dri: Add RGBA masks to GBM format table")
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Mathias Fröhlich [Fri, 23 Feb 2018 19:46:20 +0000 (20:46 +0100)]
mesa: Update vertex processing mode on _mesa_UseProgram.
The change is a bug fix for
92d76a169:
mesa: Provide an alternative to get_vp_mode()
that actually got exposed through
4562a7b0:
vbo: Make use of _DrawVAO from the dlist code.
Fixes: KHR-GLES31.core.shader_image_load_store.advanced-sso-simple
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105229
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 14 Feb 2018 22:21:14 +0000 (23:21 +0100)]
mesa: rename has_core_gs -> has_gs in get_programiv
This is also true for GLES.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 14 Feb 2018 20:19:33 +0000 (21:19 +0100)]
mesa: replace some API_OPENGL_CORE checks with _mesa_is_desktop_gl
This is more accurate with respect to the compatibility profile.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 14 Feb 2018 21:32:59 +0000 (22:32 +0100)]
mesa: add some of missing compatibility support for ARB_bindless_texture
The extension is exposed in the compatibility profile.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 14 Feb 2018 22:42:08 +0000 (23:42 +0100)]
mesa: expose ARB_enhanced_layouts in the compatibility profile
GLSL 1.40 is required.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 14 Feb 2018 19:13:40 +0000 (20:13 +0100)]
mesa: enable OpenGL 3.1 with ARB_compatibility
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 14 Feb 2018 19:12:51 +0000 (20:12 +0100)]
mesa: implement ARB_compatibility
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Brian Paul <brianp@vmware.com>