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Chandler Carruth [Wed, 7 Feb 2018 23:59:14 +0000 (23:59 +0000)]
[x86] Fix nasty bug in the x86 backend that is essentially impossible to
hit from IR but creates a minefield for MI passes.
The x86 backend has fairly powerful logic to try and fold loads that
feed register operands to instructions into a memory operand on the
instruction. This is almost always a good thing, but there are specific
relocated loads that are only allowed to appear in specific
instructions. Notably, R_X86_64_GOTTPOFF is only allowed in `movq` and
`addq`. This patch blocks folding of memory operands using this
relocation unless the target is in fact `addq`.
The particular relocation indicates why we simply don't hit this under
normal circumstances. This relocation is only used for TLS, and it gets
used in very specific ways in conjunction with %fs-relative addressing.
The result is that loads using this relocation are essentially never
eligible for folding into an instruction's memory operands. Unless, of
course, you have an MI pass that inserts usage of such a load. I have
exactly such an MI pass and was greeted by truly mysterious miscompiles
where the linker replaced my instruction with a completely garbage byte
sequence. Go team.
This is the only such relocation I'm aware of in x86, but there may be
others that need to be similarly restricted.
Fixes PR36165.
Differential Revision: https://reviews.llvm.org/D42732
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324546
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Mircea Trofin [Wed, 7 Feb 2018 23:29:52 +0000 (23:29 +0000)]
Verify profile data confirms large loop trip counts.
Summary:
Loops with inequality comparers, such as:
// unsigned bound
for (unsigned i = 1; i < bound; ++i) {...}
have getSmallConstantMaxTripCount report a large maximum static
trip count - in this case, 0xffff fffe. However, profiling info
may show that the trip count is much smaller, and thus
counter-recommend vectorization.
This change:
- flips loop-vectorize-with-block-frequency on by default.
- validates profiled loop frequency data supports vectorization,
when static info appears to not counter-recommend it. Absence
of profile data means we rely on static data, just as we've
done so far.
Reviewers: twoh, mkuper, davidxl, tejohnson, Ayal
Reviewed By: davidxl
Subscribers: bkramer, llvm-commits
Differential Revision: https://reviews.llvm.org/D42946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324543
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Craig Topper [Wed, 7 Feb 2018 22:45:38 +0000 (22:45 +0000)]
[X86] Prune some unreachable 'return SDValue()' paths from LowerSIGN_EXTEND/LowerZERO_EXTEND/LowerANY_EXTEND.
We were doing a lot of whitelisting of what we handle in these routines, but setOperationAction constrains what we can get here. So just add some asserts and prune the unreachable paths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324538
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Craig Topper [Wed, 7 Feb 2018 22:19:26 +0000 (22:19 +0000)]
[X86] Remove dead code from EmitTest that looked for an i1 type which should have already been type legalized away. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324536
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Craig Topper [Wed, 7 Feb 2018 21:41:50 +0000 (21:41 +0000)]
[X86] When doing callee save/restore for k-registers make sure we don't use KMOVQ on non-BWI targets
If we are saving/restoring k-registers, the default behavior of getMinimalRegisterClass will find the VK64 class with a spill size of 64 bits. This will cause the KMOVQ opcode to be used for save/restore. If we don't have have BWI instructions we need to constrain the class returned to give us VK16 with a 16-bit spill size. We can do this by passing the either v16i1 or v64i1 into getMinimalRegisterClass.
Also add asserts to make sure BWI is enabled anytime we use KMOVD/KMOVQ. These are what caught this bug.
Fixes PR36256
Differential Revision: https://reviews.llvm.org/D42989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324533
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Craig Topper [Wed, 7 Feb 2018 21:29:30 +0000 (21:29 +0000)]
[X86] Auto-generate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324530
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Momchil Velikov [Wed, 7 Feb 2018 20:28:47 +0000 (20:28 +0000)]
Revert "[DebugInfo] Improvements to representation of enumeration types (PR36168)"
Revert commit r324489, it broke LLDB tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324511
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Alexey Bataev [Wed, 7 Feb 2018 20:11:37 +0000 (20:11 +0000)]
[SLP] Add a tests for PR36280, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324510
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Zachary Turner [Wed, 7 Feb 2018 19:37:52 +0000 (19:37 +0000)]
Generate PDB files for profiling even in Release build.
This patch enables PDB generation for Release build, which has
slightly different optimize option with RelWithDebInfo on windows.
This helps to know slow part of Release build when profiling.
Patch by Takuto Ikuta
Differential Revision: https://reviews.llvm.org/D42632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324504
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Craig Topper [Wed, 7 Feb 2018 18:32:15 +0000 (18:32 +0000)]
[X86] Regenerate test using update_mir_test_checks.py. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324497
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Rafael Espindola [Wed, 7 Feb 2018 18:09:35 +0000 (18:09 +0000)]
Revert "AMDGPU: Add 32-bit constant address space"
This reverts commit r324487.
It broke clang tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324494
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Jonas Devlieghere [Wed, 7 Feb 2018 17:35:27 +0000 (17:35 +0000)]
Revert dsymutil -update commits
Revert "[dsymutil][test] Check the updated dSYM instead of companion file."
Revert "[dsymutil] Upstream update feature."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324493
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Nirav Dave [Wed, 7 Feb 2018 17:12:34 +0000 (17:12 +0000)]
[SelectionDAG] More Aggressibly prune nodes in AddChains. NFCI.
Travel all chains paths to first non-tokenfactor node can be
exponential work. Add simple redundency check to avoid this.
Fixes PR36264.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324491
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Momchil Velikov [Wed, 7 Feb 2018 16:46:33 +0000 (16:46 +0000)]
[DebugInfo] Improvements to representation of enumeration types (PR36168)
This patch is the LLVM part of fixing the issues, described in
https://bugs.llvm.org/show_bug.cgi?id=36168
* The representation of enumerator values in the debug info metadata now
contains a boolean flag isUnsigned, which determines how the bits of
the value are interpreted.
* The DW_TAG_enumeration type DIE now always (for DWARF version >= 3)
includes a DW_AT_type attribute, which refers to the underlying
integer type, as suggested in DWARFv4 (5.7 Enumeration Type Entries).
* The debug info metadata for enumeration type contains (in flags)
indication whether this is a C++11 "fixed enum".
* For C++11 enumeration with a fixed underlying type, the DIE also
includes the DW_AT_enum_class attribute (for DWARF version >= 4).
* Encoding of enumerator constants uses DW_FORM_sdata for signed values
and DW_FORM_udata for unsigned values, as suggested by DWARFv4 (7.5.4
Attribute Encodings).
The changes should be backwards compatible:
* the isUnsigned attribute is optional and defaults to false.
* if the underlying type for the enumeration is not available, the
enumerator values are considered signed.
* the FixedEnum flag defaults to clear.
* the bitcode format for DIEnumerator stores the unsigned flag bit #1 of
the first record element, so the format does not change and the zero
previously stored there is consistent with the false default for
IsUnsigned.
Differential Revision: https://reviews.llvm.org/D42734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324489
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Marek Olsak [Wed, 7 Feb 2018 16:01:00 +0000 (16:01 +0000)]
AMDGPU: Add 32-bit constant address space
Note: This is a candidate for LLVM 6.0, because it was planned to be
in that release but was delayed due to a long review period.
Merge conflict in release_60 - resolution:
Add "-p6:32:32" into the second (non-amdgiz) string.
Only scalar loads support 32-bit pointers. An address in a VGPR will
fail to compile. That's OK because the results of loads will only be used
in places where VGPRs are forbidden.
Updated AMDGPUAliasAnalysis and used SReg_64_XEXEC.
The tests cover all uses cases we need for Mesa.
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D41651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324487
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Marek Olsak [Wed, 7 Feb 2018 16:00:40 +0000 (16:00 +0000)]
AMDGPU: Remove the s_buffer workaround for GFX9 chips
Summary:
I checked the AMD closed source compiler and the workaround is only
needed when x3 is emulated as x4, which we don't do in LLVM.
SMEM x3 opcodes don't exist, and instead there is a possibility to use x4
with the last component being unused. If the last component is out of
buffer bounds and falls on the next 4K page, the hw hangs.
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D42756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324486
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Simon Pilgrim [Wed, 7 Feb 2018 15:48:44 +0000 (15:48 +0000)]
[X86][AVX] Add PACKSSDW/PACKUSDW support for truncation of clamped values
SSE and shorter vector sizes will have to wait until we can add support for general SMIN/SMAX matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324485
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Jonas Devlieghere [Wed, 7 Feb 2018 15:18:21 +0000 (15:18 +0000)]
[dsymutil][test] Check the updated dSYM instead of companion file.
This patch has llvm-dwarfdump check the whole dSYM, rather than the
hard-coded path to the Mach-O companion file. This might be what's
causing the Windows bot to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324483
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Clement Courbet [Wed, 7 Feb 2018 14:26:43 +0000 (14:26 +0000)]
[SLPVectorizer][NFC] Make a loop more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324482
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Jonas Devlieghere [Wed, 7 Feb 2018 13:51:29 +0000 (13:51 +0000)]
[dsymutil] Upstream update feature.
Now that dsymutil can generate accelerator tables, we can upstream the
update logic that, as the name implies, updates the accelerator tables
in an existing dSYM bundle. In combination with `-minimize` this can be
used to remove redundant .debug_(inlines|pubtypes|pubnames).
Differential revision: https://reviews.llvm.org/D42880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324480
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Simon Pilgrim [Wed, 7 Feb 2018 13:28:23 +0000 (13:28 +0000)]
[X86] Regenerate atomic i32 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324479
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Benjamin Kramer [Wed, 7 Feb 2018 12:55:01 +0000 (12:55 +0000)]
[Orc] Pacify -pedantic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324478
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Simon Atanasyan [Wed, 7 Feb 2018 12:36:39 +0000 (12:36 +0000)]
[mips] Support 'y' operand code to print exact log2 of the operand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324477
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Simon Atanasyan [Wed, 7 Feb 2018 12:36:33 +0000 (12:36 +0000)]
[mips] Handle 'M' and 'L' operand codes for memory operands
Both operand codes now work the same way in case of register or memory
operands. It print high-order or low-order word in a double-word
register or memory location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324476
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Pavel Labath [Wed, 7 Feb 2018 11:19:29 +0000 (11:19 +0000)]
[BinaryFormat] Remove dangling declaration of DiscriminantString
The implementation of the function was deleted in r324426. This also
removes the declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324474
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Max Kazantsev [Wed, 7 Feb 2018 11:16:29 +0000 (11:16 +0000)]
Re-enable "[SCEV] Make isLoopEntryGuardedByCond a bit smarter"
The failures happened because of assert which was overconfident about
SCEV's proving capabilities and is generally not valid.
Differential Revision: https://reviews.llvm.org/D42835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324473
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Clement Courbet [Wed, 7 Feb 2018 09:58:55 +0000 (09:58 +0000)]
[MergeICmps] Re-commit rL324317 "Enable the MergeICmps Pass by default."
With fixes from rL324341.
Original commit message:
[MergeICmps] Enable the MergeICmps Pass by default.
Summary: Now that PR33325 is fixed, this should always improve the generated code.
Reviewers: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324465
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Serguei Katkov [Wed, 7 Feb 2018 09:10:08 +0000 (09:10 +0000)]
Revert [SCEV] Make isLoopEntryGuardedByCond a bit smarter
Revert rL324453 commit which causes buildbot failures.
Differential Revision: https://reviews.llvm.org/D42835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324462
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George Rimar [Wed, 7 Feb 2018 08:46:36 +0000 (08:46 +0000)]
Revert r324455 "[ThinLTO] - Simplify code in ThinLTOBitcodeWriter."
It broke BB:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/23721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324458
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Sjoerd Meijer [Wed, 7 Feb 2018 08:37:17 +0000 (08:37 +0000)]
[ARM] FP16 mov imm pattern
This is a follow up of r324321, adding a match pattern for mov with a FP16
immediate (also fixing operand vfp_f16imm that wasn't even compiling).
Differential Revision: https://reviews.llvm.org/D42973
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324456
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George Rimar [Wed, 7 Feb 2018 08:32:35 +0000 (08:32 +0000)]
[ThinLTO] - Simplify code in ThinLTOBitcodeWriter.
Recently introduced convertToDeclaration is very similar
to code used in filterModule function.
Patch reuses it to reduce duplication.
Differential revision: https://reviews.llvm.org/D42971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324455
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Max Kazantsev [Wed, 7 Feb 2018 07:56:26 +0000 (07:56 +0000)]
[SCEV] Make isLoopEntryGuardedByCond a bit smarter
Sometimes `isLoopEntryGuardedByCond` cannot prove predicate `a > b` directly.
But it is a common situation when `a >= b` is known from ranges and `a != b` is
known from a dominating condition. Thia patch teaches SCEV to sum these facts
together and prove strict comparison via non-strict one.
Differential Revision: https://reviews.llvm.org/D42835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324453
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Michael Zolotukhin [Wed, 7 Feb 2018 06:54:11 +0000 (06:54 +0000)]
The xfailed test from r324448 passed on one of the bots: remove it entirely for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324451
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Serguei Katkov [Wed, 7 Feb 2018 06:53:37 +0000 (06:53 +0000)]
[LoopPrediction] Introduce utility function getLatchPredicateForGuard. NFC.
Factor out getting the predicate for latch condition in a guard to
utility function getLatchPredicateForGuard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324450
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Chandler Carruth [Wed, 7 Feb 2018 06:16:24 +0000 (06:16 +0000)]
[x86/retpoline] Make the external thunk names exactly match the names
that happened to end up in GCC.
This is really unfortunate, as the names don't have much rhyme or reason
to them. Originally in the discussions it seemed fine to rely on aliases
to map different names to whatever external thunk code developers wished
to use but there are practical problems with that in the kernel it turns
out. And since we're discovering this practical problems late and since
GCC has already shipped a release with one set of names, we are forced,
yet again, to blindly match what is there.
Somewhat rushing this patch out for the Linux kernel folks to test and
so we can get it patched into our releases.
Differential Revision: https://reviews.llvm.org/D42998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324449
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Michael Zolotukhin [Wed, 7 Feb 2018 06:11:50 +0000 (06:11 +0000)]
Xfail the test added in r324445 until the underlying issue in LoopSink is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324448
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Eugene Leviant [Wed, 7 Feb 2018 05:38:29 +0000 (05:38 +0000)]
[LegalizeDAG] Truncate condition operand of ISD::SELECT
Differential revision: https://reviews.llvm.org/D42737
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324447
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Tom Stellard [Wed, 7 Feb 2018 04:47:59 +0000 (04:47 +0000)]
AMDGPU/GlobalISel: Mark 32-bit G_FPTOUI as legal
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D42152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324446
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Michael Zolotukhin [Wed, 7 Feb 2018 04:24:44 +0000 (04:24 +0000)]
Follow-up for r324429: "[LCSSAVerification] Run verification only when asserts are enabled."
Before r324429 we essentially didn't have a verification of LCSSA, so
no wonder that it has been broken: currently loop-sink breaks it (the
attached test illustrates the failure).
It was detected during a stage2 RA build, so to unbreak it I'm disabling
the check for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324445
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Teresa Johnson [Wed, 7 Feb 2018 04:05:59 +0000 (04:05 +0000)]
[ThinLTO] Serialize WithGlobalValueDeadStripping index flag for distributed backends
Summary:
A recent fix to drop dead symbols (r323633) did not work for ThinLTO
distributed backends because we lose the WithGlobalValueDeadStripping
set on the index during the thin link. This patch adds a new flags
record to the bitcode format for the index, and serializes this flag
for the combined index (it would always be 0 for the per-module index
generated by the compile step, so no need to serialize the new flags
record there until/unless we add another flag that applies to the
per-module indexes).
Generally this flag should always be set for the distributed backends,
which are necessarily performed after the thin link. However, if we were
to simply set this flag on the index applied to the distributed backends
(invoked via clang), we would lose the ability to disable dead stripping
via -compute-dead=false for debugging purposes.
Reviewers: grimar, pcc
Subscribers: mehdi_amini, inglorion, eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D42799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324444
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Volkan Keles [Wed, 7 Feb 2018 02:44:51 +0000 (02:44 +0000)]
GlobalISel: Always check operand types when executing match table
Summary:
Some of the commands tries to get the register without checking
if the specified operands is a register and causing crash. All commands
should check the type of the operand first and reject if the type is
not expected.
Reviewers: dsanders, qcolombet
Reviewed By: qcolombet
Subscribers: qcolombet, rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D42984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324442
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Mark Searles [Wed, 7 Feb 2018 02:21:21 +0000 (02:21 +0000)]
[AMDGPU] Suppress redundant waitcnt instrs.
1. Run the memory legalizer prior to the waitcnt pass; keep the policy that the waitcnt pass does not remove any waitcnts within the incoming IR.
2. The waitcnt pass doesn't (yet) track waitcnts that exist prior to the waitcnt pass (it just skips over them); because the waitcnt pass is ignorant of them, it may insert a redundant waitcnt. To avoid this, check the prev instr. If it and the to-be-inserted waitcnt are the same, suppress the insertion. We keep the existing waitcnt under the assumption that whomever, e.g., the memory legalizer, inserted it knows what they were doing.
3. Follow-on work: teach the waitcnt pass to record the pre-existing waitcnts for better waitcnt production.
Differential Revision: https://reviews.llvm.org/D42854
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324440
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Craig Topper [Wed, 7 Feb 2018 00:51:37 +0000 (00:51 +0000)]
[Mips][AMDGPU] Update test cases to not use vector lt/gt compares that can be simplified to an equality/inequality or to always true/false.
For example 'ugt X, 0' can be simplified to 'ne X, 0'. Or 'uge X, 0' is always true.
We already simplify this for scalars in SimplifySetCC, but we don't currently for vectors in SimplifySetCC. D42948 proposes to change that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324436
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Matt Arsenault [Wed, 7 Feb 2018 00:21:34 +0000 (00:21 +0000)]
AMDGPU: Select BFI patterns with 64-bit ints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324431
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Michael Zolotukhin [Wed, 7 Feb 2018 00:13:08 +0000 (00:13 +0000)]
[LCSSAVerification] Run verification only when asserts are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324429
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Craig Topper [Tue, 6 Feb 2018 23:54:37 +0000 (23:54 +0000)]
[DAGCombiner][AMDGPU][X86] Turn cttz/ctlz into cttz_zero_undef/ctlz_zero_undef if we can prove the input is never zero
X86 currently has a late DAG combine after cttz/ctlz are turned into BSR+BSF+CMOV to detect this and remove the CMOV. But we should be able to do this much earlier and avoid creating the cmov all together.
For the changed AMDGPU test case it appears that previously the i8 cttz was type legalized to i16 which introduced an OR with 256 in order to limit the result to 8 on the widened type. At this point the result is known to never be zero, but nothing checked that. Then operation legalization is told to promote all i16 cttz to i32. This introduces an extend and a truncate and another OR with 65536 to limit the result to 16. With the DAG combiner change we are able to prevent the creation of the second OR since the opcode will have been changed to cttz_zero_undef after the first OR. I the lack of the OR caused the instruction to change to v_ffbl_b32_sdwa
Differential Revision: https://reviews.llvm.org/D42985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324427
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Adrian Prantl [Tue, 6 Feb 2018 23:45:59 +0000 (23:45 +0000)]
Add DWARF for discriminated unions
n Rust, an enum that carries data in the variants is, essentially, a
discriminated union. Furthermore, the Rust compiler will perform
space optimizations on such enums in some situations. Previously,
DWARF for these constructs was emitted using a hack (a magic field
name); but this approach stopped working when more space optimizations
were added in https://github.com/rust-lang/rust/pull/45225.
This patch changes LLVM to allow discriminated unions to be
represented in DWARF. It adds createDiscriminatedUnionType and
createDiscriminatedMemberType to DIBuilder and then arranges for this
to be emitted using DWARF's DW_TAG_variant_part and DW_TAG_variant.
Note that DWARF requires that a discriminated union be represented as
a structure with a variant part. However, as Rust only needs to emit
pure discriminated unions, this is what I chose to expose on
DIBuilder.
Patch by Tom Tromey!
Differential Revision: https://reviews.llvm.org/D42082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324426
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Eli Friedman [Tue, 6 Feb 2018 23:22:14 +0000 (23:22 +0000)]
Place undefined globals in .bss instead of .data
Following up on the discussion from
http://lists.llvm.org/pipermail/llvm-dev/2017-April/112305.html, undef
values are now placed in the .bss as well as null values. This prevents
undef global values taking up potentially huge amounts of space in the
.data section.
The following two lines now both generate equivalent .bss data:
@vals1 = internal unnamed_addr global [
20000000 x i32] zeroinitializer, align 4
@vals2 = internal unnamed_addr global [
20000000 x i32] undef, align 4 ; previously unaccounted for
This is primarily motivated by the corresponding issue in the Rust
compiler (https://github.com/rust-lang/rust/issues/41315).
Differential Revision: https://reviews.llvm.org/D41705
Patch by varkor!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324424
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Eli Friedman [Tue, 6 Feb 2018 23:00:17 +0000 (23:00 +0000)]
[LivePhysRegs] Fix handling of return instructions.
See D42509 for the original version of this.
Basically, there are two significant changes to behavior here:
- addLiveOuts always adds all pristine registers (even if a block has
no successors).
- addLiveOuts and addLiveOutsNoPristines always add all callee-saved
registers for return blocks (including conditional return blocks).
I cleaned up the functions a bit to make it clear these properties hold.
Differential Revision: https://reviews.llvm.org/D42655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324422
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Evandro Menezes [Tue, 6 Feb 2018 22:35:47 +0000 (22:35 +0000)]
[AArch64] Adjust the cost model for Exynos M3
Fix the modeling of long division and SIMD conversion from integer and
horizontal minimum and maximum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324417
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Andrew Kaylor [Tue, 6 Feb 2018 22:28:15 +0000 (22:28 +0000)]
Add SelectionDAGDumper support for strict FP nodes
Patch by Kevin P. Neal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324416
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Lang Hames [Tue, 6 Feb 2018 22:22:10 +0000 (22:22 +0000)]
Add OrcJIT dependency for Kaleidoscope Chapter 9.
This should fix the error at
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-expensive/10421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324413
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Adrian Prantl [Tue, 6 Feb 2018 22:17:45 +0000 (22:17 +0000)]
Fix a crash when emitting DIEs for variable-length arrays
VLAs may refer to a previous DIE to express the DW_AT_count of their
type. Clang generates an artificial "vla_expr" variable for this. If
this DIE hasn't been created yet LLVM asserts. This patch fixes this
by sorting the local variables so that dependencies come before they
are needed. It also replaces the linear scan in DWARFFile with a
std::map, which can be faster.
Differential Revision: https://reviews.llvm.org/D42940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324412
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Lang Hames [Tue, 6 Feb 2018 22:17:09 +0000 (22:17 +0000)]
[ORC] Use explicit constructor calls to fix a builder error at
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/17627
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324411
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Lang Hames [Tue, 6 Feb 2018 21:52:46 +0000 (21:52 +0000)]
[ORC] Remove some unused lambda captures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324410
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Craig Topper [Tue, 6 Feb 2018 21:47:04 +0000 (21:47 +0000)]
[X86] Add test cases that exercise the BSR/BSF optimization combineCMov.
combineCmov tries to remove compares against BSR/BSF if we can prove the input to the BSR/BSF are never zero.
As far as I can tell most of the time codegenprepare despeculates ctlz/cttz and gives us a cttz_zero_undef/ctlz_zero_undef which don't use a cmov.
So the only way I found to trigger this code is to show codegenprepare an illegal type which it won't despeculate.
I think we should be turning ctlz/cttz into ctlz_zero_undef/cttz_zero_undef for these cases before we ever get to operation legalization where the cmov is created. But wanted to add these tests so we don't regress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324409
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Sanjay Patel [Tue, 6 Feb 2018 21:43:57 +0000 (21:43 +0000)]
[x86] add tests to show demanded bits shortcoming; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324408
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Lang Hames [Tue, 6 Feb 2018 21:25:20 +0000 (21:25 +0000)]
[docs] Add out-of-date warnings to the BuildingAJIT tutorial text.
The text will be updated once the ORC API churn dies down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324406
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Lang Hames [Tue, 6 Feb 2018 21:25:11 +0000 (21:25 +0000)]
[ORC] Start migrating ORC layers to use the new ORC Core.h APIs.
In particular this patch switches RTDyldObjectLinkingLayer to use
orc::SymbolResolver and threads the requried changse (ExecutionSession
references and VModuleKeys) through the existing layer APIs.
The purpose of the new resolver interface is to improve query performance and
better support parallelism, both in JIT'd code and within the compiler itself.
The most visibile change is switch of the <Layer>::addModule signatures from:
Expected<Handle> addModule(std::shared_ptr<ModuleType> Mod,
std::shared_ptr<JITSymbolResolver> Resolver)
to:
Expected<Handle> addModule(VModuleKey K, std::shared_ptr<ModuleType> Mod);
Typical usage of addModule will now look like:
auto K = ES.allocateVModuleKey();
Resolvers[K] = createSymbolResolver(...);
Layer.addModule(K, std::move(Mod));
See the BuildingAJIT tutorial code for example usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324405
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Sanjay Patel [Tue, 6 Feb 2018 21:25:02 +0000 (21:25 +0000)]
[AArch64] add test to show sub-optimal isel; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324404
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Sanjay Patel [Tue, 6 Feb 2018 21:18:53 +0000 (21:18 +0000)]
[x86] add test to show missed BMI isel; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324403
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Daniel Neilson [Tue, 6 Feb 2018 21:18:33 +0000 (21:18 +0000)]
[DSE] Upgrade uses of MemoryIntrinic::getAlignment() to new API. (NFC)
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
DeadStoreElimination pass to cease using the old getAlignment() API of MemoryIntrinsic
in favour of getting dest specific alignments through the new API.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324402
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Sanjay Patel [Tue, 6 Feb 2018 21:09:42 +0000 (21:09 +0000)]
[TargetLowering] use local variable to reduce duplication; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324401
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Sanjay Patel [Tue, 6 Feb 2018 20:49:28 +0000 (20:49 +0000)]
[TargetLowering] use local variables to reduce duplication; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324397
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Daniel Neilson [Tue, 6 Feb 2018 20:33:36 +0000 (20:33 +0000)]
[InferAddressSpaces] Update uses of IRBuilder memory intrinsic creation to new API
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
InferAddressSpaces pass to cease using:
1) The old getAlignment() API of MemoryIntrinsic in favour of getting source & dest specific
alignments through the new API.
2) The old IRBuilder CreateMemCpy/CreateMemMove single-alignment APIs in favour of the new
API that allows setting source and destination alignments independently.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324395
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Paul Robinson [Tue, 6 Feb 2018 20:29:21 +0000 (20:29 +0000)]
[DWARFv5] Emit .debug_line_str (in a non-DWO file).
This should enable the linker to do string-pooling of path names.
Differential Revision: https://reviews.llvm.org/D42707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324393
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Krzysztof Parzyszek [Tue, 6 Feb 2018 20:22:20 +0000 (20:22 +0000)]
[Hexagon] Extract HVX lowering and selection into HVX-specific files, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324392
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Krzysztof Parzyszek [Tue, 6 Feb 2018 20:18:58 +0000 (20:18 +0000)]
[Hexagon] Lower concat of more than 2 vectors into build_vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324391
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Alexey Bataev [Tue, 6 Feb 2018 20:00:05 +0000 (20:00 +0000)]
[SLP] Update test checks, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324387
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Daniel Neilson [Tue, 6 Feb 2018 19:14:31 +0000 (19:14 +0000)]
[InlineFunction] Update deprecated use of IRBuilder CreateMemCpy (NFC)
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
InlineFunction pass to ceause using the old IRBuilder CreateMemCpy single-alignment API
in favour of the new API that allows setting source and destination alignments independently.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324384
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Stanislav Mekhanoshin [Tue, 6 Feb 2018 19:11:56 +0000 (19:11 +0000)]
[AMDGPU] removed dead code handling rmw in memory legalizer
It was always using cmpxchg path and in rmw and cmpxchg instructions
are not distinguishable in the BE.
Differential Revision: https://reviews.llvm.org/D42976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324383
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Krzysztof Parzyszek [Tue, 6 Feb 2018 19:08:41 +0000 (19:08 +0000)]
[Hexagon] Don't form new-value jumps from floating-point instructions
Additionally, verify that the register defined by the producer is a
32-bit register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324381
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Simon Pilgrim [Tue, 6 Feb 2018 18:39:23 +0000 (18:39 +0000)]
[InstCombine][ValueTracking] Match non-uniform constant power-of-two vectors
Generalize existing constant matching to work with non-uniform constant vectors as well.
Differential Revision: https://reviews.llvm.org/D42818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324369
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Craig Topper [Tue, 6 Feb 2018 18:18:49 +0000 (18:18 +0000)]
[X86] Auto-generate checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324367
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Sjoerd Meijer [Tue, 6 Feb 2018 16:28:43 +0000 (16:28 +0000)]
[ARM] f16 conversions
This is a follow up of r324321, adding f16 <-> f32 and f16 <-> f64 conversion
match patterns.
Differential Revision: https://reviews.llvm.org/D42954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324360
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Nirav Dave [Tue, 6 Feb 2018 16:14:29 +0000 (16:14 +0000)]
[DAG, X86] Improve Dependency analysis when doing multi-node
Instruction Selection
Cleanup cycle/validity checks in ISel (IsLegalToFold,
HandleMergeInputChains) and X86 (isFusableLoadOpStore). Now do a full
search for cycles / dependencies pruning the search when topological
property of NodeId allows.
As part of this propogate the NodeId-based cutoffs to narrow
hasPreprocessorHelper searches.
Reviewers: craig.topper, bogner
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D41293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324359
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Simon Pilgrim [Tue, 6 Feb 2018 16:10:12 +0000 (16:10 +0000)]
Regenerate vector-urem test. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324357
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Marek Olsak [Tue, 6 Feb 2018 15:17:55 +0000 (15:17 +0000)]
AMDGPU: Fix S_BUFFER_LOAD_DWORD_SGPR moveToVALU
Author: Bas Nieuwenhuizen
https://reviews.llvm.org/D42881
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324353
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Krzysztof Parzyszek [Tue, 6 Feb 2018 15:15:13 +0000 (15:15 +0000)]
[Hexagon] Remove leftover assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324352
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Krzysztof Parzyszek [Tue, 6 Feb 2018 14:24:57 +0000 (14:24 +0000)]
[Hexagon] Split HVX operations on vector pairs
Vector pairs are legal types, but not every operation can work on pairs.
For those operations that are legal for single vectors, generate a concat
of their results on pair halves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324350
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Krzysztof Parzyszek [Tue, 6 Feb 2018 14:21:31 +0000 (14:21 +0000)]
[Hexagon] Add helper functions to identify single/pair vector types, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324349
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Krzysztof Parzyszek [Tue, 6 Feb 2018 14:16:52 +0000 (14:16 +0000)]
[Hexagon] Handle lowering of SETCC via setCondCodeAction
It was expanded directly into instructions earlier. That was to avoid
loads from a constant pool for a vector negation: "xor x, splat(i1 -1)".
Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of
all true and all false values, and handle setcc with negations through
selection patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324348
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Simon Pilgrim [Tue, 6 Feb 2018 14:07:46 +0000 (14:07 +0000)]
[X86][SSE] Add PACKUS support for truncation of clamped values
Followup to D42544 that matches PACKUSWB cases for non-AVX512, SSE and PACKUSDW cases will have to wait until we can add support for general SMIN/SMAX matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324347
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Tim Renouf [Tue, 6 Feb 2018 13:39:38 +0000 (13:39 +0000)]
[AMDGPU] do not generate .AMDGPU.config for amdpal os type
Summary:
Now we generate PAL metadata for the amdpal os type, there is no need to
generate the .AMDGPU.config section.
Reviewers: arsenm, nhaehnle, dstuttard
Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D37760
Change-Id: I303c5fad66656ce97293da60621afac6595b4c18
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324346
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Sander de Smalen [Tue, 6 Feb 2018 13:13:21 +0000 (13:13 +0000)]
[AArch64][SVE] Asm: Add AND_ZI instructions and aliases
Summary: Adds support for the SVE AND instruction with vector and logical-immediate operands, and their corresponding aliases.
Reviewers: fhahn, rengolin, samparker, echristo, aadg, kristof.beyls
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D42295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324343
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Clement Courbet [Tue, 6 Feb 2018 12:25:33 +0000 (12:25 +0000)]
[MergeICmps] Handle chains with several complex BCE basic blocks.
- Fix condition for detecting that a complex basic block was the first in
the chain.
- Add tests.
This was caught by buildbots when submitting rL324319.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324341
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Simon Pilgrim [Tue, 6 Feb 2018 12:16:10 +0000 (12:16 +0000)]
[X86][SSE] Add PACKSS support for truncation of clamped values
Followup to D42544 that matches PACKSSWB cases for non-AVX512, SSE and PACKSSDW cases will have to wait until we can add support for general SMIN/SMAX matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324339
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Hiroshi Inoue [Tue, 6 Feb 2018 11:34:16 +0000 (11:34 +0000)]
[PowerPC] fix up in rL324229, NFC
This patch fixes up my previous commit (add initialization of local variables).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324336
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Petar Jovanovic [Tue, 6 Feb 2018 11:11:28 +0000 (11:11 +0000)]
[DeadArgumentElim] Set pointer to DISubprogram before calling RAUW. NFC
It is better to update pointer of the DISuprogram before we call RAUW for
still live arguments of the function, because with the change reviewed in
D42541 in RAUW we compare DISubprograms rather than functions itself.
Patch by Djordje Todorovic.
Differential Revision: https://reviews.llvm.org/D42794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324335
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Alexander Ivchenko [Tue, 6 Feb 2018 09:53:02 +0000 (09:53 +0000)]
Fix unused variable warning in release mode. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324330
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Oliver Stannard [Tue, 6 Feb 2018 09:39:04 +0000 (09:39 +0000)]
[AArch64] Fix spelling of ICH_ELRSR_EL2 system register
This register was mis-spelled as ICH_ELSR_EL2, but has the correct encoding for
ICH_ELRSR_EL2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324325
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Oliver Stannard [Tue, 6 Feb 2018 09:24:47 +0000 (09:24 +0000)]
[ARM][AArch64] Add CSDB speculation barrier instruction
This adds the CSDB instruction, which is a new barrier instruction
described by the whitepaper at [1].
This is in encoding space which was previously executed as a NOP, so it is
available for all targets that have the relevant NOP encoding space. This
matches the binutils behaviour for these instructions [2][3].
[1] https://developer.arm.com/support/security-update
[2] https://sourceware.org/ml/binutils/2018-01/msg00116.html
[3] https://sourceware.org/ml/binutils/2018-01/msg00120.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324324
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Clement Courbet [Tue, 6 Feb 2018 09:14:00 +0000 (09:14 +0000)]
[MergeICmps][NFC] Add more assertions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324323
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Sjoerd Meijer [Tue, 6 Feb 2018 08:43:56 +0000 (08:43 +0000)]
[ARM] Armv8.2-A FP16 code generation (part 3/3)
This adds most of the FP16 codegen support, but these areas need further work:
- FP16 literals and immediates are not properly supported yet (e.g. literal
pool needs work),
- Instructions that are generated from intrinsics (e.g. vabs) haven't been
added.
This will be addressed in follow-up patches.
Differential Revision: https://reviews.llvm.org/D42849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324321
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Clement Courbet [Tue, 6 Feb 2018 08:40:18 +0000 (08:40 +0000)]
Revert "[MergeICmps] Enable the MergeICmps Pass by default."
Breaks clang-ppc64be-linux-multistage buildbot.
This reverts commit
515bab711f308c2e8299c49dd8c84ea6a2e0b60e.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324319
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Clement Courbet [Tue, 6 Feb 2018 07:20:33 +0000 (07:20 +0000)]
[MergeICmps] Enable the MergeICmps Pass by default.
Summary: Now that PR33325 is fixed, this should always improve the generated code.
Reviewers: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324317
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Hiroshi Inoue [Tue, 6 Feb 2018 07:03:09 +0000 (07:03 +0000)]
[ThinLTO] fix test failure without x86 backend
This patch moves ThinLTOBitcodeWriter/module-asm.ll test case into x86 directory to avoid a test failure when x86 backend is not enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324316
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Craig Topper [Tue, 6 Feb 2018 06:44:05 +0000 (06:44 +0000)]
[X86] Modify a few tests to not use icmps that are provably false.
These used things like unsigned less than zero, which is always false because there is no unsigned number less than zero.
I plan to teach DAG combine to optimize these so need to stop using them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324315
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Konstantin Zhuravlyov [Tue, 6 Feb 2018 04:06:04 +0000 (04:06 +0000)]
AMDGPU/MemoryModel: Fix monotonic atomic loads
Those should have glc bit set for system and agent synchronization scopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324314
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Peter Collingbourne [Tue, 6 Feb 2018 03:29:18 +0000 (03:29 +0000)]
ThinLTOBitcodeWriter: Do not include module-level inline asm in the merged module.
If the inline asm provides the definition of a symbol, this can result
in duplicate symbol errors.
Differential Revision: https://reviews.llvm.org/D42944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324313
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