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Diana Picus [Fri, 12 Jan 2018 11:30:45 +0000 (11:30 +0000)]
[ARM GlobalISel] Legalize G_FMA
For hard float with VFP4, it is legal. Otherwise, we use libcalls.
This needs a bit of support in the LegalizerHelper for soft float
because we didn't handle G_FMA libcalls yet. The support is trivial, as
the only difference between G_FMA and other libcalls that we already
handle is that it has 3 input operands rather than just 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322366
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Max Kazantsev [Fri, 12 Jan 2018 10:00:26 +0000 (10:00 +0000)]
[IRCE][NFC] Make range check's End a non-null SCEV
Currently, IRC contains `Begin` and `Step` as SCEVs and `End` as value.
Aside from that, `End` can also be `nullptr` which can be later conditionally
converted into a non-null SCEV.
To make this logic more transparent, this patch makes `End` a SCEV and
calculates it early, so that it is never a null.
Differential Revision: https://reviews.llvm.org/D39590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322364
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Andre Vieira [Fri, 12 Jan 2018 09:24:41 +0000 (09:24 +0000)]
[ARM] Add codegen for SMMULR, SMMLAR and SMMLSR
This patch teaches the Arm back-end to generate the SMMULR, SMMLAR and SMMLSR
instructions from equivalent IR patterns.
Differential Revision: https://reviews.llvm.org/D41775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322361
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Andre Vieira [Fri, 12 Jan 2018 09:21:09 +0000 (09:21 +0000)]
[ARM] Fix erroneous availability of SMMLS for Armv7-M
Differential Revision: https://reviews.llvm.org/D41855
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322360
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Serguei Katkov [Fri, 12 Jan 2018 08:33:34 +0000 (08:33 +0000)]
[CGP] Re-enable Select in complex addressing mode
Re-enable Select after a couple of fixes.
Differential Revision: https://reviews.llvm.org/D40634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322358
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Serguei Katkov [Fri, 12 Jan 2018 07:24:43 +0000 (07:24 +0000)]
[LoopDeletion] Handle users in unreachable block
This is a fix for PR35884.
When we want to delete dead loop we must clean uses in unreachable blocks
otherwise we'll get an assert during deletion of instructions from the loop.
Reviewers: anna, davide
Reviewed By: anna
Subscribers: llvm-commits, lebedev.ri
Differential Revision: https://reviews.llvm.org/D41943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322357
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Craig Topper [Fri, 12 Jan 2018 06:48:26 +0000 (06:48 +0000)]
[X86] Don't allow lods/stos/scas/cmps/movs to be parsed without a suffix and only memory operand in at&t syntax.
Without a register with a size being mentioned the instruction is ambiguous in at&t syntax. With Intel syntax the memory operation caries a size that can be used to disambiguate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322356
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Craig Topper [Fri, 12 Jan 2018 06:48:24 +0000 (06:48 +0000)]
[X86] Don't require suffix on 'clr' mnemonic in intel syntax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322355
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Craig Topper [Fri, 12 Jan 2018 06:21:36 +0000 (06:21 +0000)]
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.
While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322354
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Craig Topper [Fri, 12 Jan 2018 05:38:15 +0000 (05:38 +0000)]
[X86] Disable sldtq parsing in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322353
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Craig Topper [Fri, 12 Jan 2018 05:38:14 +0000 (05:38 +0000)]
[X86] Disable movsq/stosq/scasqcmpsq/lodsq parsing in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322352
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Eric Fiselier [Fri, 12 Jan 2018 04:01:41 +0000 (04:01 +0000)]
[CMake] Add LLVM_ENABLE_IDE option to better process sources for IDE's
Summary:
Currently LLVM has no way to support configuring for IDE's like CLion. Like XCode and MSVC's IDE, CLion needs to see all of the headers and tablegen files in order to properly parse the sources.
This patch adds an `LLVM_ENABLE_IDE` option which can be used to configure for IDE's in general. It is used by `LLVMProcessSources.cmake` to determine if the extra source files should be added to the target.
Unfortunately because of the low level of `LLVMProcessSources.cmake`, I'm not sure where the `LLVM_ENABLE_IDE` option should live. I choose `HandleLLVMOptions.cmake` so that out-of-tree Clang builds would correctly configure the option by default.
Reviewers: beanz, mgorny, lebedev.ri
Reviewed By: beanz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322349
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Rui Ueyama [Fri, 12 Jan 2018 02:28:31 +0000 (02:28 +0000)]
Instead of ELFFile<ELFT>::Type, use ELFT::Type. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322346
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Ana Pazos [Fri, 12 Jan 2018 02:27:00 +0000 (02:27 +0000)]
[RISCV] Pass MCSubtargetInfo to print methods.
Summary:
This change allows checking for ISA extensions in print methods.
Reviewers: asb, niosHD
Reviewed By: asb, niosHD
Subscribers: llvm-commits, niosHD, asb, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal
Differential Revision: https://reviews.llvm.org/D41503
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322345
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Rui Ueyama [Fri, 12 Jan 2018 02:15:41 +0000 (02:15 +0000)]
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322344
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Sam Clegg [Fri, 12 Jan 2018 02:11:31 +0000 (02:11 +0000)]
[WebAssembly] Don't allow functions to be named twice
The spec doesn't allow this.
Differential Revision: https://reviews.llvm.org/D41974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322343
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Rui Ueyama [Fri, 12 Jan 2018 01:40:32 +0000 (01:40 +0000)]
Use ELF{32,64}{LE,BE} instead of ELFType<{little,big}, {true,false}>. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322342
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Lang Hames [Fri, 12 Jan 2018 00:22:05 +0000 (00:22 +0000)]
[ORC] Add a stub ExecutionSession and VModuleKey type.
ExecutionSession will represent a running JIT program.
VModuleKey is a unique key assigned to each module added as part of
an ExecutionSession. The Layer concept will be updated in future to
require a VModuleKey when a module is added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322336
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David L. Jones [Fri, 12 Jan 2018 00:17:38 +0000 (00:17 +0000)]
Revert r322279 due to Skylake miscompile.
Summary:
This revision causes Skylake (and apparently, only Skylake) codegen to fail in
certain cases. Details: https://bugs.llvm.org/show_bug.cgi?id=35918
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D41972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322335
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Sam Clegg [Thu, 11 Jan 2018 23:59:16 +0000 (23:59 +0000)]
[WebAssembly] MC: Remove SetUsed argument when calling MCSymbol::isDefined et al
Summary:
This argument (the isUsed flag) seems to only be relevant
when parsing. Other calls sites such as these don't seem
to ever use it.
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish
Differential Revision: https://reviews.llvm.org/D41970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322332
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Sanjay Patel [Thu, 11 Jan 2018 23:27:37 +0000 (23:27 +0000)]
[InstSimplify] fold implied cmp with zero (PR35790)
This doesn't handle the more complicated case in the bug report yet:
https://bugs.llvm.org/show_bug.cgi?id=35790
For that, we have to match / look through a cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322327
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Matthias Braun [Thu, 11 Jan 2018 22:59:33 +0000 (22:59 +0000)]
PeepholeOpt cleanup/refactor; NFC
- Less unnecessary use of `auto`
- Add early `using RegSubRegPair(AndIdx) =` to avoid countless
`TargetInstrInfo::` qualifications.
- Use references instead of pointers where possible.
- Remove unused parameters.
- Rewrite the CopyRewriter class hierarchy:
- Pull out uncoalescable copy rewriting functionality into
PeepholeOptimizer class.
- Use an abstract base class to make it clear that rewriters are
independent.
- Remove unnecessary \brief in doxygen comments.
- Remove unused constructor and method from ValueTracker.
- Replace UseAdvancedTracking of ValueTracker with DisableAdvCopyOpt use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322325
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Evgeniy Stepanov [Thu, 11 Jan 2018 22:53:30 +0000 (22:53 +0000)]
[hwasan] Stack instrumentation.
Summary:
Very basic stack instrumentation using tagged pointers.
Tag for N'th alloca in a function is built as XOR of:
* base tag for the function, which is just some bits of SP (poor
man's random)
* small constant which is a function of N.
Allocas are aligned to 16 bytes. On every ReturnInst allocas are
re-tagged to catch use-after-return.
This implementation has a bunch of issues that will be taken care of
later:
1. lifetime intrinsics referring to tagged pointers are not
recognized in SDAG. This effectively disables stack coloring.
2. Generated code is quite inefficient. There is one extra
instruction at each memory access that adds the base tag to the
untagged alloca address. It would be better to keep tagged SP in a
callee-saved register and address allocas as an offset of that XOR
retag, but that needs better coordination between hwasan
instrumentation pass and prologue/epilogue insertion.
3. Lifetime instrinsics are ignored and use-after-scope is not
implemented. This would be harder to do than in ASan, because we
need to use a differently tagged pointer depending on which
lifetime.start / lifetime.end the current instruction is dominated
/ post-dominated.
Reviewers: kcc, alekseyshl
Subscribers: srhines, kubamracek, javed.absar, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322324
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Sanjay Patel [Thu, 11 Jan 2018 22:48:07 +0000 (22:48 +0000)]
[InstSimplify] add tests for implied cmp with zero (PR35790); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322323
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Matthias Braun [Thu, 11 Jan 2018 22:30:43 +0000 (22:30 +0000)]
PeepholeOptimizer: Fix for vregs without defs
The PeepholeOptimizer would fail for vregs without a definition. If this
was caused by an undef operand abort to keep the code simple (so we
don't need to add logic everywhere to replicate the undef flag).
Differential Revision: https://reviews.llvm.org/D40763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322319
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Rafael Espindola [Thu, 11 Jan 2018 22:15:05 +0000 (22:15 +0000)]
Make internal/private GVs implicitly dso_local.
While updating clang tests for having clang set dso_local I noticed
that:
- There are *a lot* of tests to update.
- Many of the updates are redundant.
They are redundant because a GV is "obviously dso_local". This patch
starts formalizing that a bit by requiring that internal and private
GVs be dso_local too. Since they all are, we don't have to print
dso_local to the textual representation, making it a bit more compact
and easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322317
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Paul Robinson [Thu, 11 Jan 2018 22:03:43 +0000 (22:03 +0000)]
Tighten up DIFile verifier for checksums
Differential Revision: https://reviews.llvm.org/D41965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322314
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Matthias Braun [Thu, 11 Jan 2018 21:57:03 +0000 (21:57 +0000)]
PeepholeOptimizer: Do not form PHI with subreg arguments
When replacing a PHI the PeepholeOptimizer currently takes the register
class of the register at the first operand. This however is not correct
if this argument has a subregister index.
As there is currently no API to query the register class resulting from
applying a subregister index to all registers in a class, we can only
abort in these cases and not perform the transformation.
This changes findNextSource() to require the end of all copy chains to
not use a subregister if there is any PHI in the chain. I had to rewrite
the overly complicated inner loop there to have a good place to insert
the new check.
This fixes https://llvm.org/PR33071 (aka rdar://
32262041)
Differential Revision: https://reviews.llvm.org/D40758
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322313
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Evgeniy Stepanov [Thu, 11 Jan 2018 21:37:58 +0000 (21:37 +0000)]
[arm] Implement Target Operand Flag MIR serialization.
Reviewers: efriedma, pcc
Subscribers: aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D39975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322312
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Fiona Glaser [Thu, 11 Jan 2018 21:28:57 +0000 (21:28 +0000)]
[Sink] Really really fix predicate in legality check
LoadInst isn't enough; we need to include intrinsics that perform loads too.
All side-effecting intrinsics and such are already covered by the isSafe
check, so we just need to care about things that read from memory.
D41960, originally from D33179.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322311
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Sam Clegg [Thu, 11 Jan 2018 20:35:17 +0000 (20:35 +0000)]
[WebAssemlby] MC: Don't write COMDAT symbols as global imports
This was causing undefined references at link time in lld.
Differential Revision: https://reviews.llvm.org/D41959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322309
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Craig Topper [Thu, 11 Jan 2018 19:38:30 +0000 (19:38 +0000)]
[X86] Legalize 128/256 gathers/scatters on KNL by using widening rather than sign extending the index.
We can just widen the vectors with undef and zero extend the mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322308
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Sam Clegg [Thu, 11 Jan 2018 19:37:03 +0000 (19:37 +0000)]
[WebAssemly] Rename and improve formatting for ctor/dtor test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322307
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Aaron Ballman [Thu, 11 Jan 2018 18:47:15 +0000 (18:47 +0000)]
Use size_t to represent the size of a StringMapEntry length and alignment rather than unsigned.
Patch by Matt Davis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322305
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Adrian Prantl [Thu, 11 Jan 2018 18:35:12 +0000 (18:35 +0000)]
dag-combine: Transfer debug information when folding (zext (truncate x))
-> (zext (truncate x))
This patch adds debug info support to the dagcombine rule (zext
(truncate x)) -> (zext (truncate x)).
Differential Revision: https://reviews.llvm.org/D41924
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322304
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Krzysztof Parzyszek [Thu, 11 Jan 2018 18:30:41 +0000 (18:30 +0000)]
[Hexagon] Fix building 64-bit vector from constant values
The constants were aggregated in a reverse order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322303
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Krzysztof Parzyszek [Thu, 11 Jan 2018 18:03:23 +0000 (18:03 +0000)]
[Hexagon] Cast elements to correct type when creating constant vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322301
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Zvi Rackover [Thu, 11 Jan 2018 18:02:33 +0000 (18:02 +0000)]
DAGCombine: Let truncates negate extension through extract-subvector
Summary:
Fold cases such as:
(v8i8 truncate (v8i32 extract_subvector (v16i32 sext (v16i8 V), Idx)))
->
(v8i8 extract_subvector (v16i8 V), Idx)
This can be generalized to cases where the truncate and extend do not
fully cancel each other out, but it may require querying the target
about profitability.
Reviewers: RKSimon, craig.topper, spatel, efriedma
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322300
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Krzysztof Parzyszek [Thu, 11 Jan 2018 18:02:13 +0000 (18:02 +0000)]
[Hexagon] Impose limits on container sizes in HexagonGenInsert
With over 300k virtual registers, the size of the data exceeded 12GB.
Impose limits on how much information is collected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322299
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Krzysztof Parzyszek [Thu, 11 Jan 2018 17:59:34 +0000 (17:59 +0000)]
[Hexagon] Use SetVector when queuing nodes to scan in selectVectorConstants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322298
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Zvi Rackover [Thu, 11 Jan 2018 17:50:34 +0000 (17:50 +0000)]
X86 Tests: Add zext cases in (trunc (subvector)) test. NFC
Cases were missing as observed in D41927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322297
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Zvi Rackover [Thu, 11 Jan 2018 17:29:47 +0000 (17:29 +0000)]
X86: Refactor type-splitting to target-legal size vector to a helper function
Summary: This is a preparatory step for D41811: refactoring code for breaking vector operands of binary operation to legal-types.
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41925
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322296
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Simon Pilgrim [Thu, 11 Jan 2018 16:57:58 +0000 (16:57 +0000)]
[X86][SSE] Drop old insertps stack folding test
Broken test from old attempt for folding tables - we don't peek through extract_subvector spills at all (which is why it doesn't fold), and we already have foldMemoryOperandCustom to handle insertps immediate correction anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322292
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Joel Jones [Thu, 11 Jan 2018 16:50:56 +0000 (16:50 +0000)]
[AArch64] Remove Unsupported = 1 flag for the WriteAtomic WriteRes.
In practice, this patch has no effect on scheduling.
There is no test case as there already exists a comprehensive test case for
LSE Atomics.
Patch by Stefan Teleman
Differential Revision: https://reviews.llvm.org/D40694
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322291
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Ben Hamilton [Thu, 11 Jan 2018 16:30:08 +0000 (16:30 +0000)]
[docs] Update Phabricator docs about setting repository for diffs uploaded via web
Summary:
Docs are out of date now that we have separate repositories for LLVM,
Clang, etc.
Reviewers: asb
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D41919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322290
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Daniel Neilson [Thu, 11 Jan 2018 16:28:32 +0000 (16:28 +0000)]
[NFC] Abstract out source argument index in MemTransferInst.
Summary:
References to the source operand within class MemTransferInst are currently
by a constant 1. Abstract this out into a named constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322289
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Benjamin Kramer [Thu, 11 Jan 2018 15:33:21 +0000 (15:33 +0000)]
[InstCombine] Apply the fix from r322284 for sin / cos -> tan too
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322285
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Benjamin Kramer [Thu, 11 Jan 2018 15:19:02 +0000 (15:19 +0000)]
[InstCombine] For cos/sin -> tan copy attributes from cos instead of the
parent function
Ideally we should merge the attributes from the functions somehow, but
this is obviously an improvement over taking random attributes from the
caller which will trip up the verifier if they're nonsensical for an
unary intrinsic call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322284
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Sanjay Patel [Thu, 11 Jan 2018 15:13:47 +0000 (15:13 +0000)]
[ValueTracking] recognize min/max-of-min/max with notted ops (PR35875)
This was originally planned as the fix for:
https://bugs.llvm.org/show_bug.cgi?id=35834
...but simpler transforms handled that case, so I implemented a
lesser solution. It turns out we need to handle the case with 'not'
ops too because the real code example that we are trying to solve:
https://bugs.llvm.org/show_bug.cgi?id=35875
...has extra uses of the intermediate values, so we can't rely on
smaller canonicalizations to get us to the goal.
As with rL321672, I've tried to show every possibility in the
codegen tests because that's the simplest way to prove we're doing
the right thing in the wide variety of permutations of this pattern.
We can also show an InstCombine win because we added a fold for
this case in:
rL321998 / D41603
An Alive proof for one variant of the pattern to show that the
InstCombine and codegen results are correct:
https://rise4fun.com/Alive/vd1
Name: min3_nots
%nx = xor i8 %x, -1
%ny = xor i8 %y, -1
%nz = xor i8 %z, -1
%cmpxz = icmp slt i8 %nx, %nz
%minxz = select i1 %cmpxz, i8 %nx, i8 %nz
%cmpyz = icmp slt i8 %ny, %nz
%minyz = select i1 %cmpyz, i8 %ny, i8 %nz
%cmpyx = icmp slt i8 %y, %x
%r = select i1 %cmpyx, i8 %minxz, i8 %minyz
=>
%cmpxyz = icmp slt i8 %minxz, %ny
%r = select i1 %cmpxyz, i8 %minxz, i8 %ny
Name: min3_nots_alt
%nx = xor i8 %x, -1
%ny = xor i8 %y, -1
%nz = xor i8 %z, -1
%cmpxz = icmp slt i8 %nx, %nz
%minxz = select i1 %cmpxz, i8 %nx, i8 %nz
%cmpyz = icmp slt i8 %ny, %nz
%minyz = select i1 %cmpyz, i8 %ny, i8 %nz
%cmpyx = icmp slt i8 %y, %x
%r = select i1 %cmpyx, i8 %minxz, i8 %minyz
=>
%xz = icmp sgt i8 %x, %z
%maxxz = select i1 %xz, i8 %x, i8 %z
%xyz = icmp sgt i8 %maxxz, %y
%maxxyz = select i1 %xyz, i8 %maxxz, i8 %y
%r = xor i8 %maxxyz, -1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322283
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Sanjay Patel [Thu, 11 Jan 2018 14:53:45 +0000 (14:53 +0000)]
[InstCombine] add min3-with-nots test (PR35875); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322281
91177308-0d34-0410-b5e6-
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Igor Laevsky [Thu, 11 Jan 2018 14:43:05 +0000 (14:43 +0000)]
[FuzzMutate] Avoid using swifterror as a source operand
Differential Revision: https://reviews.llvm.org/D41107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322280
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Simon Pilgrim [Thu, 11 Jan 2018 14:25:18 +0000 (14:25 +0000)]
[X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decoding
Primarily, this allows us to use the aggressive extraction mechanisms in combineExtractWithShuffle earlier and make use of UNDEF elements that may be lost during lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322279
91177308-0d34-0410-b5e6-
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Jonas Paulsson [Thu, 11 Jan 2018 13:03:21 +0000 (13:03 +0000)]
[VectorLegalizer] Remove broken code in ExpandStore.
The code that is supposed to "Round odd types to the next pow of two" seems
broken and as well completely unused (untested). It also seems that
ExpandStore really shouldn't ever change the memory VT, which this in fact
does.
As a first step in fixing the broken handling of vector stores (of irregular
types, e.g. an i1 vector), this code is removed. For discussion, see
https://bugs.llvm.org/show_bug.cgi?id=35520.
Review: Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322275
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Zvi Rackover [Thu, 11 Jan 2018 12:26:52 +0000 (12:26 +0000)]
X86: Fix LowerBUILD_VECTORAsVariablePermute for case Src is smaller than Indices
Summary:
As RKSimon suggested in pr35820, in the case that Src is smaller in
bit-size than Indices, need to widen Src to avoid type mismatch.
Fixes pr35820
Reviewers: RKSimon, craig.topper
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41865
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322272
91177308-0d34-0410-b5e6-
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Alex Bradbury [Thu, 11 Jan 2018 11:17:19 +0000 (11:17 +0000)]
[RISCV] Reserve an emergency spill slot for the register scavenger when necessary
Although the register scavenger can often find a spare register, an emergency
spill slot is needed to guarantee success. Reserve this slot in cases where
the function is known to have a large stack (meaning the scavenger may be
needed when forming stack addresses).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322269
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Andrew V. Tischenko [Thu, 11 Jan 2018 10:31:01 +0000 (10:31 +0000)]
Implementation of X86Operand::print.
Differential Revision: https://reviews.llvm.org/D41610
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322267
91177308-0d34-0410-b5e6-
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Stefan Maksimovic [Thu, 11 Jan 2018 10:07:47 +0000 (10:07 +0000)]
[Mips] Handle one byte unsupported relocations
Fail gracefully instead of crashing upon encountering
this type of relocation.
Differential revision: https://reviews.llvm.org/D41857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322266
91177308-0d34-0410-b5e6-
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Sander de Smalen [Thu, 11 Jan 2018 10:02:27 +0000 (10:02 +0000)]
[AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraints
Summary: Patch [3/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.
Reviewers: rengolin, mcrosier, evandro, fhahn, echristo
Reviewed By: rengolin, fhahn
Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322265
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 11 Jan 2018 07:19:29 +0000 (07:19 +0000)]
[X86] Fix unused variable in release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322262
91177308-0d34-0410-b5e6-
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Aaron Smith [Thu, 11 Jan 2018 06:42:11 +0000 (06:42 +0000)]
[CodeView] Fix the type for a variadic argument
Summary:
- MSVC uses the none type for a variadic argument in CodeView
- Add a unit test
Reviewers: zturner, llvm-commits
Reviewed By: zturner
Differential Revision: https://reviews.llvm.org/D41931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322257
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Dmitry Venikov [Thu, 11 Jan 2018 06:33:00 +0000 (06:33 +0000)]
[InstCombine] Missed optimization in math expression: sin(x) / cos(x) => tan(x)
Summary: This patch enables folding sin(x) / cos(x) -> tan(x), cos(x) / sin(x) -> 1 / tan(x) under -ffast-math flag
Reviewers: hfinkel, spatel
Reviewed By: spatel
Subscribers: andrew.w.kaylor, efriedma, scanon, llvm-commits
Differential Revision: https://reviews.llvm.org/D41286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322255
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Craig Topper [Thu, 11 Jan 2018 06:31:28 +0000 (06:31 +0000)]
[X86] Optimize v2i32/v2f32 scatters.
If the index is v2i64 we can use the scatter instruction that has v4i32/v4f32 data register, v2i64 index, and v2i1 mask. Similar was already done for gather.
Implement custom widening for v2i32 data to remove the code that reverses type legalization during lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322254
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Wolfgang Pieb [Thu, 11 Jan 2018 02:35:00 +0000 (02:35 +0000)]
[DWARF][NFC] Overload AsmPrinter::emitDwarfStringOffsets() to take a DwarfStringPoolEntry
record.
Differential Revision: https://reviews.llvm.org/D41920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322250
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Marcello Maggioni [Thu, 11 Jan 2018 02:06:28 +0000 (02:06 +0000)]
[NFC] Commit to mention that r322248 is actually made by AndrewScheidecker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322249
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Marcello Maggioni [Thu, 11 Jan 2018 02:01:16 +0000 (02:01 +0000)]
[SimplifyCFG] Add cut-off for InitializeUniqueCases.
The function can take a significant amount of time on some
complicated test cases, but for the currently only use of
the function we can stop the initialization much earlier
when we find out we are going to discard the result anyway
in the caller of the function.
Adding configurable cut-off points so that we avoid wasting time.
NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322248
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Matt Morehouse [Wed, 10 Jan 2018 23:53:11 +0000 (23:53 +0000)]
SmallVector: fix use-after-poison MSAN error in destructor
Summary:
Addresses issue: https://bugs.llvm.org/show_bug.cgi?id=34595
The topmost class, `SmallVector`, has internal storage for some
elements; `N - 1` elements' bytes worth of space. Meanwhile a base
class `SmallVectorTemplateCommon` has room for one element as well,
totaling `N` elements' worth of space.
The space for the N elements is contiguous and straddles
`SmallVectorTemplateCommon` and `SmallVector`.
A class "between" those two owning the storage, `SmallVectorImpl`, in
its destructor, calls the destructor for elements contained in the
vector, if any. It uses `destroy_range(begin, end)` and deletes all
items in sequence, starting from the end.
By the time the destructor for `SmallVectorImpl` is running, though, the
memory for elements `[1, N)` is already poisoned, due to `SmallVector`'s
destructor having done its thing already.
So if the element type `T` has a nontrivial destructor that accesses any
members of the `T` instance being destroyed, we'll run into a
user-after-poison bug.
This patch moves the destruction loop into `SmallVector`'s destructor,
so any memory being accessed while dtors are running is not yet
poisoned.
Confirmed this broke before (and now works with this patch) with these
compiler flags:
-fsanitize=memory
-fsanitize-memory-use-after-dtor
-fsanitize-memory-track-origins
and with the cmake flag
`-DLLVM_USE_SANITIZER='MemoryWithOrigins;Undefined'` as well as
`MSAN_OPTIONS=poison_in_dtor=1`.
Patch By: elsteveogrande
Reviewers: eugenis, morehouse, dblaikie
Reviewed By: eugenis, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322241
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Sanjay Patel [Wed, 10 Jan 2018 23:31:42 +0000 (23:31 +0000)]
[AArch64] add tests for notted variants of min/max; NFC
Like rL321668 / rL321672, the planned optimizer change to
fix these will be in ValueTracking, but we can test the
changes cleanly here with AArch64 codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322238
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Matthias Braun [Wed, 10 Jan 2018 22:36:28 +0000 (22:36 +0000)]
Revert "AArch64: Fix emergency spillslot being out of reach for large callframes"
Revert for now as the testcase is hitting a pre-existing verifier error
that manifest as a failure when expensive checks are enabled (or
-verify-machineinstrs) is used.
This reverts commit r322200.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322231
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Matthias Braun [Wed, 10 Jan 2018 22:36:26 +0000 (22:36 +0000)]
LiveRangeEdit: Inline markDeadRemat() into only user; NFC
This function was only called from a single place in which we didn't
even need the `if (DeadRemats)` check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322230
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Craig Topper [Wed, 10 Jan 2018 22:07:16 +0000 (22:07 +0000)]
[X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through the MCAsmBackend constructor
After D41349, we can no get a MCSubtargetInfo into the MCAsmBackend constructor. This allows us to get NOPL from a subtarget feature rather than a CPU name blacklist.
Differential Revision: https://reviews.llvm.org/D41721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322227
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Matthias Braun [Wed, 10 Jan 2018 21:41:02 +0000 (21:41 +0000)]
LiveRangeEdit: Simplify code; NFC
Simplify the code slightly: Instead of creating empty subranges in one
case and immediately removing them, do not create them in the first
place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322226
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Alexey Bataev [Wed, 10 Jan 2018 21:29:18 +0000 (21:29 +0000)]
[SLP] Add/update tests for SLP vectorizer, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322225
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Alex Bradbury [Wed, 10 Jan 2018 21:05:07 +0000 (21:05 +0000)]
[RISCV] Implement support for the BranchRelaxation pass
Branch relaxation is needed to support branch displacements that overflow the
instruction's immediate field.
Differential Revision: https://reviews.llvm.org/D40830
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322224
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Matthias Braun [Wed, 10 Jan 2018 20:49:57 +0000 (20:49 +0000)]
TargetLoweringBase: The ios simulator has no bzero function.
Make sure I really get back to the beahvior before my rewrite in r321035
which turned out not to be completely NFC as I changed the behavior for
the ios simulator environment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322223
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Alex Bradbury [Wed, 10 Jan 2018 20:47:00 +0000 (20:47 +0000)]
[RISCV] Implement branch analysis
This is a prerequisite for the branch relaxation pass, and allows a number of
optimisation passes (e.g. BranchFolding and MachineBlockPlacement) to work.
Differential Revision: https://reviews.llvm.org/D40808
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322222
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Alex Bradbury [Wed, 10 Jan 2018 20:12:00 +0000 (20:12 +0000)]
[RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322218
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Alex Bradbury [Wed, 10 Jan 2018 20:05:09 +0000 (20:05 +0000)]
[RISCV] Add basic support for inline asm constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322217
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Alex Bradbury [Wed, 10 Jan 2018 19:53:46 +0000 (19:53 +0000)]
[RISCV] Support stack frames and offsets up to 32-bits
Differential Revision: https://reviews.llvm.org/D40807
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322216
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Alex Bradbury [Wed, 10 Jan 2018 19:41:03 +0000 (19:41 +0000)]
[RISCV] Support for varargs
Includes support for expanding va_copy. Also adds support for using 'aligned'
registers when necessary for vararg calls, and ensure the frame pointer always
points to the bottom of the vararg spill region. This is necessary to ensure
that the saved return address and stack pointer are always available at fixed
known offsets of the frame pointer.
Differential Revision: https://reviews.llvm.org/D40805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322215
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Scott Linder [Wed, 10 Jan 2018 19:27:20 +0000 (19:27 +0000)]
Test commit access
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322213
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Craig Topper [Wed, 10 Jan 2018 19:16:05 +0000 (19:16 +0000)]
[SelectionDAG][X86] Explicitly store the scale in the gather/scatter ISD nodes
Currently we infer the scale at isel time by analyzing whether the base is a constant 0 or not. If it is we assume scale is 1, else we take it from the element size of the pass thru or stored value. This seems a little weird and I think it makes more sense to make it explicit in the DAG rather than doing tricky things in the backend.
Most of this patch is just making sure we copy the scale around everywhere.
Differential Revision: https://reviews.llvm.org/D40055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322210
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Jessica Paquette [Wed, 10 Jan 2018 18:49:57 +0000 (18:49 +0000)]
[MachineOutliner] Outline ADRPs
ADRP instructions weren't being outlined because they're PC-relative and thus
fail the LR checks. This patch adds a special case for ADRPs to
getOutliningType to make sure that ADRPs can be outlined and updates the MIR
test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322207
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Sanjay Patel [Wed, 10 Jan 2018 18:47:21 +0000 (18:47 +0000)]
[InstCombine] add test to show missed bswap; NFC
D41353 / D41233 are proposing to alter the shl/and canonicalization,
but I think that would just move an existing pattern-matching hole
to a different place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322206
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Matthias Braun [Wed, 10 Jan 2018 18:16:24 +0000 (18:16 +0000)]
AArch64: Fix emergency spillslot being out of reach for large callframes
Large callframes (calls with several hundreds or thousands or
parameters) could lead to situations in which the emergency spillslot is
out of range to be addressed relative to the stack pointer.
This commit forces the use of a frame pointer in the presence of large
callframes.
This commit does several things:
- Compute max callframe size at the end of instruction selection.
- Add mirFileLoaded target callback. Use it to compute the max callframe size
after loading a .mir file when the size wasn't specified in the file.
- Let TargetFrameLowering::hasFP() return true if there exists a
callframe > 255 bytes.
- Always place the emergency spillslot close to FP if we have a frame
pointer.
- Note that `useFPForScavengingIndex()` would previously return false
when a base pointer was available leading to the emergency spillslot
getting allocated late (that's the whole effect of this callback).
Which made no sense to me so I took this case out: Even though the
emergency spillslot is technically not referenced by FP in this case
we still want it allocated early.
Differential Revision: https://reviews.llvm.org/D40876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322200
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Francis Visoiu Mistrih [Wed, 10 Jan 2018 17:53:16 +0000 (17:53 +0000)]
[MIR] Update MIRLangRef with documentation on bundled instructions
Differential Revision: https://reviews.llvm.org/D41872
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322198
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Simon Pilgrim [Wed, 10 Jan 2018 17:05:03 +0000 (17:05 +0000)]
[X86][MMX] Add test for PR35869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322197
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Simon Pilgrim [Wed, 10 Jan 2018 15:32:19 +0000 (15:32 +0000)]
[X86][MMX] Pull out common MMX VT test. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322195
91177308-0d34-0410-b5e6-
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Zvi Rackover [Wed, 10 Jan 2018 14:56:15 +0000 (14:56 +0000)]
X86 Tests: Add isel tests for truncate-extract_vector-extend. NFC.
To be improved in a future patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322192
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Dmitry Preobrazhensky [Wed, 10 Jan 2018 14:22:19 +0000 (14:22 +0000)]
[AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support
See bug 35764: https://bugs.llvm.org/show_bug.cgi?id=35764
Differential Revision: https://reviews.llvm.org/D41614
Reviewers: vpykhtin, artem.tamazov, arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322189
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Simon Pilgrim [Wed, 10 Jan 2018 13:52:30 +0000 (13:52 +0000)]
Fix -Wdocumentation warning by removing empty @brief. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322186
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 10 Jan 2018 13:28:34 +0000 (13:28 +0000)]
[X86][SSE] Add some basic FABS combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322182
91177308-0d34-0410-b5e6-
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Bjorn Pettersson [Wed, 10 Jan 2018 13:01:18 +0000 (13:01 +0000)]
Avoid inlining if there is byval arguments with non-alloca address space
Summary:
After teaching InlineCost more about address spaces ()
another fault was detected in the inliner. If an argument has
the byval attribute the parameter might be copied to an alloca.
That part seems to work fine even if the argument has a different
address space than the alloca address space. However, if the
address spaces differ, then the inlined function still might
refer to the parameter using the original address space (the
inliner does not handle that situation very well).
This patch avoids the problem by simply disallowing inlining
when there are byval arguments with address space that differs
from the alloca address space.
I'm not really sure how to transform the code if we want to
get inlining for this situation. I assume that it never has
been working, and that the fixes in r321809 just exposed an
old problem.
Fault found by skatkov (Serguei Katkov). It is mentioned in
follow up comments to https://reviews.llvm.org/D40455.
Reviewers: skatkov
Reviewed By: skatkov
Subscribers: uabelho, eraman, llvm-commits, haicheng
Differential Revision: https://reviews.llvm.org/D41898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322181
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 10 Jan 2018 12:23:39 +0000 (12:23 +0000)]
[X86][SSE] Add v2f64 u2 shuffle test
Adds missing coverage for SHUFPD undef argument lowering, and also shows a missed opportunity to remove a unnecessary move compared to 02 shuffle mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322175
91177308-0d34-0410-b5e6-
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Sander de Smalen [Wed, 10 Jan 2018 11:32:47 +0000 (11:32 +0000)]
[AArch64][SVE] Asm: Add support for (mov|dup) of scalar
Summary: This patch adds support for 'dup' (Scalar -> SVE) and its corresponding 'mov' alias.
Reviewers: fhahn, rengolin, evandro, echristo
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322172
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Diana Picus [Wed, 10 Jan 2018 11:13:36 +0000 (11:13 +0000)]
[ARM GlobalISel] Add inst selector tests for G_FNEG s32 and s64
G_FNEG is already handled by the TableGen'erated code. Just add a few
tests to make sure everything works as expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322170
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Diana Picus [Wed, 10 Jan 2018 11:13:31 +0000 (11:13 +0000)]
[ARM GlobalISel] Map G_FNEG to the FPR bank
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322169
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Diana Picus [Wed, 10 Jan 2018 10:45:34 +0000 (10:45 +0000)]
[ARM GlobalISel] Legalize G_FNEG for s32 and s64
For hard float, it is legal.
For soft float, we need to lower to 0 - x first, and then we can use the
libcall for G_FSUB. This is undoing some of the canonicalization
performed by the IRTranslator (which introduces G_FNEG when it sees a
0 - x). Ideally, that canonicalization would be performed by a
pre-legalizer pass that would allow targets to opt out of this behaviour
rather than dance around it in the legalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322168
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Sander de Smalen [Wed, 10 Jan 2018 10:10:56 +0000 (10:10 +0000)]
[TableGen][AsmMatcherEmitter] Generate assembler checks for tied operands
Summary:
This extends TableGen's AsmMatcherEmitter with code that generates
a table with tied-operand constraints. The constraints are checked
when parsing the instruction. If an operand is not equal to its tied operand,
the assembler will give an error.
Patch [2/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.
Reviewers: olista01, rengolin, mcrosier, fhahn, craig.topper, evandro, echristo
Reviewed By: fhahn
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D41446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322166
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Jonas Paulsson [Wed, 10 Jan 2018 10:05:55 +0000 (10:05 +0000)]
Temporarily revert
"[SystemZ] Check for legality before doing LOAD AND TEST transformations."
, due to test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322165
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Diana Picus [Wed, 10 Jan 2018 10:01:49 +0000 (10:01 +0000)]
[ARM GlobalISel] Legalize s32/s64 G_FCONSTANT
Legal for hard float.
Change to G_CONSTANT for soft float (but preserve the binary
representation).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322164
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