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Rafael Espindola [Thu, 22 Jun 2017 17:25:35 +0000 (17:25 +0000)]
Add a common error checking for some invalid expressions.
This refactors a bit of duplicated code and fixes an assertion failure
on ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306035
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David Stuttard [Thu, 22 Jun 2017 17:15:49 +0000 (17:15 +0000)]
[AMDGPU] Add intrinsics for tbuffer load and store - build error fix
Variable was unused in non-debug build (used in assert) causing compile time
warning and eventual build failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306034
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Sanjay Patel [Thu, 22 Jun 2017 17:01:14 +0000 (17:01 +0000)]
[x86] add tests for select --> sbb transform; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306032
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David Stuttard [Thu, 22 Jun 2017 16:29:22 +0000 (16:29 +0000)]
[AMDGPU] Add intrinsics for tbuffer load and store
Intrinsic already existed for llvm.SI.tbuffer.store
Needed tbuffer.load and also re-implementing the intrinsic as llvm.amdgcn.tbuffer.*
Added CodeGen tests for the 2 new variants added.
Left the original llvm.SI.tbuffer.store implementation to avoid issues with existing code
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr
Differential Revision: https://reviews.llvm.org/D30687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306031
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Krzysztof Parzyszek [Thu, 22 Jun 2017 16:25:46 +0000 (16:25 +0000)]
[Hexagon] Fix typo in a testcase
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306030
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Craig Topper [Thu, 22 Jun 2017 16:23:30 +0000 (16:23 +0000)]
[InstCombine] Teach foldSelectICmpAndOr to recognize (select (icmp slt (trunc (X)), 0), Y, (or Y, C2))
Summary:
InstCombine likes to turn (icmp eq (and X, C1), 0) into (icmp slt (trunc (X)), 0) sometimes. This breaks foldSelectICmpAndOr's ability to recognize (select (icmp eq (and X, C1), 0), Y, (or Y, C2))->(or (shl (and X, C1), C3), y).
This patch tries to recover this. I had to flip around some of the early out checks so that I could create a new And instruction during the compare processing without it possibly never getting used.
Reviewers: spatel, majnemer, davide
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306029
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Teresa Johnson [Thu, 22 Jun 2017 16:18:48 +0000 (16:18 +0000)]
[ThinLTO] Remove unnecessary include of Linker.h (NFC)
The ModuleLinker is no longer used by ThinLTO, so this is not needed.
Patch by Benoit Belley <Benoit.Belley@autodesk.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306028
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Craig Topper [Thu, 22 Jun 2017 16:12:02 +0000 (16:12 +0000)]
[InstCombine] Add one use checks to or/and->xnor folding
If the components of the and/or had multiple uses, this transform created an additional instruction.
This patch makes sure we remove one of the components.
Differential Revision: https://reviews.llvm.org/D34498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306027
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Krzysztof Parzyszek [Thu, 22 Jun 2017 15:53:31 +0000 (15:53 +0000)]
[Hexagon] Handle a global operand to A2_addi when creating duplexes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306012
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Sanjay Patel [Thu, 22 Jun 2017 15:46:54 +0000 (15:46 +0000)]
[InstCombine] reverse bitcast + bitwise-logic canonicalization (PR33138)
There are 2 parts to this patch made simultaneously to avoid a regression.
We're reversing the canonicalization that moves bitwise vector ops before bitcasts.
We're moving bitwise vector ops *after* bitcasts instead. That's the 1st and 3rd hunks
of the patch. The motivation is that there's only one fold that currently depends on
the existing canonicalization (see next), but there are many folds that would
automatically benefit from the new canonicalization.
PR33138 ( https://bugs.llvm.org/show_bug.cgi?id=33138 ) shows why/how we have these
patterns in IR.
There's an or(and,andn) pattern that requires an adjustment in order to continue matching
to 'select' because the bitcast changes position. This match is unfortunately complicated
because it requires 4 logic ops with optional bitcast and sext ops.
Test diffs:
1. The bitcast.ll and bitcast-bigendian.ll changes show the most basic difference -
bitcast comes before logic.
2. There are also tests with no diffs in bitcast.ll that verify that we're still doing
folds that were enabled by the previous canonicalization.
3. icmp-xor-signbit.ll shows the payoff. We don't need to adjust existing icmp patterns
to look through bitcasts.
4. logical-select.ll contains several tests for the or(and,andn) --> select fold to
verify that we are still handling those cases. The lone diff shows the movement of
the bitcast from the new canonicalization rule.
Differential Revision: https://reviews.llvm.org/D33517
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306011
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whitequark [Thu, 22 Jun 2017 15:42:53 +0000 (15:42 +0000)]
[X86] Add support for "probe-stack" attribute
This commit adds prologue code emission for stack probe function
calls.
Reviewed By: majnemer
Differential Revision: https://reviews.llvm.org/D34387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306010
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Florian Hahn [Thu, 22 Jun 2017 15:32:41 +0000 (15:32 +0000)]
[ARM] Create relocations for beq.w branches to ARM function syms.
Summary:
The ARM ELF ABI requires the linker to do interworking for wide
conditional branches from Thumb code to ARM code.
That was pointed out by @peter.smith in the comments for D33436.
Reviewers: rafael, peter.smith, echristo
Reviewed By: peter.smith
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, peter.smith
Differential Revision: https://reviews.llvm.org/D34447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306009
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Sanjay Patel [Thu, 22 Jun 2017 15:28:01 +0000 (15:28 +0000)]
[InstCombine] add peekThroughBitcast() helper; NFC
This is an NFC portion of D33517. We have similar helpers in the backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306008
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Petar Jovanovic [Thu, 22 Jun 2017 15:24:16 +0000 (15:24 +0000)]
[mips] Allow $AT to be used as a register name
This patch allows $AT to be used as a register name in assembly files.
Currently only $at is recognized as a valid register name.
Patch by Stanislav Ocovaj.
Differential Revision: https://reviews.llvm.org/D34348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306007
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Nirav Dave [Thu, 22 Jun 2017 15:07:49 +0000 (15:07 +0000)]
[DAG] Add Target Store Merge pass ordering function
Allow targets to specify if they should merge stores before or after
legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306006
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Pavel Labath [Thu, 22 Jun 2017 14:18:55 +0000 (14:18 +0000)]
Revert "[Support] Add RetryAfterSignal helper function" and subsequent fix
The fix in r306003 uncovered a pretty fundamental problem that libc++
implementation of std::result_of does not handle the prototype of
open(2) correctly (presumably because it contains ...). This makes the
whole function unusable in its current form, so I am also reverting the
original commit (r305892), which introduced the function, at least until
I figure out a way to solve the libc++ issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306005
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Krzysztof Parzyszek [Thu, 22 Jun 2017 14:11:23 +0000 (14:11 +0000)]
[Hexagon] Recognize potential offset overflow for store-imm to stack
Reserve an extra scavenging stack slot if the offset field in store-
-immediate instructions may overflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306004
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Pavel Labath [Thu, 22 Jun 2017 13:55:54 +0000 (13:55 +0000)]
[Support] Fix return type deduction in RetryAfterSignal
The default value of the ResultT template argument (which was there only
to avoid spelling out the long std::result_of template multiple times)
was being overriden by function call template argument deduction. This
manifested itself as a compiler error when calling the function as
FILE *X = RetryAfterSignal(nullptr, fopen, ...)
because the function would try to assign the result of fopen to
nullptr_t, but a more insidious side effect was that
RetryAfterSignal(-1, read, ...) would return "int" instead of "ssize_t",
losing precision along the way.
I fix this by having the function take the argument in a way that
prevents argument deduction from kicking in and add a test that makes
sure the return type is correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306003
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Kamil Rytarowski [Thu, 22 Jun 2017 13:18:46 +0000 (13:18 +0000)]
[Solaris] replace Solaris.h hack with a set of better hacks
Summary:
Got rid of unwieldy -include Solaris.h portability solution, replacing it with interposed header and moving endian defines into Host.h.
Fixes PR28370.
Reviewers: joerg, alekseyshl, mgorny
Reviewed By: joerg
Subscribers: llvm-commits, mgorny, ro, krytarowski
Patch by Fedor Sergeev.
Differential Revision: https://reviews.llvm.org/D3413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306002
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Pavel Labath [Thu, 22 Jun 2017 13:11:50 +0000 (13:11 +0000)]
[Testing/Support] Remove the const_cast in TakeExpected
Summary:
The const_cast in the "const" version of TakeExpected was quite
dangerous, as the function does indeed modify the apparently const
argument.
I assume the reason the const overload was added was to make the
function bind to xvalues(temporaries). That can be also achieved with
rvalue references, so I use that instead.
Using the ASSERT macros on const Expected objects will now become
illegal, but I believe that is correct, as it is not actually possible
to inspect the error stored in an Expected object without modifying it.
Reviewers: zturner, chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34405
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306001
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Sagar Thakur [Thu, 22 Jun 2017 12:48:04 +0000 (12:48 +0000)]
Revert [mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyld
Reverting due to build bot failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306000
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Sam Kolton [Thu, 22 Jun 2017 12:42:14 +0000 (12:42 +0000)]
[AMDGPU] SDWA: remove support for VOP2 instructions that have only 64-bit encoding
Summary:
Despite that this instructions are listed in VOP2, they are treated as VOP3 in specs. They should not support SDWA.
There are no real instructions for them, but there are pseudo instructions.
Reviewers: arsenm, vpykhtin, cfang
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D34403
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305999
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Kristof Beyls [Thu, 22 Jun 2017 12:11:38 +0000 (12:11 +0000)]
Don't conditionalize Neon instructions, even in IT blocks.
This has been deprecated since ARMARM v7-AR, release C.b, published back
in 2012.
This also removes test/CodeGen/Thumb2/ifcvt-neon.ll that originally was
introduced to check that conditionalization of Neon instructions did
happen when generating Thumb2. However, the test had evolved and was no
longer testing that. Rather than trying to adapt that test, this commit
introduces test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir, since we can
now use the MIR framework to write nicer/more maintainable tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305998
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Sagar Thakur [Thu, 22 Jun 2017 11:49:19 +0000 (11:49 +0000)]
[mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyld
After the N64 static relocation model support was added to llvm it is required to add its support in RuntimeDyld also because lldb uses ExecutionEngine for evaluating expressions.
Reviewed by sdardis
Differential: D31649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305997
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Simon Dardis [Thu, 22 Jun 2017 10:41:51 +0000 (10:41 +0000)]
[mips] Implement the ".rdata" MIPS assembly directive.
Rather than creating a separate ".rdata" section distinct from the
customary ".rodata" in ELF, ".rdata" switches to the ".rodata" section.
This patch relands r305949 and r305950 with the correct commit message
and addresses nit raised during review.
Patch By: John Baldwin!
Differential Revision: https://reviews.llvm.org/D34452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305995
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Ekaterina Vaartis [Thu, 22 Jun 2017 10:38:49 +0000 (10:38 +0000)]
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305994
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John Brawn [Thu, 22 Jun 2017 10:30:53 +0000 (10:30 +0000)]
[ARM] Add .w aliases of MOV with shifted operand
These appear to have been simply missing.
Differential Revision: https://reviews.llvm.org/D34461
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305993
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John Brawn [Thu, 22 Jun 2017 10:29:31 +0000 (10:29 +0000)]
[ARM] Clean up choice of narrow instructions in ARMAsmParser, NFC
This patch makes a couple of changes to how we decide whether to use the narrow
or wide encoding of thumb2 instructions:
* Common out the detection of the .w qualifier
* Check for the CPSR operand in a consistent way
Differential Revision: https://reviews.llvm.org/D34460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305992
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Diana Picus [Thu, 22 Jun 2017 10:00:28 +0000 (10:00 +0000)]
Revert "Enable vectorizer-maximize-bandwidth by default."
This reverts commit r305960 because it broke self-hosting on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305990
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Igor Breger [Thu, 22 Jun 2017 09:43:35 +0000 (09:43 +0000)]
[GlobalISel][X86] Support vector type G_INSERT legalization/selection.
Summary:
Support vector type G_INSERT legalization/selection.
Split from https://reviews.llvm.org/D33665
Reviewers: qcolombet, t.p.northover, zvi, guyblank
Reviewed By: guyblank
Subscribers: guyblank, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D33956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305989
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Florian Hahn [Thu, 22 Jun 2017 09:39:36 +0000 (09:39 +0000)]
[ARM] Add macro fusion for AES instructions.
Summary:
This patch adds a macro fusion using CodeGen/MacroFusion.cpp to pair AES
instructions back to back and adds FeatureFuseAES to enable the feature.
Reviewers: evandro, javed.absar, rengolin, t.p.northover
Reviewed By: javed.absar
Subscribers: aemerson, mgorny, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305988
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Elena Demikhovsky [Thu, 22 Jun 2017 06:47:41 +0000 (06:47 +0000)]
AVX-512: Lowering Masked Gather intrinsic - fixed a bug
Masked gather for vector length 2 is lowered incorrectly for element type i32.
The type <2 x i32> was automatically extended to <2 x i64> and we generated VPGATHERQQ instead of VPGATHERQD.
The type <2 x float> is extended to <4 x float>, so there is no bug for this type, but the sequence may be more optimal.
In this patch I'm fixing <2 x i32>bug and optimizing <2 x float> sequence for GATHERs only. The same fix should be done for Scatters as well.
Differential revision: https://reviews.llvm.org/D34343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305987
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Sam Kolton [Thu, 22 Jun 2017 06:26:41 +0000 (06:26 +0000)]
[AMDGPU] SDWA: add support for GFX9 in peephole pass
Summary:
Added support based on merged SDWA pseudo instructions. Now peephole allow one scalar operand, omod and clamp modifiers.
Added several subtarget features for GFX9 SDWA.
This diff also contains changes from D34026.
Depends D34026
Reviewers: vpykhtin, rampitec, arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D34241
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305986
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Craig Topper [Thu, 22 Jun 2017 05:20:39 +0000 (05:20 +0000)]
[InstCombine] Add test cases to demonstrate that and->xnor and or->xnor folding can create more instructions than it removed when there are multiple uses. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305985
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Hiroshi Inoue [Thu, 22 Jun 2017 04:33:44 +0000 (04:33 +0000)]
[PowerPC] fix potential verification errors
This patch fixes trivial mishandling of 32-bit/64-bit instructions that may cause verification errors with -verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305984
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Reid Kleckner [Thu, 22 Jun 2017 01:10:29 +0000 (01:10 +0000)]
[llvm-readobj] Dump the COFF image load config
This includes the safe SEH tables and the control flow guard function
table. LLD will emit the guard table soon, and I need a tool that dumps
them for testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305979
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Reid Kleckner [Thu, 22 Jun 2017 01:07:05 +0000 (01:07 +0000)]
[wasm] Fix WebAssembly asm backend after r305968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305978
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Rafael Espindola [Thu, 22 Jun 2017 00:44:05 +0000 (00:44 +0000)]
Also test thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305976
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Davide Italiano [Thu, 22 Jun 2017 00:11:41 +0000 (00:11 +0000)]
Revert "[Target] Implement the ".rdata" MIPS assembly directive."
This reverts commit r305949 and r305950 as they didn't have the
correct commit message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305973
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Sam Clegg [Wed, 21 Jun 2017 23:46:41 +0000 (23:46 +0000)]
[WebAssembly] Cleanup WasmObjectWriter.cpp. NFC
- Use auto where appropriate
- Use early return to reduce nesting
- Remove stray comment line
- Use C++ foreach over explicit iterator
Differential Revision: https://reviews.llvm.org/D34477
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305971
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Stanislav Mekhanoshin [Wed, 21 Jun 2017 23:46:22 +0000 (23:46 +0000)]
[AMDGPU] Add FP_CLASS to the add/setcc combine
This is one of the nodes which also compile as v_cmp_*.
Differential Revision: https://reviews.llvm.org/D34485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305970
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Eugene Zelenko [Wed, 21 Jun 2017 23:19:47 +0000 (23:19 +0000)]
[ProfileData, Support] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305969
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Rafael Espindola [Wed, 21 Jun 2017 23:06:53 +0000 (23:06 +0000)]
Use a MutableArrayRef. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305968
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Rafael Espindola [Wed, 21 Jun 2017 23:02:57 +0000 (23:02 +0000)]
Fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305967
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Bob Haarman [Wed, 21 Jun 2017 22:31:52 +0000 (22:31 +0000)]
[codeview] respect signedness of APSInts when printing to YAML
Summary:
This fixes a bug where we always treat APSInts in Codeview as
signed when writing them to YAML. One symptom of this problem is that
llvm-pdbdump raw would show Enumerator Values that differ between the
original PDB and a PDB that has been round-tripped through YAML.
Reviewers: zturner
Reviewed By: zturner
Subscribers: llvm-commits, fhahn
Differential Revision: https://reviews.llvm.org/D34013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305965
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Stanislav Mekhanoshin [Wed, 21 Jun 2017 22:30:01 +0000 (22:30 +0000)]
[AMDGPU] Combine add and adde, sub and sube
If one of the arguments of adde/sube is zero we can fold another
add/sub into it.
Differential Revision: https://reviews.llvm.org/D34374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305964
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Sam Clegg [Wed, 21 Jun 2017 22:19:17 +0000 (22:19 +0000)]
Mark dump() methods as const. NFC
Add const qualifier to any dump() method where adding one
was trivial.
Differential Revision: https://reviews.llvm.org/D34481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305963
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Stanislav Mekhanoshin [Wed, 21 Jun 2017 22:05:06 +0000 (22:05 +0000)]
[AMDGPU] simplify add x, *ext (setcc) => addc|subb x, 0, setcc
This simplification allows to avoid generating v_cndmask_b32
to serialize condition code between compare and use.
Differential Revision: https://reviews.llvm.org/D34300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305962
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NAKAMURA Takumi [Wed, 21 Jun 2017 22:04:07 +0000 (22:04 +0000)]
TableGen.cmake: Use DEPFILE for Ninja Generator with CMake>=3.7.
CMake emits build targets as relative paths (from build.ninja) but Ninja doesn't identify absolute path (in *.d) as relative path (in build.ninja).
So, let file names, in the command line, relative from ${CMAKE_BINARY_DIR}, where build.ninja is.
Note that tblgen is executed on ${CMAKE_BINARY_DIR} as working directory.
Differential Revision: https://reviews.llvm.org/D33707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305961
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Dehao Chen [Wed, 21 Jun 2017 22:01:32 +0000 (22:01 +0000)]
Enable vectorizer-maximize-bandwidth by default.
Summary:
vectorizer-maximize-bandwidth is generally useful in terms of performance. I've tested the impact of changing this to default on speccpu benchmarks on sandybridge machines. The result shows non-negative impact:
spec/2006/fp/C++/444.namd 26.84 -0.31%
spec/2006/fp/C++/447.dealII 46.19 +0.89%
spec/2006/fp/C++/450.soplex 42.92 -0.44%
spec/2006/fp/C++/453.povray 38.57 -2.25%
spec/2006/fp/C/433.milc 24.54 -0.76%
spec/2006/fp/C/470.lbm 41.08 +0.26%
spec/2006/fp/C/482.sphinx3 47.58 -0.99%
spec/2006/int/C++/471.omnetpp 22.06 +1.87%
spec/2006/int/C++/473.astar 22.65 -0.12%
spec/2006/int/C++/483.xalancbmk 33.69 +4.97%
spec/2006/int/C/400.perlbench 33.43 +1.70%
spec/2006/int/C/401.bzip2 23.02 -0.19%
spec/2006/int/C/403.gcc 32.57 -0.43%
spec/2006/int/C/429.mcf 40.35 +0.27%
spec/2006/int/C/445.gobmk 26.96 +0.06%
spec/2006/int/C/456.hmmer 24.4 +0.19%
spec/2006/int/C/458.sjeng 27.91 -0.08%
spec/2006/int/C/462.libquantum 57.47 -0.20%
spec/2006/int/C/464.h264ref 46.52 +1.35%
geometric mean +0.29%
The regression on 453.povray seems real, but is due to secondary effects as all hot functions are bit-identical with and without the flag.
I started this patch to consult upstream opinions on this. It will be greatly appreciated if the community can help test the performance impact of this change on other architectures so that we can decided if this should be target-dependent.
Reviewers: hfinkel, mkuper, davidxl, chandlerc
Reviewed By: chandlerc
Subscribers: rengolin, sanjoy, javed.absar, bjope, dorit, magabari, RKSimon, llvm-commits, mzolotukhin
Differential Revision: https://reviews.llvm.org/D33341
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305960
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Krzysztof Parzyszek [Wed, 21 Jun 2017 21:03:34 +0000 (21:03 +0000)]
[Hexagon] Use MachineInstrBuilder instead of changing instruction in place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305953
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Sam Clegg [Wed, 21 Jun 2017 20:58:17 +0000 (20:58 +0000)]
Rename WinCOFFStreamer.cpp -> MCWinCOFFStreamer.cpp
For consistency with other MC*Streamer.cpp files and
the header file.
Differential Revision: https://reviews.llvm.org/D34466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305952
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Nirav Dave [Wed, 21 Jun 2017 20:50:07 +0000 (20:50 +0000)]
Add Aarch64 ldst-opt test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305951
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Davide Italiano [Wed, 21 Jun 2017 20:42:34 +0000 (20:42 +0000)]
[Target/Mips] Add test associated with r305949.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305950
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Davide Italiano [Wed, 21 Jun 2017 20:40:27 +0000 (20:40 +0000)]
[Target] Implement the ".rdata" MIPS assembly directive.
Patch by John Baldwin < jhb at freebsd dot org >!
Differential Revision: https://reviews.llvm.org/D34452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305949
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Davide Italiano [Wed, 21 Jun 2017 20:36:32 +0000 (20:36 +0000)]
[Solaris] emit .init_array instead of .ctors on Solaris (Sparc/x86)
Patch by Fedor Sergeev.
Differential Revision: https://reviews.llvm.org/D33868
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305948
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Craig Topper [Wed, 21 Jun 2017 19:39:35 +0000 (19:39 +0000)]
[Reassociate] Use early returns in a couple places to reduce indentation and improve readability. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305946
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Craig Topper [Wed, 21 Jun 2017 19:39:33 +0000 (19:39 +0000)]
[Reassociate] Const correct a helper function. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305945
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Wolfgang Pieb [Wed, 21 Jun 2017 19:37:44 +0000 (19:37 +0000)]
[DWARF] Support for DW_FORM_strx3 and complete support for DW_FORM_strx{1,2,4}
(consumer).
Reviewer: aprantl
Differential Revision: https://reviews.llvm.org/D34418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305944
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Krzysztof Parzyszek [Wed, 21 Jun 2017 19:21:30 +0000 (19:21 +0000)]
[Hexagon] Handle more types of immediate operands in expand-condsets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305943
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Craig Topper [Wed, 21 Jun 2017 18:57:00 +0000 (18:57 +0000)]
[InstCombine] Cleanup using commutable matchers. Make a couple helper methods standalone static functions. Put 'if' around variable declaration instead of after. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305941
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whitequark [Wed, 21 Jun 2017 18:46:50 +0000 (18:46 +0000)]
Add a "probe-stack" attribute
This attribute is used to ensure the guard page is triggered on stack
overflow. Stack frames larger than the guard page size will generate
a call to __probestack to touch each page so the guard page won't
be skipped.
Reviewed By: majnemer
Differential Revision: https://reviews.llvm.org/D34386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305939
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Michael Kruse [Wed, 21 Jun 2017 18:25:37 +0000 (18:25 +0000)]
[BasicAA] Use MayAlias instead of PartialAlias for fallback.
Using various methods, BasicAA tries to determine whether two
GetElementPtr memory locations alias when its base pointers are known
to be equal. When none of its heuristics are applicable, it falls back
to PartialAlias to, according to a comment, protect TBAA making a wrong
decision in case of unions and malloc. PartialAlias is not correct,
because a PartialAlias result implies that some, but not all, bytes
overlap which is not necessarily the case here.
AAResults returns the first analysis result that is not MayAlias.
BasicAA is always the first alias analysis. When it returns
PartialAlias, no other analysis is queried to give a more exact result
(which was the intention of returning PartialAlias instead of MayAlias).
For instance, ScopedAA could return a more accurate result.
The PartialAlias hack was introduced in r131781 (and re-applied in
r132632 after some reverts) to fix llvm.org/PR9971 where TBAA returns a
wrong NoAlias result due to a union. A test case for the malloc case
mentioned in the comment was not provided and I don't think it is
affected since it returns an omnipotent char anyway.
Since r303851 (https://reviews.llvm.org/D33328) clang does emit specific
TBAA for unions anymore (but "omnipotent char" instead). Hence, the
PartialAlias workaround is not required anymore.
This patch passes the test-suite and check-llvm/check-clang of a
self-hoisted build on x64.
Reviewed By: hfinkel
Differential Revision: https://reviews.llvm.org/D34318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305938
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Peter Collingbourne [Wed, 21 Jun 2017 18:23:19 +0000 (18:23 +0000)]
Object: Have the irsymtab builder take a string table builder. NFCI.
This will be needed in order to share the irsymtab string table with
the bitcode string table.
Differential Revision: https://reviews.llvm.org/D33971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305937
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Sanjay Patel [Wed, 21 Jun 2017 18:20:52 +0000 (18:20 +0000)]
[CGP, memcmp] replace CreateZextOrTrunc with CreateZext because it can never trunc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305936
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Sanjay Patel [Wed, 21 Jun 2017 18:06:13 +0000 (18:06 +0000)]
[CGP] fix variables to be unsigned in memcmp expansion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305935
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Dehao Chen [Wed, 21 Jun 2017 17:57:43 +0000 (17:57 +0000)]
Do not inline recursive direct calls in sample loader pass.
Summary: r305009 disables recursive inlining for indirect calls in sample loader pass. The same logic applies to direct recursive calls.
Reviewers: iteratee, davidxl
Reviewed By: iteratee
Subscribers: sanjoy, llvm-commits, eraman
Differential Revision: https://reviews.llvm.org/D34456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305934
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Reid Kleckner [Wed, 21 Jun 2017 17:25:56 +0000 (17:25 +0000)]
[PDB] Add symbols to the PDB
Summary:
The main complexity in adding symbol records is that we need to
"relocate" all the type indices. Type indices do not have anything like
relocations, an opaque data structure describing where to find existing
type indices for fixups. The linker just has to "know" where the type
references are in the symbol records. I added an overload of
`discoverTypeIndices` that works on symbol records, and it seems to be
able to link the standard library.
Reviewers: zturner, ruiu
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D34432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305933
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Lei Huang [Wed, 21 Jun 2017 17:17:56 +0000 (17:17 +0000)]
[PowerPC] define target hook isReallyTriviallyReMaterializable()
Define target hook isReallyTriviallyReMaterializable() to explicitly specify
PowerPC instructions that are trivially rematerializable. This will allow
the MachineLICM pass to accurately identify PPC instructions that should always
be hoisted.
Differential Revision: https://reviews.llvm.org/D34255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305932
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Sanjay Patel [Wed, 21 Jun 2017 17:06:24 +0000 (17:06 +0000)]
[x86] set the datalayout to match the RUN line triple; NFC
I don't think there's any visible difference from having the wrong layout
for the 32-bit case at this point, but that could change in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305931
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Craig Topper [Wed, 21 Jun 2017 16:32:35 +0000 (16:32 +0000)]
[InstCombine] Add range metadata to cttz/ctlz/ctpop intrinsic calls based on known bits
Summary:
I noticed that passing known bits across these intrinsics isn't great at capturing the information we really know. Turning known bits of the input into known bits of a count output isn't able to convey a lot of what we really know.
This patch adds range metadata to these intrinsics based on the known bits.
Currently the patch punts if we already have range metadata present.
Reviewers: spatel, RKSimon, davide, majnemer
Reviewed By: RKSimon
Subscribers: sanjoy, hfinkel, llvm-commits
Differential Revision: https://reviews.llvm.org/D32582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305927
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Craig Topper [Wed, 21 Jun 2017 16:07:13 +0000 (16:07 +0000)]
[InstCombine] Don't let folding (select (icmp eq (and X, C1), 0), Y, (or Y, C2)) create more instructions than it removes
Summary:
Previously this folding had no checks to see if it was going to result in less instructions. This was pointed out during the review of D34184
This patch adds code to count how many instructions its going to create vs how many its going to remove so we can make a proper decision.
Reviewers: spatel, majnemer
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305926
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Craig Topper [Wed, 21 Jun 2017 16:07:09 +0000 (16:07 +0000)]
[Reassociate] Support xor reassociating for splat vectors
Summary: This patch adds support for xors of splat vectors.
Reviewers: mcrosier
Reviewed By: mcrosier
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305925
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Dmitry Preobrazhensky [Wed, 21 Jun 2017 16:00:54 +0000 (16:00 +0000)]
[AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failures
See Bug 33509: https://bugs.llvm.org//show_bug.cgi?id=33509
Reviewers: Sam Kolton, Artem Tamazov, Valery Pykhtin
Differential Revision: https://reviews.llvm.org/D34360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305923
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Nirav Dave [Wed, 21 Jun 2017 15:40:43 +0000 (15:40 +0000)]
[DAG] Move BaseIndexOffset into separate Libarary. NFC.
Move BaseIndexOffset analysis out of DAGCombiner for use in other
files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305921
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David Blaikie [Wed, 21 Jun 2017 15:20:46 +0000 (15:20 +0000)]
ClangFormat some changes from r305226
Post commit review feedback from Justin Bogner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305919
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Christof Douma [Wed, 21 Jun 2017 15:18:39 +0000 (15:18 +0000)]
[AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics.
Added test file for ARMv8.1 LSE Atomics that I forgot to include in
commit r305893.
Patch by Ananth Jasty.
Differential Revision: https://reviews.llvm.org/D33586
Change-Id: Ic1ad8ed87c1b584c4c791b459a686c866a3c3087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305918
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Nirav Dave [Wed, 21 Jun 2017 15:07:30 +0000 (15:07 +0000)]
[DAG] Remove Node csonstruction from BaseIndexOffset match. NFCI.
Move GlobalAddress Offset decomposition from initial match into
comparision check and removing the possibility of constructing a new
offseted global address when examining addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305917
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Simon Pilgrim [Wed, 21 Jun 2017 14:51:23 +0000 (14:51 +0000)]
[X86][SSE] Dropped -mcpu from 256-bit vector shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305916
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Dmitry Preobrazhensky [Wed, 21 Jun 2017 14:41:34 +0000 (14:41 +0000)]
[AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is different than any of the src
See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279
Reviewers: artem.tamazov, vpykhtin
Differential Revision: https://reviews.llvm.org/D34003
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305915
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Sanjay Patel [Wed, 21 Jun 2017 14:27:11 +0000 (14:27 +0000)]
[x86] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305914
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Simon Pilgrim [Wed, 21 Jun 2017 14:23:02 +0000 (14:23 +0000)]
[X86][SSE] Dropped -mcpu from 128-bit vector shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305913
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Simon Pilgrim [Wed, 21 Jun 2017 13:46:42 +0000 (13:46 +0000)]
[X86][SSE] Regenerate merge store tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305910
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Simon Pilgrim [Wed, 21 Jun 2017 13:45:33 +0000 (13:45 +0000)]
[X86][SSE] Dropped -mcpu from vector blend shuffle tests and regenerate
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305909
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Simon Pilgrim [Wed, 21 Jun 2017 13:26:52 +0000 (13:26 +0000)]
[X86][SSE] Dropped -mcpu from vector shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305908
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Simon Pilgrim [Wed, 21 Jun 2017 13:17:14 +0000 (13:17 +0000)]
[X86][SSE] Dropped -mcpu from vector zero extend tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305907
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Simon Pilgrim [Wed, 21 Jun 2017 13:15:41 +0000 (13:15 +0000)]
[X86][SSE] Dropped -mcpu from variable shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305906
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Simon Pilgrim [Wed, 21 Jun 2017 12:58:56 +0000 (12:58 +0000)]
[X86][AVX] Add AVX1 shuffle truncation tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305905
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Simon Pilgrim [Wed, 21 Jun 2017 12:58:19 +0000 (12:58 +0000)]
[X86][SSE] Add SSE2/SSE42 shuffle truncation tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305904
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Zvi Rackover [Wed, 21 Jun 2017 11:21:43 +0000 (11:21 +0000)]
[X86] Rerun the update_llc_test_checks tool on test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305897
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Pavel Labath [Wed, 21 Jun 2017 11:10:02 +0000 (11:10 +0000)]
Fix build after r305892
Make sure to #include <cerrno> in Support/Errno.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305895
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Christof Douma [Wed, 21 Jun 2017 10:58:31 +0000 (10:58 +0000)]
[AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics.
Implemented support to AArch64 codegen for ARMv8.1 Large System
Extensions atomic instructions. Where supported, these instructions can
provide atomic operations with higher performance.
Currently supported operations include: fetch_add, fetch_or, fetch_xor,
fetch_smin, fetch_min/max (signed and unsigned), swap, and
compare_exchange.
This implementation implies sequential-consistency ordering, more
relaxed ordering is under development.
Subtarget->hasLSE is currently supported for Cavium ThunderX2T99.
Patch by Ananth Jasty.
Differential Revision: https://reviews.llvm.org/D33586
Change-Id: I82f6d3d64255622791ceb0715b7ab9f4dc4d4b2c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305893
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Pavel Labath [Wed, 21 Jun 2017 10:55:34 +0000 (10:55 +0000)]
[Support] Add RetryAfterSignal helper function
Summary:
This function retries an operation if it was interrupted by a signal
(failed with EINTR). It's inspired by the TEMP_FAILURE_RETRY macro in
glibc, but I've turned that into a template function. I've also added a
fail-value argument, to enable the function to be used with e.g.
fopen(3), which is documented to fail for any reason that open(2) can
fail (which includes EINTR).
The main user of this function will be lldb, but there were also a
couple of uses within llvm that I could simplify using this function.
Reviewers: zturner, silvas, joerg
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D33895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305892
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Florian Hahn [Wed, 21 Jun 2017 09:51:52 +0000 (09:51 +0000)]
[AArch64] Add early exit to promoteLoadFromStore.
There should be at most a single kill flag for the
promoted operand between the store/load pair.
Discussed in https://reviews.llvm.org/D34402.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305889
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Strahinja Petrovic [Wed, 21 Jun 2017 09:25:51 +0000 (09:25 +0000)]
[MIPS] Fix for selecting of DINS/INS instruction
This patch adds one more condition in selection DINS/INS
instruction, which fixes MultiSource/Applications/JM/ldecod/
for mips32r2 (and mips64r2 n32 abi).
Differential Revision: https://reviews.llvm.org/D33725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305888
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Javed Absar [Wed, 21 Jun 2017 09:10:10 +0000 (09:10 +0000)]
Use range-loop in machine-scheduler. NFCI.
Converts to range-loop usage in machine scheduler.
This makes the code neater and easier to read,
and also keeps pace of the machine scheduler
implementation with C++11 features.
Reviewed by: Matthias Braun
Differential Revision: https://reviews.llvm.org/D34320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305887
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Sam Kolton [Wed, 21 Jun 2017 08:53:38 +0000 (08:53 +0000)]
[AMDGPU] SDWA: merge VI and GFX9 pseudo instructions
Summary: Previously there were two separate pseudo instruction for SDWA on VI and on GFX9. Created one pseudo instruction that is union of both of them. Added verifier to check that operands conform either VI or GFX9.
Reviewers: dp, arsenm, vpykhtin
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, artem.tamazov
Differential Revision: https://reviews.llvm.org/D34026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305886
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Florian Hahn [Wed, 21 Jun 2017 08:47:23 +0000 (08:47 +0000)]
[AArch64] Preserve register flags when promoting a load from store.
Summary:
This patch updates promoteLoadFromStore to use the store MachineOperand as the
source operand of the of the new instruction instead of creating a new
register MachineOperand. This way, the existing register flags are
preserved.
This fixes PR33468 (https://bugs.llvm.org/show_bug.cgi?id=33468).
Reviewers: MatzeB, t.p.northover, junbuml
Reviewed By: MatzeB
Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305885
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Guy Blank [Wed, 21 Jun 2017 07:38:41 +0000 (07:38 +0000)]
[DAGCombiner] Add another combine from build vector to shuffle
Add support for combining a build vector to a shuffle.
When the build vector is of extracted elements from 2 vectors (vec1, vec2) where vec2 is 2 times smaller than vec1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305883
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Max Kazantsev [Wed, 21 Jun 2017 07:28:13 +0000 (07:28 +0000)]
[SCEV] Make MulOpsInlineThreshold lower to avoid excessive compilation time
MulOpsInlineThreshold option of SCEV is defaulted to 1000, which is inadequately high.
When constructing SCEVs of expressions like:
x1 = a * a
x2 = x1 * x1
x3 = x2 * x2
...
We actually have huge SCEVs with max allowed amount of operands inlined.
Such expressions are easy to get from unrolling of loops looking like
x = a
for (i = 0; i < n; i++)
x = x * x
Or more tricky cases where big powers are involved. If some non-linear analysis
tries to work with a SCEV that has 1000 operands, it may lead to excessively long
compilation. The attached test does not pass within 1 minute with default threshold.
This patch decreases its default value to 32, which looks much more reasonable if we
use analyzes with complexity O(N^2) or O(N^3) working with SCEV.
Differential Revision: https://reviews.llvm.org/D34397
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305882
91177308-0d34-0410-b5e6-
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