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Jason Ekstrand [Wed, 13 Feb 2019 22:22:37 +0000 (16:22 -0600)]
nir/xfb: Work in terms of components rather than slots
We needed to better handle cases where a chunk of a variable starts at
some non-zero location_frac and rolls over into the next slot but may
not be more than 4 dwords. For example, if gl_CullDistance is an array
of 3 things and has location_frac = 2, it will span across two vec4s but
is not, itself, bigger than a vec4. If you ignore the clip/cull special
case, it's not allowed to happen for anything else because the only
things that can span more than one slot is dvec3 and dvec4 and they're
both bigger than a vec4. The current code uses this attrib_slot thing
where we count attribute slots and iterate over them. However, that
doesn't work in the case above because gl_CullDistance will have an
attrib_slot count of 1 even though it does span two slots. We could fix
this by adjusting attrib_slot but we already have comp_mask and it's
easier to just handle it that way.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit
558c3145045f1c6da8bddb31ed77a418ab27f2f9)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/compiler/nir/nir_gather_xfb_info.c
Jason Ekstrand [Tue, 12 Feb 2019 18:49:08 +0000 (12:49 -0600)]
nir/xfb: Properly align 64-bit values
Fixes:
19064b8c "nir: Add a pass for gathering transform feedback info"
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit
8f0fe71cc5658728adc273daa03400aab7ec6d93)
Jason Ekstrand [Tue, 12 Feb 2019 19:03:34 +0000 (13:03 -0600)]
compiler/types: Add a contains_64bit helper
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit
30b548fc6258e9a72722f511e377cf4716fd443c)
Andrii Simiklit [Fri, 25 Jan 2019 13:03:07 +0000 (15:03 +0200)]
i965: re-emit index buffer state on a reset option change.
Seems like we forget to update the index buffer (ib) status and
IndexedDrawCutIndexEnable or CutIndexEnable flag is left unchanged it
leads to ignoring of glEnable/glDisable functions for GL_PRIMITIVE_RESTART
in some cases. The index buffer (ib) status should be re-emmited after the
reset option change to avoid some unexpected behavior.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109451
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Signed-off-by: Andrii Simiklit <asimiklit.work@gmail.com>
(cherry picked from commit
f4f4ec941e1427142656e588244f378e469e996e)
Carlos Garnacho [Tue, 20 Nov 2018 17:06:38 +0000 (18:06 +0100)]
wayland/egl: Ensure EGL surface is resized on DRI update_buffers()
Fullscreening and unfullscreening a totem window while playing a video
sometimes results in the video subsurface not changing size along. This
is also reproducible with epiphany.
If a surface gets resized while we have an active back buffer for it, the
resized dimensions won't get neither immediately applied on the resize
callback, nor correctly synchronized on update_buffers(), as the
(now stale) surface size and currently attached buffer size still do match.
There's actually 2 things to synchronize here, first the surface query
size might not be updated yet to the wl_egl_window's (i.e. resize_callback
happened while there is a back buffer), and second the wayland buffers
would need dropping if new surface size differs with the currently attached
buffer. These are done in separate steps now.
https://bugzilla.redhat.com/show_bug.cgi?id=
1650929
https://bugs.freedesktop.org/show_bug.cgi?id=109594
Fixes:
a9fb331ea7d ("wayland/egl: update surface size on window resize")
Signed-off-by: Carlos Garnacho <carlosg@gnome.org>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Bastien Nocera <hadess@hadess.net>
Tested-by: Denys Kostin <denys.kostin@globallogic.com>
(cherry picked from commit
30a01cd9232ed83a0259d184b82e050bae219ed3)
Bas Nieuwenhuizen [Wed, 20 Feb 2019 01:19:42 +0000 (02:19 +0100)]
radv: Sync ETC2 whitelisted devices.
Fixes:
4bb6c49375e "radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9."
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
7631feaa0040616585cf69b52241d2b06b82b524)
Marek Olšák [Tue, 19 Feb 2019 22:29:52 +0000 (17:29 -0500)]
driconf: add Civ6Sub executable for Civilization 6
I'm getting Civ6Sub instead of Civ6.
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
bff8da6c591e55e4b5f04aea1fef29e6230e9222)
Marek Olšák [Tue, 19 Feb 2019 22:21:20 +0000 (17:21 -0500)]
radeonsi: always enable NIR for Civilization 6 to fix corruption
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
ae21bdf47cacafdf69b904cbf3e433cbe0cccb84)
Marek Olšák [Tue, 19 Feb 2019 22:20:01 +0000 (17:20 -0500)]
radeonsi: add driconf option radeonsi_enable_nir
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
ccbfe44e5ff88a19451701561f752c6046677122)
Rhys Perry [Thu, 6 Dec 2018 12:11:00 +0000 (12:11 +0000)]
radv: ensure export arguments are always float
So that the signature is correct and consistent, the inputs to a export
intrinsic should always be 32-bit floats.
This and the previous commit fixes a large amount crashes from
dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_*
tests
Fixes:
b722b29f10d ('radv: add support for 16bit input/output')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
0ca550e01ac55c67c2deef50f5cb750a0181352b)
Rhys Perry [Thu, 6 Dec 2018 12:10:41 +0000 (12:10 +0000)]
radv: bitcast 16-bit outputs to integers
16-bit outputs are stored as 16-bit floats in the outputs array, so they
have to be bitcast.
Fixes:
b722b29f10d ('radv: add support for 16bit input/output')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
64065aa504c4872a15f7b0894b6037a6b2bcae65)
Samuel Pitoiset [Mon, 18 Feb 2019 16:42:10 +0000 (17:42 +0100)]
radv: fix writing the alpha channel of MRT0 when alpha coverage is enabled
This version is better and safer.
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
47616810ed7cfce21d239391131ad9a5ef558b52)
Samuel Pitoiset [Fri, 15 Feb 2019 17:02:52 +0000 (18:02 +0100)]
radv: write the alpha channel of MRT0 when alpha coverage is enabled
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109597
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
0d8f09629377da9cf48ab4315574d69fdef5369d)
Jason Ekstrand [Tue, 12 Feb 2019 04:39:45 +0000 (22:39 -0600)]
intel/fs: Bail in optimize_extract_to_float if we have modifiers
This fixes a bug in runscape where we were optimizing x >> 16 to an
extract and then negating and converting to float. The NIR to fs pass
was dropping the negate on the floor breaking a geometry shader and
causing it to render nothing.
Fixes:
1f862e923cb "i965/fs: Optimize float conversions of byte/word..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109601
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit
367b0ede4d9115aba772d6e46ec73642761f7ff6)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/intel/compiler/brw_fs_nir.cpp
Emil Velikov [Mon, 18 Feb 2019 18:33:16 +0000 (18:33 +0000)]
docs: add sha256 checksums for 18.3.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 18 Feb 2019 18:23:55 +0000 (18:23 +0000)]
docs: add release notes for 18.3.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 18 Feb 2019 18:19:54 +0000 (18:19 +0000)]
Update version to 18.3.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Eric Anholt [Mon, 11 Feb 2019 19:51:35 +0000 (11:51 -0800)]
vc4: Fix copy-and-paste fail in backport of NEON asm fixes.
One of the cpu pointers wasn't marked as read-write, causing gcc to complain:
../src/gallium/drivers/vc4/vc4_tiling_lt.c:181:17: error: output operand constraint lacks ‘=’
__asm__ volatile (
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Fixes:
813f0a82960 ("vc4: Declare the cpu pointers as being modified in NEON asm.")
Dylan Baker [Wed, 13 Feb 2019 17:26:16 +0000 (09:26 -0800)]
meson: Add dependency on genxml to anvil
Currently the Intel "anvil" driver races with the generation of genxml
files, while i965 has an explicit dependency. This patch adds the same
dependency to anvil.
Fixes:
d1992255bb29054fa51763376d125183a9f602f
("meson: Add build Intel "anv" vulkan driver")
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
279060cd32dd673c6a5bf302ceac852f51a6c17c)
Samuel Pitoiset [Tue, 12 Feb 2019 08:50:15 +0000 (09:50 +0100)]
radv: always export gl_SampleMask when the fragment shader uses it
For some reasons, this breaks trees rendering in Project Cars.
Fixes:
85010585cde ("radv: only enable gl_SampleMask if MSAA is enabled too")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109401
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
334da034d8d91ca5a0a1bff8deaefd8ca762c42e)
Dylan Baker [Tue, 12 Feb 2019 22:03:21 +0000 (14:03 -0800)]
get-pick-list: Add --pretty=medium to the arguments for Cc patches
Because none of them have been picked up for 19.0 due to this bug
being reintroduced.
v2: - Fix fixes tags
Fixes:
e6b3a3b2014413366110f6deeced8095e7262b1d
("bin/get-pick-list.sh: handle "typod" usecase.")
Fixes:
fac10169bbad2da918ef07a62c01e0b321508cfe
("bin/get-pick-list.sh: prefix output with "[stable] "")
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
aff52dd2c61eb8d1b03cebbcca7e070ffa48afdf)
Oscar Blumberg [Tue, 12 Feb 2019 20:52:51 +0000 (21:52 +0100)]
radeonsi: Fix guardband computation for large render targets
Stop using 12.12 quantization for viewports that are not contained in
the lower 4k corner of the render target as the hardware needs to keep
both absolute and relative coordinates representable.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
3c540e0a748844258e77254fc4f864f3b875fe18)
Juan A. Suarez Romero [Tue, 12 Feb 2019 18:19:13 +0000 (19:19 +0100)]
anv/cmd_buffer: check for NULL framebuffer
This can happen when we record a VkCmdDraw in a secondary buffer that
was created inheriting from the primary buffer, but with the framebuffer
set to NULL in the VkCommandBufferInheritanceInfo.
Vulkan 1.1.81 spec says that "the application must ensure (using scissor
if neccesary) that all rendering is contained in the render area [...]
[which] must be contained within the framebuffer dimesions".
While this should be done by the application, commit
465e5a86 added the
clamp to the framebuffer size, in case of application does not do it.
But this requires to know the framebuffer dimensions.
If we do not have a framebuffer at that moment, the best compromise we
can do is to just apply the scissor as it is, and let the application to
ensure the rendering is contained in the render area.
v2: do not clamp to framebuffer if there isn't a framebuffer
v3 (Jason):
- clamp earlier in the conditional
- clamp to render area if command buffer is primary
v4: clamp also x and y to render area (Jason)
v5: rename used variables (Jason)
Fixes:
465e5a86 ("anv: Clamp scissors to the framebuffer boundary")
CC: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
1ad26f941792f07f226c054811be78b0c0ac9fce)
Emil Velikov [Tue, 12 Feb 2019 18:22:46 +0000 (18:22 +0000)]
cherry-ignore: radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8
stable The commit addresses functionality not present in branch.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Rodrigo Vivi [Sat, 2 Feb 2019 08:03:04 +0000 (00:03 -0800)]
intel: Add more PCI Device IDs for Coffee Lake and Ice Lake.
Align with kernel commits:
5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.")
03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit
56c3b4971d44748ad8618efdf8833ec2f9af4078)
Mario Kleiner [Wed, 13 Jun 2018 04:04:15 +0000 (06:04 +0200)]
egl/wayland-drm: Only announce formats via wl_drm which the driver supports.
Check if a pixel format is supported by the Wayland servers gpu driver
before exposing it to the client via wl_drm, so we avoid reporting formats
to the client which the server gpu can't handle.
Restrict this reporting to the new color depth 30 formats for now, as the
ARGB/XRGB8888 and RGB565 formats are probably supported by every gpu under
the sun.
Atm. this is mostly useful to allow proper PRIME renderoffload for depth
30 formats on the typical Intel iGPU + NVidia dGPU "NVidia Optimus" laptop
combo.
Tested on Intel, AMD, NVidia with single-gpu setup and on a Intel + NVidia
Optimus setup.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit
820dfcea431e4f96f25e6b340edd9cd1e449158b)
Mario Kleiner [Wed, 13 Jun 2018 04:04:14 +0000 (06:04 +0200)]
egl/wayland: Allow client->server format conversion for PRIME offload. (v2)
Support PRIME render offload between a Wayland server gpu and a Wayland
client gpu with different channel ordering for their color formats,
e.g., between Intel drivers which currently only support ARGB2101010
and XRGB2101010 import/display and nouveau which only supports ABGR2101010
rendering and display on nv-50 and later.
In the wl_visuals table, we also store for each format an alternate
sibling format which stores colors at the same precision, but with
different channel ordering, e.g., ARGB2101010 <-> ABGR2101010.
If a given client-gpu renderable format is not supported by the server
for import, but the alternate format is supported by the server, expose
the client-gpu renderable format as a valid EGLConfig to the client. At
eglSwapBuffers time, during the blitImage() detiling blit from the client
backbuffer to the linear buffer, the client format is converted to the
server supported format. As we have to do a copy for PRIME anyway,
this channel swizzling conversion comes essentially for free.
Note that even if a server gpu in principle does support sampling
from the clients native format, this conversion will be a performance
advantage if it allows to convert to the servers preferred format
for direct scanout, as the Wayland compositor may then be able to
directly page-flip a fullscreen client wl_buffer onto the primary
plane, or onto a hardware overlay plane, avoiding an extra data copy
for desktop composition.
Tested so far under Weston with: nouveau single-gpu, Intel single-gpu,
AMD single-gpu, "Optimus" Intel server iGPU for display + NVidia
client dGPU for rendering.
v2: Implement minor review comments by Eric Engestrom: Add some
comment and assert, and some style fixes for clarity.
No functional change.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit
a34b0d68bbf8571e4d858cf4e1176766a50364de)
Iago Toral Quiroga [Mon, 28 May 2018 11:03:24 +0000 (13:03 +0200)]
intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments
The implementation of these opcodes in the generator assumes that their
arguments are packed, and it generates register regions based on that
assumption.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
391894321161b37a3f8ae1cae4ece6c72ea38bc1)
Samuel Pitoiset [Mon, 11 Feb 2019 09:17:52 +0000 (10:17 +0100)]
radv: fix compiler issues with GCC 9
"The C standard says that compound literals which occur inside of
the body of a function have automatic storage duration associated
with the enclosing block. Older GCC releases were putting such
compound literals into the scope of the whole function, so their
lifetime actually ended at the end of containing function. This
has been fixed in GCC 9. Code that relied on this extended lifetime
needs to be fixed, move the compound literals to whatever scope
they need to accessible in."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109543
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Gustaw Smolarczyk <wielkiegie@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
129a9f4937b8f2adb4d37999677d748d816d611c)
Kenneth Graunke [Mon, 11 Feb 2019 06:49:20 +0000 (22:49 -0800)]
st/mesa: Limit GL_MAX_[NATIVE_]PROGRAM_PARAMETERS_ARB to 2048
Piglit's vp-max-array test creates a vertex program containing a uniform
array sized to the value of GL_MAX_NATIVE_PROGRAM_PARAMETERS_ARB. Mesa
will then add additional state-var parameters for things like the MVP
matrix.
radeonsi currently exposes a value of 4096, derived from constant buffer
upload size. This means the array will have 4096 elements, and the
extra MVP state-vars would get a prog_src_register::Index of over 4096.
Unfortunately, prog_src_register::Index is a signed 13-bit integer, so
values beyond 4096 end up turning into negative numbers. Negative
source indexes are only valid for relative addressing, so this ends up
generating illegal IR.
In prog_to_nir, this would cause an out of bounds array access.
st_mesa_to_tgsi checks for a negative value, assumes it's bogus,
and remaps it to parameter 0 in order to get something in-range.
This isn't right - instead of reading the MVP matrix, it would read
the first element of the vertex program's large array. But the test
only checks that the program compiles, so we never noticed that it
was broken.
This patch limits the size of the program limits, with the understanding
that we may need to generate additional state-vars internally. i965 has
exposed 1024 for this limit for years, so I don't expect lowering it to
2048 will cause any practical problems for radeonsi or other drivers.
Fixes vp-max-array with prog_to_nir.c.
Cc: "19.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
f45dd6d31b2ff46a082931386ccd0bf043cfad59)
Leo Liu [Fri, 8 Feb 2019 14:48:23 +0000 (09:48 -0500)]
st/va/vp9: set max reference as default of VP9 reference number
If there is no information about number of render targets
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
a0a52a036708dbf5989778795fd67a79e3226289)
Leo Liu [Fri, 8 Feb 2019 13:56:53 +0000 (08:56 -0500)]
st/va: fix the incorrect max profiles report
Add "PIPE_VIDEO_PROFILE_MAX" to enum, so it will make sure here will
be correct when adding more profiles in the future.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109107
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
21cdb828a3f4d1e2f140fc7c81a4bc305b2f6b04)
Marek Olšák [Mon, 4 Feb 2019 20:12:17 +0000 (15:12 -0500)]
winsys/amdgpu: don't drop manually added fence dependencies
wow, it's hard to believe that fence and syncobjs dependencies were ignored.
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit
ddfe209a0d61917e7b08100eeac82f4c20ca59e8)
Marek Olšák [Fri, 1 Feb 2019 22:10:46 +0000 (17:10 -0500)]
radeonsi: fix EXPLICIT_FLUSH for flush offsets > 0
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit
61c678d4bc91d2ff9ca8c9b183e08daf07d8d24c)
Marek Olšák [Fri, 1 Feb 2019 22:10:46 +0000 (17:10 -0500)]
gallium/u_threaded: fix EXPLICIT_FLUSH for flush offsets > 0
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit
4522f01d4ef9e8a1bb945ca28fba7649aae2171b)
Jason Ekstrand [Mon, 11 Feb 2019 04:23:01 +0000 (22:23 -0600)]
nir/deref: Rematerialize parents in rematerialize_derefs_in_use_blocks
When nir_rematerialize_derefs_in_use_blocks_impl was first written, I
attempted to optimize things a bit by not bothering to re-materialize
the sources of deref instructions figuring that the final caller would
take care of that. However, in the case of more complex deref chains
where the first link or two lives in block A and then another link and
the load/store_deref intrinsic live in block B it doesn't work. The
code in rematerialize_deref_in_block looks at the tail of the chain,
sees that it's already in block B and skips it, not realizing that part
of the chain also lives in block A.
The easy solution here is to just rematerialize deref sources of deref
instructions as well. This may potentially lead to a few more deref
instructions being created by the conditions required for that to
actually happen are fairly unlikely and, thanks to the caching, it's all
linear time regardless.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109603
Fixes:
7d1d1208c2b "nir: Add a small pass to rematerialize derefs per-block"
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit
9e6a6ef0d45a5bb61a541c495fe12e54e646ecfe)
Ilia Mirkin [Sun, 10 Feb 2019 03:36:49 +0000 (22:36 -0500)]
nvc0: we have 16k-sized framebuffers, fix default scissors
For some reason we don't use view volume clipping by default, and use
scissors instead. These scissors were set to an 8k max fb size, while
the driver advertises 16k-sized framebuffers.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
cc79a1483ffb7b91edc97c9870eadcab1e83b8f3)
Emil Velikov [Thu, 14 Feb 2019 12:32:02 +0000 (12:32 +0000)]
cherry-ignore: add more 19.0 only nominations from Ilia
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Kristian H. Kristensen [Wed, 6 Feb 2019 21:47:32 +0000 (13:47 -0800)]
freedreno/a6xx: Emit blitter dst with OUT_RELOCW
We're writing to the bo and the kernel needs to know for
fd_bo_cpu_prep() to work.
Fixes:
f93e43127252679b ("freedreno/a6xx: Enable blitter")
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
(cherry picked from commit
357ea7da51a2392eb1b7f464ff99cbe8e98378e2)
Bas Nieuwenhuizen [Wed, 23 Jan 2019 21:44:05 +0000 (22:44 +0100)]
amd/common: Use correct writemask for shared memory stores.
The check was for 1 bit being set, which is clearly not what we want.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
3c24fc64c7a4e564d84843fab7db25963d574d99)
Bas Nieuwenhuizen [Tue, 22 Jan 2019 21:29:26 +0000 (22:29 +0100)]
radv: Only look at pImmutableSamples if the descriptor has a sampler.
Equivalent of ANV patch
c7f4a2867ce492d78c1f8e2870c0a593d280572d
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
39ab4e12f71a640b43403a110d3d85565b59d16c)
Eric Engestrom [Wed, 6 Feb 2019 16:28:12 +0000 (16:28 +0000)]
xvmc: fix string comparison
Fixes:
6fca18696d0e6a243f6f "g3dvl: Update XvMC unit tests."
Cc: Younes Manton <younes.m@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
40b53a72033a601ab474c5f8e27eb5ca2c8bad6c)
Eric Engestrom [Wed, 6 Feb 2019 16:21:08 +0000 (16:21 +0000)]
xvmc: fix string comparison
Fixes:
c7b65dcaffeb9d0760c8 "xvmc: Define some Xv attribs to allow users
to specify color standard and procamp"
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
110a6e1839bcf31e3592389ad55a7ba07b551965)
Bart Oldeman [Sun, 3 Feb 2019 02:57:10 +0000 (02:57 +0000)]
gallium-xlib: query MIT-SHM before using it.
When Mesa is compiled for gallium-xlib using e.g.
./configure --enable-glx=gallium-xlib --disable-dri --disable-gbm
-disable-egl
and is used by an X server (usually remotely via SSH X11 forwarding)
that does not support MIT-SHM such as XMing or MobaXterm, OpenGL
clients report error messages such as
Xlib: extension "MIT-SHM" missing on display "localhost:11.0".
ad infinitum.
The reason is that the code in src/gallium/winsys/sw/xlib uses
MIT-SHM without checking for its existence, unlike the code
in src/glx/drisw_glx.c and src/mesa/drivers/x11/xm_api.c.
I copied the same check using XQueryExtension, and tested with
glxgears on MobaXterm.
This issue was reported before here:
https://lists.freedesktop.org/archives/mesa-users/2016-July/001183.html
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
a203eaa4f4fb672b95426289b8dad3a8998f92d7)
Emil Velikov [Tue, 12 Feb 2019 21:07:17 +0000 (21:07 +0000)]
cherry-ignore: nv50,nvc0: add explicit settings for recent caps
stable Explicit 19.0 only nomination.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Marek Olšák [Thu, 24 Jan 2019 00:48:26 +0000 (19:48 -0500)]
meson: drop the xcb-xrandr version requirement
autotools doesn't have any requirement. This fixes meson on Ubuntu 16.04.
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit
1e85cfb91a08565f28f51cc19573324722765823)
Jason Ekstrand [Tue, 15 Jan 2019 16:53:44 +0000 (10:53 -0600)]
intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode
Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions. If you have a SIMD8 instruction in a SIMD16 shader,
neither would trigger and the restriction could still be hit.
Fixes:
232ed8980217dd "i965/fs: Register allocator shoudn't use grf127..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
b4f0d062cd12b4f675bac900ac41d1085a79239a)
Ernestas Kulik [Thu, 30 Aug 2018 16:02:46 +0000 (19:02 +0300)]
v3d: Fix leak in resource setup error path
Reported by Coverity: in the case of unsupported modifier request, the
code does not jump to the “fail” label to destroy the acquired resource.
CID:
1435704
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Fixes:
45bb8f295710 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.")
(cherry picked from commit
90458bef544ac46a912f06e73f71c3cb20fdaaf6)
Ernestas Kulik [Thu, 30 Aug 2018 16:02:47 +0000 (19:02 +0300)]
vc4: Fix leak in HW queries error path
Reported by Coverity: in the case where there exist hardware and
non-hardware queries, the code does not jump to err_free_query and leaks
the query.
CID:
1430194
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Fixes:
9ea90ffb98fb ("broadcom/vc4: Add support for HW perfmon")
(cherry picked from commit
f6e49d5ad0fde19a074644491475470d684dd721)
Jason Ekstrand [Wed, 31 Oct 2018 15:18:21 +0000 (10:18 -0500)]
intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()
Like all the other sends, it's just mlen * REG_SIZE.
Fixes:
3cbc02e4693 "intel: Use TXS for image_size when we have..."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
cf42b0f9e2d2d612f92b24ec8a5a77ff107b92ab)
Rob Clark [Tue, 29 Jan 2019 17:23:28 +0000 (12:23 -0500)]
freedreno: stop frob'ing pipe_resource::nr_samples
Previously we tried to normalize nr_samples to MAX2(1, nr_samples) to
avoid having to deal with 0 vs 1 everywhere. But this causes problems
in mesa/st, for example st_finalize_texture() will think there is a
nr_samples mismatch and recreate the texture. Somehow this manifests
as corrupt x11 font rendering on generations that do not support MSAA
(but apparently works fine on a5xx and a6xx which do support MSAA.)
Fixes:
cf0c7258ee0 freedreno/a5xx: MSAA
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
c3baa077bf6db9f9d46be62ed7cbbc3167e68c8f)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/drivers/freedreno/freedreno_batch_cache.c
Emil Velikov [Thu, 31 Jan 2019 21:08:36 +0000 (21:08 +0000)]
docs: add sha256 checksums for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 31 Jan 2019 20:58:09 +0000 (20:58 +0000)]
docs: add release notes for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Danylo Piliaiev [Thu, 10 Jan 2019 16:16:59 +0000 (18:16 +0200)]
glsl: Fix copying function's out to temp if dereferenced by array
Function's out variable could be an array dereferenced by an array:
func(v[w[i]]);
or something more complicated.
Copy index in any case.
Fixes:
76c27e47b906 ("glsl: Copy function out to temp if we don't directly ref a variable")
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
0862929bf64222e85e8242824aecf05e494c157c)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109488
Nominated-by: Matt Turner <mattst88@gmail.com>
Timothy Arceri [Mon, 9 Apr 2018 04:40:40 +0000 (14:40 +1000)]
glsl: Copy function out to temp if we don't directly ref a variable
Otherwise we can end up with IR that looks like this:
(
(declare (temporary ) vec4 f@8)
(assign (xyzw) (var_ref f@8) (var_ref f) )
(call f16 ((swiz y (var_ref f@8) )))
(assign (xyzw) (var_ref f) (var_ref f@8) )
))
When we really need:
(declare (temporary ) float inout_tmp)
(assign (x) (var_ref inout_tmp) (swiz y (var_ref f) ))
(call f16 ((var_ref inout_tmp) ))
(assign (y) (var_ref f) (swiz y (swiz xxxx (var_ref inout_tmp) )))
(declare (temporary ) void void_var)
The GLSL IR function inlining code seemed to produce correct code
even without this but we need the correct IR for GLSL IR -> NIR to
be able to understand whats going on.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
76c27e47b90647df047e785d6b3ab5d0d979a1ee)
Nominated-by: Matt Turner <mattst88@gmail.com>
Tomeu Vizoso [Mon, 17 Dec 2018 08:56:00 +0000 (09:56 +0100)]
etnaviv: Consolidate buffer references from framebuffers
We were leaking surfaces because the references taken in
etna_set_framebuffer_state weren't being released on context destroy.
Instead of just directly releasing those references in
etna_context_destroy, use the util_copy_framebuffer_state helper.
Take the chance to remove the duplicated buffer references in
compiled_framebuffer_state to avoid confusion.
The leak can be reproduced with a client that continuously creates and
destroys contexts.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reported-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit
bf1dfcc3e8120400c9a78d03dd914a786728b5f7)
[Emil: resolve trivial conflict - dummy_rt does not exist in branch]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/drivers/etnaviv/etnaviv_context.c
Eric Anholt [Mon, 28 Jan 2019 19:39:12 +0000 (11:39 -0800)]
vc4: Enable NEON asm on meson cross-builds.
The core Mesa with_asm_arch and USE_ARM_ASM flags are disabled for meson
cross-builds because of the need to run host binaries on the build system.
vc4 doesn't need to do that, so skip with_asm_arch to enable NEON on my
cross-builds.
Fixes:
ebcb4c2156e9 ("meson: Enable VC4's NEON assembly support.")
(cherry picked from commit
932ed9c00b99e6ec92146ec9e820f546cf3e6551)
Vinson Lee [Sat, 26 Jan 2019 08:21:06 +0000 (00:21 -0800)]
meson: Fix typo.
meson.build:166:21: ERROR: Unknown method "verson_compare" for a string.
Fixes:
c1efa240c91e ("meson: Add warnings and errors when using ICC")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
be5b271ea76d81d32e3dc490ef5b32a61c3fb965)
Carsten Haitzler (Rasterman) [Tue, 8 Jan 2019 16:28:30 +0000 (16:28 +0000)]
vc4: Declare the cpu pointers as being modified in NEON asm.
Otherwise, the compiler is free to reuse the register containing the input
for another call and assume that the value hasn't been modified. Fixes
crashes on texture upload/download with current gcc.
We now have to have a temporary for the cpu2 value, since outputs must be
lvalues.
(commit message by anholt)
Fixes:
4d30024238ef ("vc4: Use NEON to speed up utile loads on Pi2.")
(cherry picked from commit
300d3ae8b1445b5060f92c77c0f577f4b7b2c7d6)
[Emil: apply the patch to vc4_tiling_lt.c instead of v3d_cpu_tiling.h]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/broadcom/common/v3d_cpu_tiling.h
Squashed with commit:
vc4: Declare the last cpu pointer as being modified in NEON asm.
Earlier commit addressed 7 of the 8 instances available.
v2: Rebase patch back to master (by anholt)
Cc: Carsten Haitzler (Rasterman) <raster@rasterman.com>
Cc: Eric Anholt <eric@anholt.net>
Fixes:
300d3ae8b14 ("vc4: Declare the cpu pointers as being modified in NEON asm.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
385843ac3ce1b868d9e24fcb2dbc0c8d5f5a7c99)
Conflicts:
src/broadcom/common/v3d_cpu_tiling.h
Carsten Haitzler (Rasterman) [Tue, 29 Jan 2019 16:55:30 +0000 (16:55 +0000)]
vc4: Use named parameters for the NEON inline asm.
This makes the asm code more intelligible and clarifies the functional
change in the next commit.
(commit message and commit squashing by anholt)
(cherry picked from commiti
522f68847152e9111def094f7fb35b44f3d0fc80)
[Emil: apply the patch to vc4_tiling_lt.c instead of v3d_cpu_tiling.h]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/broadcom/common/v3d_cpu_tiling.h
Timothy Arceri [Mon, 28 Jan 2019 06:15:34 +0000 (17:15 +1100)]
glsl: use remap location when serialising uniform program resource data
This allows us to avoid expensive string compares since we already have
a map to the pointers.
These compares were taking ~30 seconds for a single shader compile
in Godot due to it using 64,000+ uniforms.
Fixes:
c4cff5f40254 ("glsl: add basic support for resource list to shader cache")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109229
(cherry picked from commit
fb78a6cb72270de271f75d6f6c9b5ebadba7a898)
Timothy Arceri [Thu, 24 Jan 2019 05:02:17 +0000 (16:02 +1100)]
radv/ac: fix some fp16 handling
Fixes:
b722b29f10d4 ("radv: add support for 16bit input/output")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
0907ae35ad0e7733535516fada04948ea7125291)
Niklas Haas [Thu, 22 Nov 2018 23:32:29 +0000 (00:32 +0100)]
radv: correctly use vulkan 1.0 by default
From the vulkan spec 3.2 "Instances":
"Providing a NULL VkInstanceCreateInfo::pApplicationInfo or providing an
apiVersion of 0 is equivalent to providing an apiVersion of
VK_MAKE_VERSION(1,0,0)."
Fixes:
ffa15861ef7c924a33e1f "radv: UseEnumerateInstanceVersion for the default version."
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
d12dc3939620dcc942523a30a7fcc3271e751a6c)
Axel Davy [Tue, 22 Jan 2019 19:14:43 +0000 (20:14 +0100)]
st/nine: Immediately upload user provided textures
Fixes regression caused by
42d672fa6a766363e5703f119607f7c7975918aa
st/nine: Bind src not dst in nine_context_box_upload
Before that patch, for user provided textures,
when the texture was destroyed, the safety
check for pending uploads, which according to
the code "Following condition cannot happen currently",
was flushing the queue and thus triggering the upload.
After the patch, the texture destruction was delayed after
the upload. However the user frees the texture buffer,
as it thinks the texture released.
Instead of reverting the faulty patch,
this patch instead flushes the csmt queue right away
after queuing the upload for this type of textures.
This is more future-proof, as we may want to bind the
surface for other reasons in the future.
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
d7433c22e6c9624ca5275a3cd35be79caed9fffc)
Dylan Baker [Mon, 14 Jan 2019 23:23:41 +0000 (15:23 -0800)]
meson: Add warnings and errors when using ICC
ICC tries to be helpful by not erroring when it sees something that it
doesn't understand, which is completely the opposite of helpful. Meson
0.49.0 does much better at handling this by really trying to make ICC
error, but there are some things in mesa that still get ignored until
0.49.1
v2: - Fix id check, which is 'intel' not 'icc'
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
(cherry picked from commit
c1efa240c91e78385e8e433af134289b006016d0)
Lionel Landwerlin [Thu, 17 Jan 2019 18:19:59 +0000 (18:19 +0000)]
anv: fix invalid binding table index computation
The ++ operator strikes again.
Fixes:
f92c5bc8f3f517 ("anv/device: fix maximum number of images supported")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
4149d41f2e4ea02ca86975d25ab160e69bf0f8e5)
Emil Velikov [Tue, 29 Jan 2019 15:38:06 +0000 (15:38 +0000)]
cherry-ignore: WARNING: Commit XXX lists invalid sha
warn The commits refer stale sha, yet don't fix anything in particular.
98984b7cdd79c15cc7331c791f8be61e873b8bbd
9f86f1da7c68b5b900cd6f60925610ff1225a72d
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Timothy Arceri [Wed, 23 Jan 2019 03:58:40 +0000 (14:58 +1100)]
ac/nir_to_llvm: fix clamp shadow reference for more hardware
Fixes the following piglit test on my VEGA and matches the behaviour in the
tgsi backend.
tests/spec/glsl-1.10/execution/samplers/glsl-fs-shadow2D-clamp-z.shader_test
Fixes:
625dcbbc4566 ("amd/common: pass address components individually to ac_build_image_intrinsic")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
5d66f7103f0df6b996951e65483fc5873d9b66df)
Eric Engestrom [Tue, 11 Dec 2018 16:51:25 +0000 (16:51 +0000)]
meson/vdpau: add missing soversion
This mirrors what autotools does in src/gallium/state_trackers/vdpau/Makefile.am
and src/gallium/targets/vdpau/Makefile.am:
VDPAU_MAJOR = 1
VDPAU_MINOR = 0
libvdpau_gallium_la_LDFLAGS = -version-number $(VDPAU_MAJOR):$(VDPAU_MINOR)
Reported-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Fixes:
68076b87474e7959c161 "meson: build gallium vdpau state tracker"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
69e944036720d826d0548a019f8fe18b9ed57e6e)
Dylan Baker [Mon, 14 Jan 2019 23:15:09 +0000 (15:15 -0800)]
meson: Fix compiler checks for SWR with ICC
This is a bit fragile, as the way this "fixes" the check is to move the
one that we know is correct before the one that is incorrectly reported
as working. In meson 0.49.1 (which isn't out yet) this is fixed that the
incorrect check is reported as a failure.
Fixes:
e0b037d6979b266d4959c1e31746d4d19c941fdb
("meson: Build SWR driver")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109129
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
7cb7f35bc76bf21d15ca4b1f4ee724e9ff1e2804)
Dylan Baker [Mon, 14 Jan 2019 22:44:30 +0000 (14:44 -0800)]
meson: fix swr KNL build
There's a typo in one of the #defines that breaks compilation.
Fixes:
e0b037d6979b266d4959c1e31746d4d19c941fdb
("meson: Build SWR driver")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109023
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
3ba7ab8d2c8454346c3349ddc56cb480eea4f958)
Dave Airlie [Thu, 27 Dec 2018 04:26:49 +0000 (14:26 +1000)]
gallium: use put image shm2 path (v2)
This fixes the drisw paths to use the new shm2 interface, so that
we don't trigger the X server overflow checks when the x offset is non-zero.
This just hides the versioning in drisw, and either passes the src_x
or adds the offset fixup for the fallback path.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit
1f6b92b47652e7f48f03ef6a4228a19537022d23)
Dave Airlie [Thu, 27 Dec 2018 04:26:33 +0000 (14:26 +1000)]
glx: add support for putimageshm2 path (v2)
v2: pass x,0 in as the offset coords at glx level not earlier
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit
00af91ca463a2486c043c635d94d9958fb1e8700)
Dave Airlie [Thu, 27 Dec 2018 04:26:04 +0000 (14:26 +1000)]
dri_interface: add put shm image2 (v2)
This adds a new interface to the swrast interface to fix an shm put image bug.
The current code adds the x,y src offsets into the offset parameters,
however if the x offset is > 0, and the put image copies up to the height
of the image, this can trigger an X server validation check to fail and
the renderering to get BadMatch.
This patch fixes it to pass the x offset coord in as a src x.
We cannot pass the Y coordinate due to the horrible code mangling the
image w/h vs stride in swrastXPutImage.
v2: drop srcx,y from api
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit
db83a2b40f95fa3b9a741e9797dbf3e18f065a71)
Marek Olšák [Mon, 21 Jan 2019 17:09:07 +0000 (12:09 -0500)]
st/mesa: purge framebuffers when unbinding a context
This fixes pipe_surface "leaks".
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
c89e8470e58066637c4bfd5c76a2247eb3608b8b)
Rob Clark [Tue, 22 Jan 2019 19:08:41 +0000 (14:08 -0500)]
loader: fix the no-modifiers case
Normally modifiers take precendence over use flags, as they are more
explicit. But if the driver supports modifiers, but the xserver does
not, then we should fallback to the old mechanism of allocating a buffer
using 'use' flags.
Fixes:
069fdd5f9facbd72fb6a289696c7b74e3237e70f
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
(cherry picked from commit
c56fe4118a2dd991ff1b2a532c0f234eddd435e9)
Marek Olšák [Thu, 10 Jan 2019 19:32:42 +0000 (14:32 -0500)]
radeonsi: fix rendering to tiny viewports where the viewport center is > 8K
This fixes an assertion failure with GL CTS when cts-runner is used.
(not a specific test)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108877
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
4c4c8bb1f047234d738ab9bb70938bee4733ed2e)
Marek Olšák [Fri, 11 Jan 2019 20:11:30 +0000 (15:11 -0500)]
radeonsi: fix a u_blitter crash after a shader with FBFETCH
This fixes an assertion failure with GL CTS when cts-runner is used.
(not a specific test)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108877
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
caa2dcd7309311c3f707b1855c7e30c1c72818e2)
Jason Ekstrand [Thu, 6 Dec 2018 22:49:27 +0000 (16:49 -0600)]
nir/xfb: Fix offset accounting for dvec3/4
Before, we were double-counting the component slots when we had a dvec3
or dvec4. Instead, just add them in once and manually offset the
recorded output offset.
Fixes:
19064b8c "nir: Add a pass for gathering transform feedback info"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit
4f99ac9144abda9b4e7d0891571eb1691b853c25)
Eric Engestrom [Mon, 21 Jan 2019 19:44:45 +0000 (19:44 +0000)]
configure: EGL requirements only apply if EGL is built
Issue was hit with this configuration:
--disable-{egl,gbm} --with-platform=drm
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes:
3208fd2e46b ("configure: move platform handling further up")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
610f956fdead37da49ee2857a2261c3dfd8fc3cd)
Jason Ekstrand [Sat, 19 Jan 2019 15:40:12 +0000 (09:40 -0600)]
anv: Only parse pImmutableSamplers if the descriptor has samplers
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
c7f4a2867ce492d78c1f8e2870c0a593d280572d)
Karol Herbst [Fri, 18 Jan 2019 13:13:25 +0000 (14:13 +0100)]
glsl/lower_output_reads: set invariant and precise flags on temporaries
fixes a couple of deqp tests (on nvc0 and potential other drivers):
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_3
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_3
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_3
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
987744be9850bfe3a7c3c9556ae5d48ee5c34352)
Timothy Arceri [Thu, 10 Jan 2019 04:54:43 +0000 (15:54 +1100)]
ac/nir_to_llvm: fix interpolateAt* for arrays
This builds on the recent interpolate fix by Rhys
ee8488ea3b99.
This fixes the arb_gpu_shader5 interpolateAt* tests that contain
arrays.
Fixes:
ee8488ea3b99 ("ac/nir,radv,radeonsi/nir: use correct indices for interpolation intrinsics")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
9e669ed22b52857495593b92537d53c9ead7d424)
Karol Herbst [Thu, 17 Jan 2019 22:32:19 +0000 (23:32 +0100)]
nv50/ir: disable tryCollapseChainedMULs in ConstantFolding for precise instructions
fixes dEQP-GLES2.functional.shaders.invariance.mediump.loop_3
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
30b5c9eda2fe4c335cc15cb921e4f7774af0879e)
Bas Nieuwenhuizen [Thu, 17 Jan 2019 18:54:20 +0000 (19:54 +0100)]
nir: Account for atomics in copy propagation.
Otherwise writes get propagated across atomics if no barrier is
used. Without barrier writes should still be visible in the same
invocation, so an atomic has to be considered a write.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Fixes:
b3c61469255 "nir: Copy propagation between blocks"
Fixes:
62332d139c8 "nir: Add a local variable-based copy propagation pass"
(cherry picked from commit
8424cd8fbd1671c4c13f57cfa34bf8145d0fffcf)
Iago Toral Quiroga [Thu, 10 Jan 2019 12:34:07 +0000 (13:34 +0100)]
anv/device: fix maximum number of images supported
We had defined MAX_IMAGES as 8, which we used to size the array for
image push constant data. The comment there stated that this was for
gen8, but anv_nir_apply_pipeline_layout runs for all gens and writes
that array, asserting that we don't exceed that number of images,
which imposes a limit of MAX_IMAGES on all gens.
Furthermore, despite this, we are exposing up to 64 images per shader
stage on all gens, gen8 included.
This patch lowers the number of images we expose in gen8 to 8 and
keeps 64 images for gen9+ while making sure that only pre-SKL gens
use push constant space to handle images.
v2:
- <= instead of < in the assert (Eric, Lionel)
- Change the way the assertion is written (Eric)
v3:
- Revert the way the assertion is written to the form it had in v1,
the version in v2 was not equivalent and was incorrect. (Lionel)
v4:
- gen9+ doesn't need push constants for images at all (Jason)
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v3)
(cherry picked from commit
f92c5bc8f3f517f3dadab27c5fcf28a6c2747204)
Jason Ekstrand [Wed, 21 Nov 2018 23:19:37 +0000 (17:19 -0600)]
anv/nir: Rework arguments to apply_pipeline_layout
Instead of taking a whole pipeline (which could be anything!), just take
a physical device and robust_buffer_access boolean. This makes it
easier to verify that only the things in the hash actually affect
pipeline compilation.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
a24654b49d36609b43a5ef6f04453ab284a6ea4f)
Eric Anholt [Wed, 16 Jan 2019 00:02:23 +0000 (16:02 -0800)]
vc4: Don't leak the GPU fd for renderonly usage.
Noticed while debugging V3D -- the ro->gpu_fd was freshly opened in ro
setup, and it needs to stay open until screen close (since it may be used
by renderonly) and should be the same one used by the vc4 screen.
Fixes:
7029ec05e2c7 ("gallium: Add renderonly-based support for pl111+vc4.")
(cherry picked from commit
99ef66c325a99b3e191987d8327e7e4cd4aafcd7)
Dylan Baker [Tue, 15 Jan 2019 19:55:36 +0000 (11:55 -0800)]
meson: allow building dri driver without window system if osmesa is classic
This was already enabled for gallium based osmesa with gallium drivers
in
9d10581897ef7cfa0f6c392e2048cc04357281b9, so do the same for classic
driver with classic osmesa.
Fixes:
cbbd5bb889a2c271a504c379f36a7cb717a85af4
("meson: build classic osmesa")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit
431e9abaaba6386aa7fbc1ec0e2566a3f8999f5d)
Bruce Cherniak [Fri, 4 Jan 2019 20:53:59 +0000 (14:53 -0600)]
gallium/swr: Fix multi-context sync fence deadlock.
Various recreation scenarios lead to API thread getting stuck in
swr_fence_finish(). This is a multi-context issue, whereby one context
overwrites the fence read-value with a previous sync's lesser value.
The fence sync value is supposed to be always increasing.
In swr_fence_cb(), only update the "read" value if the new value is
greater.
(This may seem like we're not waiting on the other context to finish, but
had we needed for it to finish there would have been a wait prior to
submitting a new sync.)
cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
ed7673afd2d1a31bfcec0520743acd2681b462e6)
Pierre Moreau [Wed, 9 Jan 2019 22:03:45 +0000 (23:03 +0100)]
meson: Fix with_gallium_icd to with_opencl_icd
`with_gallium_icd` is never used throughout the different Meson build
files, whereas `with_opencl_icd` tracks whether or not `gallium-opencl`
was set to "icd".
Fixes:
42ea0631f108d82554339530d6c88aa1b448af1e
("meson: build clover")
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
0b736f7fd4852bdea2ac6be9a018a41065252233)
Bas Nieuwenhuizen [Sat, 12 Jan 2019 19:09:23 +0000 (20:09 +0100)]
radv: Set partial_vs_wave for pipelines with just GS, not tess.
Looking at -pro we need to enable it for pipelines with just a
GS too.
This seems to reduce the hangs from
https://bugs.freedesktop.org/show_bug.cgi?id=109242 on a RX 550 to
the point where I can't reproduce, after the false start with the
wd_switch_on_eop patch due to flakiness.
(but people are reporting it does not fix the issue completely for
them on polaris 11)
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
568e7a2998e39263c41ec70ec67bcc5601477781)
Samuel Pitoiset [Thu, 8 Nov 2018 13:00:36 +0000 (14:00 +0100)]
radv: clean up setting partial_es_wave for distributed tess on VI
Only needed when the pipeline actually uses tessellation. I don't
think that changes anything, except improving readability.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
d9d14346c2ba66bfef7ca120ccbcd3201ca32359)
Marek Olšák [Mon, 14 Jan 2019 23:24:08 +0000 (18:24 -0500)]
radeonsi: also apply the GS hang workaround to draws without tessellation
ported from AMDVLK.
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
5183e794affbbbf7dc959332619b0852c21536d6)
Bas Nieuwenhuizen [Mon, 14 Jan 2019 13:44:15 +0000 (14:44 +0100)]
radv: Only use 32 KiB per threadgroup on Stoney.
Causes hangs on some machines.
What works for dEQP-VK.tessellation.shader_input_output.barrier:
- running num_patches = 6 (which limits LDS to 32 KiB)
- running num_patches = 8, and artificially cutting LDS size at 32 KiB.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
76b12fa564a5f48e3f2264718dea0158d0c05b4c)
Andres Gomez [Fri, 11 Jan 2019 14:43:27 +0000 (16:43 +0200)]
bin/get-pick-list.sh: fix redirection in sh
"&>" is bash specific.
Fixes:
e0dbfc99537 ("bin/get-pick-list.sh: warn when commit lists invalid sha")
Cc: Juan A. Suarez <jasuarez@igalia.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit
3ec9ab80b870efffb5ba7c7a00b86b2df729ec6d)
Andres Gomez [Fri, 11 Jan 2019 14:42:25 +0000 (16:42 +0200)]
bin/get-pick-list.sh: fix the oneline printing
"--summary" will also print extended header information such as
creations, renames and mode changes.
Let's just use "--no-patch", which suppresses the diff output.
v2: Use "--no-patch" instead of the "-s" abbreviation (Eric).
Fixes:
559c32d2412 ("bin/get-pick-list.sh: simplify git oneline printing")
Cc: Juan A. Suarez <jasuarez@igalia.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit
716ed41a36037459ed5bfe0775484ac2cbd90707)
Emil Velikov [Tue, 29 Jan 2019 15:10:34 +0000 (15:10 +0000)]
cherry-ignore: spirv: Handle arbitrary bit sizes for deref array indices
stable The commits aren't suitable in their present form.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Tue, 29 Jan 2019 14:58:15 +0000 (14:58 +0000)]
cherry-ignore: radv: Fix multiview depth clears
fixes: This commit requires commits
aeaf8dbd097 and
7484bc894b9 which
did not land in branch.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 17 Jan 2019 11:30:49 +0000 (11:30 +0000)]
docs: add sha256 checksums for 18.3.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>