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Jason Ekstrand [Fri, 16 Sep 2016 04:12:34 +0000 (21:12 -0700)]
nir/spirv/cfg: Use a nop intrinsic for tagging the ends of blocks
Previously, we were saving off the last nir_block in a vtn_block before
moving on so that we could find the nir_block again when it came time to
handle phi sources. Unfortunately, NIR's control flow modification code is
inconsistent when it comes to how it splits blocks so the block pointer we
saved off may point to a block somewhere else in the shader by the time we
get around to handling phi sources. In order to get around this, we insert
a nop instruction and use that as the logical end of our block. Since the
control flow manipulation code respects instructions, the nop will keeps
its place like any other instruction and we can easily find the end of our
block when we need it.
This fixes a bug triggered by a couple of vkQuake shaders.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97233
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Tested-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Fri, 16 Sep 2016 04:02:37 +0000 (21:02 -0700)]
nir: Add a nop intrinsic
This intrinsic has no destination, no sources, no variables, and can be
eliminated. In other words, it does nothing and will always get deleted by
dead code elimination. However, it does provide a quick-and-easy way to
temporarily tag a particular location in a NIR shader.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 13 Sep 2016 00:56:38 +0000 (17:56 -0700)]
intel/isl: Allow non-2D HiZ surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 22:45:18 +0000 (15:45 -0700)]
intel/isl: Add a detailed comment about multisampling with HiZ
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 05:25:50 +0000 (22:25 -0700)]
intel/isl: Remove tiling checks from choose_msaa_layout
We already do those checks in filter_tiling. There's no good reason to
repeat them in choose_msaa_layout. If anything they should have been
asserts and not "return false" checks. Also, this check was causing us to
outright reject multisampled HiZ surfaces which wasn't intended.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 05:01:47 +0000 (22:01 -0700)]
intel/isl: Handle HiZ and CCS tiling more directly
The HiZ and CCS tiling formats are always used for HiZ and CCS surfaces
respectively. There's no reason why we should go through filter_tiling and
it's much easier to always get HiZ and CCS right if we just handle them
directly.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 01:57:18 +0000 (18:57 -0700)]
intel/isl: Allow multisampling with ISL_FORMAT_HiZ
HiZ buffers can be multisampled and, on Broadwell and earlier, simply using
interleaved multisampling with a compression block size of 8x4 samples
yields the correct HiZ surface size calculations. Unfortunately,
choose_msaa_layout was rejecting multisampled HiZ buffers because of format
checks. Now that we have a simple helper for determining if a format
supports multisampling, that's an easy enough issue to fix.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Tue, 13 Sep 2016 00:43:28 +0000 (17:43 -0700)]
intel/isl: Allow creation of 1-D compressed textures
Compressed 1-D textures are not well-defined thing in either GL or Vulkan.
However, auxiliary surfaces are treated as compressed textures in ISL and
we can do HiZ and CCS with 1-D so we need to be able to create them. In
order to prevent actually using them (the docs say no), we assert in the
state setup code.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 02:52:38 +0000 (19:52 -0700)]
intel/isl: Fix up asserts in calc_phys_level0_extent_sa
The assertion that a format is uncompressed in the multisample layouts
isn't quite right. What we really want to assert is that the format
supports multisampling which is a bit more complicated query. We also want
to assert that it has a block size of 1x1 since we do nothing with the
block size in the phys_level0_sa assignment.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 01:57:01 +0000 (18:57 -0700)]
intel/isl: Add a format_supports_multisampling helper
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Nayan Deshmukh [Sat, 1 Oct 2016 05:22:52 +0000 (10:52 +0530)]
vl/dri3: fix warning about incompatible pointer type
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Bruce Cherniak [Tue, 27 Sep 2016 18:27:08 +0000 (13:27 -0500)]
swr: Removed stalling SwrWaitForIdle from queries.
Previous fundamental change in stats gathering added a temporary
SwrWaitForIdle to begin_query and end_query. Code has been reworked to
remove stall.
Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
Tim Rowley [Fri, 30 Sep 2016 21:05:19 +0000 (16:05 -0500)]
swr: [rasterizer core] refactor thread creation
Create worker pool now computes number of worker threads based on
things like topologies, etc. and creates the pool but doesn't actually
launch the threads. Instead there is a separate start thread pool
function. This allows thread resources to be constructed first before
threads start.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Fri, 30 Sep 2016 20:18:13 +0000 (15:18 -0500)]
swr: [rasterizer jitter] canonicalize blend compile state
Canonicalize to prevent unnecessary JIT compiles.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Thu, 22 Sep 2016 23:00:47 +0000 (18:00 -0500)]
swr: [rasterizer core] archrast fixes
- Immediately sleep threads until thread data is initialized
- Fix some compile bugs with AR enabled
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Tue, 20 Sep 2016 22:14:54 +0000 (17:14 -0500)]
swr: [rasterizer jitter] fixes for icc in vs2015 compat mode
- Move most jitter functionality into SwrJit namespace
- Avoid global "using namespace llvm" in headers
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 21 Sep 2016 18:39:44 +0000 (13:39 -0500)]
swr: [rasterizer core] generalize compute dispatch mechanism
Generalize compute dispatch mechanism to support other types of dispatches.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 21 Sep 2016 04:55:24 +0000 (23:55 -0500)]
swr: [rasterizer common] os.h portability header changes
- Fix conflict between windows MemoryFence and llvm::sys::MemoryFence
- Declare gettid()
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Ville Syrjälä [Fri, 30 Sep 2016 20:00:22 +0000 (23:00 +0300)]
anv/formats: Fix build on gcc-4 and earlier
gcc-4 and earlier don't allow compound literals where a constant
is required in -std=c99/gnu99 mode, so we can't use ISL_SWIZZLE()
when populating the anv_formats[] array. There are a few ways around
it: First one would be -std=c89/gnu89, but the rest of the code
depends on c99 so it's not really an option. The second option
would be to upgrade to gcc-5+ where the compiler behaviour was relaxed
a bit [1]. And the third option is just to avoid using compound
literals. I chose the last option since it keeps gcc-4 and earlier
working.
[1] https://gcc.gnu.org/gcc-5/porting_to.html
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Topi Pohjolainen <topi.pohjolainen@intel.com>
Fixes:
7ddb21708c80 ("intel/isl: Add an isl_swizzle structure and use it for isl_view swizzles")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tapani Pälli [Mon, 26 Sep 2016 07:03:32 +0000 (10:03 +0300)]
egl: stop claiming support for pbuffer + msaa
This fixes a crash in egl-create-msaa-pbuffer-surface Piglit test
and same crash in many dEQP EGL tests.
I also found that some Qt example did a workaround because of this
crash: https://bugreports.qt.io/browse/QTBUG-47509
v2: Ian pointed out that v1 removed support for all multisample
configs, including window ones. This one removes pbuffer bit
when adding configs, now only pbuffer+msaa gets rejected and
window+msaa continues to work. Fixed also comment (Emil)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Sun, 2 Oct 2016 23:39:29 +0000 (10:39 +1100)]
i965: rename max_ds_* variable to max_tes_*
Using consistent naming allows us to create macros more easily.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sun, 2 Oct 2016 23:39:28 +0000 (10:39 +1100)]
i965: rename max_hs_* variables to max_tcs_*
Using consistent naming allows us to create macros more easily.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Fri, 9 Sep 2016 07:12:58 +0000 (00:12 -0700)]
i965: Drop pointless stage == MESA_SHADER_FRAGMENT checks.
There's an assert right above this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Sat, 1 Oct 2016 01:45:22 +0000 (11:45 +1000)]
glsl: add missing headers to blob.h
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Jason Ekstrand [Sat, 17 Sep 2016 05:04:57 +0000 (22:04 -0700)]
nir/spirv/cfg: Detect switch_break after loop_break/continue
While the current CFG code is valid in the case where a switch break also
happens to be a loop continue, it's a bit suboptimal. Since hardware is
capable of handling the continue as a direct jump, it's better to use a
continue instruction when we can than to bother with all of the nasty
switch break lowering.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sat, 17 Sep 2016 04:55:08 +0000 (21:55 -0700)]
nir/spirv/cfg: Handle switches whose break block is a loop continue
It is possible that the break block of a switch is actually the continue of
the loop containing the switch. In this case, we need to identify the
break block as a continue and break out of current level of CFG handling.
If we don't, the continue portion of the loop will get handled twice, once
by following after the break and a second time by the loop handling code
handling it explicitly.
This fixes 6 of the new Vulkan CTS tests:
- dEQP-VK.spirv_assembly.instruction.graphics.opphi.out_of_order*
- dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order*
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Eric Engestrom [Sun, 25 Sep 2016 15:49:53 +0000 (16:49 +0100)]
nir/spirv: add spirv2nir binary to .gitignore
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Sun, 25 Sep 2016 15:49:52 +0000 (16:49 +0100)]
nir/spirv: improve mmap() error handling
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Sun, 25 Sep 2016 15:49:51 +0000 (16:49 +0100)]
nir/spirv: improve lseek() error handling
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Sun, 25 Sep 2016 15:49:50 +0000 (16:49 +0100)]
nir/spirv: add some error checking to open()
CovID:
1373369
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Fri, 30 Sep 2016 23:20:26 +0000 (09:20 +1000)]
mesa: use uint32_t rather than unsigned for xfb struct members
These structs will be written to disk as part of the shader cache
so use uint32_t just to be safe.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Timothy Arceri [Fri, 30 Sep 2016 06:37:03 +0000 (16:37 +1000)]
i915/i965: remove commented out warning
The warning was also the wrong location, it should have been
in the else.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 30 Sep 2016 16:25:05 +0000 (10:25 -0600)]
mesa: move _mesa_valid_to_render() to api_validate.c
Almost all of the other drawing validation code is in api_validate.c
so put this function there as well.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Steven Toth [Fri, 30 Sep 2016 11:58:00 +0000 (05:58 -0600)]
gallium/hud: Add support for CPU frequency monitoring
Detect all of the CPUs in the system. Expose metrics
for min, max and current frequency in Hz.
Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Fri, 30 Sep 2016 10:55:08 +0000 (12:55 +0200)]
Revert "gallium/hud: automatically print % if max_value == 100"
This reverts commit
dbfeb0ec12d6550e68de1bcd164e422e79bccf2d.
With max_value being rounded to 100, it's often wrong.
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Fri, 30 Sep 2016 13:18:13 +0000 (07:18 -0600)]
docs: update the list of Mesa major versions and API support
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Nicolai Hähnle [Fri, 30 Sep 2016 10:00:44 +0000 (12:00 +0200)]
gallium/radeon: fix crash/regression in performance counters
Regression introduced by "gallium/radeon: zero all query buffers".
Cc: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 29 Sep 2016 14:47:27 +0000 (16:47 +0200)]
gallium/radeon: update documentation of buffer_get_virtual_address
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 30 Sep 2016 09:46:47 +0000 (11:46 +0200)]
gallium/radeon: emit relocations for query fences
This is only needed for r600 which doesn't have ARB_query_buffer_object and
therefore wouldn't really need the fences, but let's be optimistic about
filling in this feature gap eventually.
Cc: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 29 Sep 2016 14:50:10 +0000 (16:50 +0200)]
radeon/uvd: adjust the buffer offset when relocation is used
We don't plan to use sub-allocated buffers with UVD, but just in case one
slips through, this increases the chances of things working out anyway.
Reviewed-by: Christian König <christian.koenig@amd.com>
Nicolai Hähnle [Thu, 29 Sep 2016 14:47:53 +0000 (16:47 +0200)]
radeon/vce: adjust the buffer offset when relocation is used
We don't plan to use sub-allocated buffers with VCE, but just in case one
slips through, this increases the chances of things working out anyway.
Reviewed-by: Christian König <christian.koenig@amd.com>
Nicolai Hähnle [Fri, 30 Sep 2016 09:26:13 +0000 (11:26 +0200)]
radeon/video: don't use sub-allocated buffers
Cc: Christian König <christian.koenig@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97976
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969
Reviewed-by: Christian König <christian.koenig@amd.com>
Steven Toth [Thu, 29 Sep 2016 14:11:00 +0000 (08:11 -0600)]
gallium/hud: Add power sensor support
Implement support for power based sensors, reporting units in
milli-watts and watts.
Also, minor cleanup - change the related if block to a switch.
Tested with two different power sensors, including the nouveau
'power1' sensors on a GTX950 card.
Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Samuel Pitoiset [Wed, 14 Sep 2016 21:02:38 +0000 (23:02 +0200)]
nv50/ir: teach insnCanLoad() about SHLADD
Commutativity is not allowed with SHLADD, but src2 can accept
loads. To allow the load propagation pass to do its job, add a
special case like for SUCLAMP because src1 is always an immediate.
This IMAD to SHLADD optimization helps a bunch of shaders from Tomb
Raider, Victor Vran, UE4 demos (+15% perf with Elemental) and Shadow
Warrior.
GF100/GK104:
total instructions in shared programs :
2838045 ->
2834712 (-0.12%)
total gprs used in shared programs :396684 -> 396386 (-0.08%)
total local used in shared programs :34416 -> 34416 (0.00%)
local gpr inst bytes
helped 0 326 1105 1105
hurt 0 55 3 3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 14 Sep 2016 20:15:14 +0000 (22:15 +0200)]
nv50/ir: optimize SHLADD(a, b, c) to MOV((a << b) + c)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 14 Sep 2016 16:57:02 +0000 (18:57 +0200)]
nv50/ir: optimize SHLADD(a, b, 0x0) to SHL(a, b)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 14 Sep 2016 16:49:36 +0000 (18:49 +0200)]
nv50/ir: optimize IMAD to SHLADD in presence of power of 2
Only and only if src1 is a power of 2 we can replace IMAD by SHLADD.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 14 Sep 2016 22:18:25 +0000 (00:18 +0200)]
nvc0/ir: add emission for SHLADD
Unfortunately, we can't use the emit helpers for GF100/GK110
because src1 and src2 are swapped.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 14 Sep 2016 14:42:45 +0000 (16:42 +0200)]
nv50/ir: add preliminary support for SHLADD
This instruction is available since SM20 (Fermi) and allow to do
(a << b) + c in one shot. In some situations, IMAD should be
replaced by SHLADD when b is a power of 2, and ADD+SHL should be
replaced by SHLADD as well.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Tue, 27 Sep 2016 20:08:11 +0000 (22:08 +0200)]
nvc0: update GM107 sched control codes format
envyas now uses a much better representation for those control
codes and it displays the different flags instead of an
unreadable hex number.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Nicolai Hähnle [Tue, 27 Sep 2016 14:52:42 +0000 (16:52 +0200)]
gallium/radeon: use smaller buffers for query results
Most of the time, even the 512 bytes that we now get is more than sufficient
(pipeline stats queries are the largest at 184 bytes per shot).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 27 Sep 2016 14:51:46 +0000 (16:51 +0200)]
gallium/radeon/winsyses: add radeon_winsys::min_alloc_size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 14 Sep 2016 07:43:42 +0000 (09:43 +0200)]
radeonsi: enable ARB_query_buffer_object (v2)
v2: enable only when compute is available
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 14 Sep 2016 10:00:50 +0000 (12:00 +0200)]
gallium/radeon: implement get_query_result_resource (v2)
v2: fix a comment (Gustaw Smolarczyk)
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 15 Sep 2016 13:58:36 +0000 (15:58 +0200)]
gallium/radeon: zero all query buffers
To ensure that fences are properly initialized.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 15 Sep 2016 10:18:24 +0000 (12:18 +0200)]
gallium/radeon: cleanup getting PIPE_QUERY_TIMESTAMP result
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 14 Sep 2016 08:38:33 +0000 (10:38 +0200)]
gallium/radeon: add query fences and r600_get_hw_query_params
We will support the waiting option in ARB_query_buffer_object using
WAIT_REG_MEM on an appropriate fence-like dword. Some queries conveniently
write their results with the highest bit set, and we can just use that;
for others, we have to write a fence explicitly.
ZPASS_DONE for occlusion queries writes its results with the high bit
set, but it writes up to 8 pairs of results (one for each DB). We have
to wait for all of these results, so let's just add an explicit fence.
The new function provides summary information to be used by subsequent
patches.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 14 Sep 2016 07:46:36 +0000 (09:46 +0200)]
radeonsi: add save_qbo_state
Save compute shader state that will be used for the ARB_query_buffer_object
implementation.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 14 Sep 2016 07:45:37 +0000 (09:45 +0200)]
radeonsi: add si_get_shader_buffers/get_pipe_constant_buffers (v2)
These functions extract the pipe state structure from the current
descriptors, for state saving.
v2: correctly dereference *buf (Bas)
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 14 Sep 2016 13:43:18 +0000 (15:43 +0200)]
gallium/radeon: add r600_gfx_{write,wait}_fence
For bottom-of-pipe fences inside the gfx command stream.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 15 Sep 2016 14:24:17 +0000 (16:24 +0200)]
gallium/radeon: add barrier_flags to r600_common_screen
There are driver-specific context flags for barriers that are not covered
by the Gallium barrier interfaces.
The R600 settings of these flags may not be optimal, but we're not going
to use them yet anyway.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 28 Sep 2016 06:04:09 +0000 (16:04 +1000)]
glsl: remove remaining tabs from ast_type.cpp
Acked-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Wed, 28 Sep 2016 06:04:08 +0000 (16:04 +1000)]
glsl: remove remaining tabs from ast_to_hir.cpp
Acked-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Wed, 28 Sep 2016 06:04:07 +0000 (16:04 +1000)]
glsl: remove remaining tabs from ast_array_index.cpp
Acked-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Wed, 28 Sep 2016 06:04:06 +0000 (16:04 +1000)]
glsl: remove tabs from ast_expr.cpp
Acked-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Wed, 28 Sep 2016 06:04:05 +0000 (16:04 +1000)]
glsl: remove tabs from linker.{cpp,h}
Acked-by: Dave Airlie <airlied@redhat.com>
Steven Toth [Wed, 28 Sep 2016 18:58:00 +0000 (12:58 -0600)]
gallium/hud: Add support for block I/O, network I/O and lmsensor stats
V8: Feedback based on peer review
convert if block into a switch
Constify some func args
V7: Increase precision when measuring lmsensors volts
Flatten patch series.
V6: Feedback based on peer review
Simplify sensor initialization (arg passing).
Constify some func args
V5: Feedback based on peer review
Convert sprintf to snprintf
Convert char * to const char *
int arg converted to bool
Func changes to take a filename vs a larger struct.
Omit the space between '*' and the param name.
V4: Merged with master as of 2016/9/27 6pm
V3: Flatten the entire patchset ready for the ML
V2: Additional seperate patches based on feedback
a) configure.ac: Add a comment related to libsensors
b) HUD: Disable Block/NIC I/O stats by default.
Implement configuration option --enable-gallium-extra-hud=yes
and enable both statistics when this option is enabled.
c) Configure.ac: Minor cleanup to user visible configuration settings
d) Configure.ac: HUD stats - build system improvements
Move the -lsensors out of a deeper Makefile, bring it into the configure.ac.
Also, rename a compiler directive to more closely follow the standard.
V1: Initial release to the ML
Three new features:
1. Disk/block I/O device read/write stats MB/ps.
2. Network Interface RX/TX transfer statistics as a percentage
of the overall NIC speed.
3. lmsensor power, voltage and temperature sensors.
The lmsensor changes makes a dependency on libsensors so support
for the change is opt out by default.
Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Ben Widawsky [Tue, 27 Sep 2016 22:02:12 +0000 (15:02 -0700)]
i965: Remove useless (harmful) assertion
The code already skips doing the depth stall on gen >= 8, and as we
enable new platforms this assertion will fail needlessly. Instead of
changing the caller, make this simple change.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Eric Anholt [Mon, 26 Sep 2016 23:14:51 +0000 (16:14 -0700)]
vc4: Emit perf debug when we fall back to quad clears.
Eric Anholt [Wed, 16 Mar 2016 01:32:19 +0000 (18:32 -0700)]
nir: Optimize out discard_ifs with a constant 0 argument.
I found this in a shader that was doing an alpha test when alpha is fixed
at 1.0.
v2: Rebase on master (now the const value is "u32" not "u").
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Michel Dänzer [Tue, 27 Sep 2016 09:17:12 +0000 (18:17 +0900)]
gallium/radeon: Initialize pipe_resource::next to NULL
Fixes lots of piglit tests crashing due to using uninitialized memory.
Fixes:
ecd6fce2611e ("mesa/st: support lowering multi-planar YUV")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Sun, 27 Mar 2016 05:25:12 +0000 (16:25 +1100)]
glsl: don't crash when dumping shaders if some come from cache
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Tue, 27 Sep 2016 22:55:02 +0000 (08:55 +1000)]
glsl: Add initial functions to implement an on-disk cache
This code provides for an on-disk cache of objects. Objects are stored
and retrieved via names that are arbitrary 20-byte sequences,
(intended to be SHA-1 hashes of something identifying for the
content). The directory used for the cache can be specified by means
of environment variables in the following priority order:
$MESA_GLSL_CACHE_DIR
$XDG_CACHE_HOME/mesa
<user-home-directory>/.cache/mesa
By default the cache will be limited to a maximum size of 1GB. The
environment variable:
$MESA_GLSL_CACHE_MAX_SIZE
can be set (at the time of GL context creation) to choose some other
size. This variable is a number that can optionally be followed by
'K', 'M', or 'G' to select a size in kilobytes, megabytes, or
gigabytes. By default, an unadorned value will be interpreted as
gigabytes.
The cache will be entirely disabled at runtime if the variable
MESA_GLSL_CACHE_DISABLE is set at the time of GL context creation.
Many thanks to Kristian Høgsberg <krh@bitplanet.net> for the initial
implementation of code that led to this patch. In particular, the idea
of using an mmapped file, (indexed by a portion of the SHA-1), for the
efficent implementation of cache_has_key was entirely his
idea. Kristian also provided some very helpful advice in discussions
regarding various race conditions to be avoided in this code.
Signed-off-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Chad Versace [Tue, 27 Sep 2016 20:22:44 +0000 (13:22 -0700)]
.gitignore: Ignore src/compiler/spirv2nir
Ian Romanick [Thu, 15 Sep 2016 18:11:12 +0000 (11:11 -0700)]
glsl: Fix cut-and-paste bug in hierarchical visitor ir_expression::accept
At this point in the code, s must be visit_continue. If the child
returned visit_stop, visit_stop is the only correct thing to return.
Found by inspection.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 7 Sep 2016 06:17:51 +0000 (23:17 -0700)]
glsl: Add bit_xor builder
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Thu, 15 Sep 2016 18:16:02 +0000 (11:16 -0700)]
glsl/standalone: Enable GLSL 4.00 through 4.50
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 14 Sep 2016 20:51:19 +0000 (13:51 -0700)]
glsl/standalone: Use API_OPENGL_CORE if the GLSL version is >= 1.40
Otherwise extensions to 1.40 that are only for core profile won't work.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 14 Sep 2016 22:14:22 +0000 (15:14 -0700)]
glsl: Update function parameter documentation for do_common_optimization
max_unroll_iterations was moved into options a long, long time ago.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tim Rowley [Thu, 21 Jul 2016 23:34:37 +0000 (18:34 -0500)]
configure.ac: add llvm inteljitevents component if enabled
Needed to successfully link llvmpipe or swr when using shared llvm libs
built with inteljitevents enabled.
v2: Make adding inteljitevents component global rather than just
llvmpipe/swr, since libgallium will have a symbol dependency.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tim Rowley [Tue, 20 Sep 2016 16:15:55 +0000 (11:15 -0500)]
swr: replace gallium->swr format enum conversion
Replace old string comparison with a mapping table.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Nicolai Hähnle [Mon, 12 Sep 2016 14:27:41 +0000 (16:27 +0200)]
gallium/radeon/winsyses: reduce the number of pb_cache buckets
Small buffers are now handled via the slabs code, so separate buckets in
pb_cache have become redundant.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 12 Sep 2016 10:19:47 +0000 (12:19 +0200)]
winsys/radeon: enable buffer allocation from slabs
Only enable for chips with GPUVM, because older driver paths do not take the
required offset into account.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 12 Sep 2016 09:46:12 +0000 (11:46 +0200)]
winsys/radeon: add fine-grained fences for slab buffers
Note the logic for adding fences is somewhat different than for amdgpu,
because radeon has no scheduler and we therefore have no guarantee about
the order in which submissions from multiple threads are processed.
(Ironically, this is only an issue when "multi-threaded submission" is
disabled, because "multi-threaded submission" actually means that all
submissions happen from a single thread that happens to be separate from
the application's threads. If we only supported "multi-threaded
submission", the fence handling could be simplified by adding the fences
in that thread where everything is serialized.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 12 Sep 2016 08:52:35 +0000 (10:52 +0200)]
winsys/radeon: add slab buffer list
Introducing radeon_bo::hash will reduce collisions between "real" buffers
and buffers from slabs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 9 Sep 2016 16:30:40 +0000 (18:30 +0200)]
winsys/radeon: separate adding a buffer from updating its reloc data
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 9 Sep 2016 13:21:03 +0000 (15:21 +0200)]
winsys/radeon: add slab entry structures to radeon_bo
Already adjust the map/unmap logic accordingly.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 7 Sep 2016 08:50:59 +0000 (10:50 +0200)]
winsys/amdgpu: enable buffer allocation from slabs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 8 Sep 2016 08:05:55 +0000 (10:05 +0200)]
winsys/amdgpu: add fence and buffer list logic for slab allocated buffers
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 7 Sep 2016 08:37:42 +0000 (10:37 +0200)]
winsys/amdgpu: add slab entry structures to amdgpu_winsys_bo
Already adjust amdgpu_bo_map/unmap accordingly.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 7 Sep 2016 09:01:17 +0000 (11:01 +0200)]
winsys/amdgpu: do not synchronize unsynchronized buffers
When a buffer is added to a CS without the SYNCHRONIZED usage flag, we now
no longer add a dependency on the buffer's fence(s).
However, we still need to add a fence to the buffer during flush, so that
cache reclaim works correctly (and in the hypothetical case that the buffer
is later added to a CS _with_ the SYNCHRONIZED flag).
It is now possible that the submissions refererring to a buffer are no longer
linearly ordered, and so we may have to keep multiple fences around. We keep
the fences in a FIFO. It should usually stay quite short (# of contexts * 2,
for gfx + dma rings).
While we're at it, extract amdgpu_add_fence_dependency for a single buffer,
which will make adding the distinction between real buffer and slab cases
easier.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 9 Sep 2016 09:49:18 +0000 (11:49 +0200)]
gallium/radeon: add RADEON_FLAG_HANDLE
When passed to winsys->buffer_create, this flag will indicate that we require
a buffer that maps 1:1 with a kernel buffer handle.
This is currently set for all textures, since textures can potentially be
exported to other processes. This is not a huge loss, since the main purpose
of this patch series is to deal with applications that allocate many small
buffers.
A hypothetical application with tons of tiny textures might still benefit
from not setting this flag, but that's not a use case I'm worried about
just now.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 7 Sep 2016 08:57:56 +0000 (10:57 +0200)]
gallium/radeon: add RADEON_USAGE_SYNCHRONIZED
This is really the behavior we want most of the time, but having a
SYNCHRONIZED flag instead of an UNSYNCHRONIZED one has the advantage that
OR'ing different flags together always results in stronger guarantees.
The parent BOs of sub-allocated buffers will be added unsynchronized.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 6 Sep 2016 12:43:00 +0000 (14:43 +0200)]
gallium/pipebuffer: add pb_slab utility
This is a simple framework for slab allocation from buffers that fits into
the buffer management scheme of the radeon and amdgpu winsyses where bufmgrs
aren't used.
The utility knows about different sized allocations and explicitly manages
reclaim of allocations that have pending fences. It manages all the free lists
but does not actually touch buffer objects directly, relying on callbacks for
that.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 6 Sep 2016 12:41:51 +0000 (14:41 +0200)]
gallium/u_math: add util_logbase2_ceil
For finding the exponent of the next power of two.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicholas Bishop [Thu, 8 Sep 2016 19:55:03 +0000 (15:55 -0400)]
i915g: add dma-buf support to i915_drm_buffer_get_handle
The implementation of i915_drm_buffer_get_handle now handles
DRM_API_HANDLE_TYPE_FD in the same way that intel_winsys_import_handle
does, by calling drm_intel_bo_gem_create_from_prime.
Tested by successfully running Chrome's ozone_demo [1] with the
ozone-gbm backend on an Intel Pineview M machine. Without this change
it fails while trying to create a DMA-BUF.
[1] https://chromium.googlesource.com/chromium/src.git/+/master/ui/ozone/demo/ozone_demo.cc
Signed-off-by: Nicholas Bishop <nbishop@neverware.com>
[Emil Velikov: Fix coding style]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Nicholas Bishop [Thu, 22 Sep 2016 15:04:13 +0000 (16:04 +0100)]
st/dri: check pipe_screen->resource_get_handle() return value
Change dri2_query_image to check the return value of resource_get_handle
and return GL_FALSE if an error occurs.
For reference this is an example callstack that should propagate the
error back to the user:
i915_drm_buffer_get_handle
i915_texture_get_handle
u_resource_get_handle_vtbl
dri2_query_image
gbm_dri_bo_get_fd
gbm_bo_get_fd
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Nicholas Bishop <nbishop@neverware.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
[Emil Velikov: Split from larger patch, polish coding style, cc stable]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Nicholas Bishop [Thu, 8 Sep 2016 19:55:02 +0000 (15:55 -0400)]
gbm: return appropriate error when queryImage() fails
Change gbm_dri_bo_get_fd to check the return value of queryImage and
return -1 (an invalid file descriptor) if an error occurs.
Update the comment for gbm_bo_get_fd to return -1, since (apart from the
above) we've already return -1 on error.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Nicholas Bishop <nbishop@neverware.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
[Emil Velikov: Split from larger patch, polish coding style, cc stable]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Andy Furniss [Mon, 26 Sep 2016 09:44:35 +0000 (10:44 +0100)]
st/va Avoid VBR bitrate calculation overflow v2
VBR bitrate calc needs 64 bits at high rates.
v2: use float.
Signed-off-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Mark Thompson [Mon, 26 Sep 2016 22:22:31 +0000 (23:22 +0100)]
st/va: Fix vaSyncSurface with no outstanding operation
Fixes crash if the application doesn't do what the state tracker expects.
Reviewed-by: Christian König <christian.koenig@amd.com>