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Simon Pilgrim [Wed, 29 Mar 2017 12:09:25 +0000 (12:09 +0000)]
[AMDGPU] Tidy up computeKnownBitsForTargetNode/ComputeNumSignBitsForTargetNode arguments. NFCI.
Based on comment in D31249.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298991
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Simon Pilgrim [Wed, 29 Mar 2017 10:47:18 +0000 (10:47 +0000)]
[X86][MMX] Added generic sitofp test to compare against existing cvtdq2ps test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298989
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Simon Pilgrim [Wed, 29 Mar 2017 10:44:51 +0000 (10:44 +0000)]
[X86] Removed old comment. NFCI.
No longer makes sense as the previous opcode mnemonic it was referring to is long gone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298988
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Sven van Haastregt [Wed, 29 Mar 2017 09:08:25 +0000 (09:08 +0000)]
[MachineVerifier] Avoid reference to nullptr
Instantiation of the MachineVerifierPass through
PassInfo::getNormalCtor would yield a segfault since the default
constructor of the MachineVerifierPass takes a reference to nullptr.
Patch by Simone Pellegrini.
Differential Revision: https://reviews.llvm.org/D31387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298987
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Eric Christopher [Wed, 29 Mar 2017 07:40:44 +0000 (07:40 +0000)]
Move the x86 cpu feature rtm from Haswell to Skylake matching clang commit r298956.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298986
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Craig Topper [Wed, 29 Mar 2017 07:31:56 +0000 (07:31 +0000)]
[AVX-512] Remove explicit KMOVWrk from isel patterns. COPY_TO_REGCLASS to GR32 is enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298985
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Craig Topper [Wed, 29 Mar 2017 06:55:28 +0000 (06:55 +0000)]
[AVX-512] Remove explicit KMOVWrk/KMOVWKr instructions from patterns where we can just use COPY_TO_REGCLASS instead.
This will result in a KMOVW or KMOVD being emitted during register allocation. And in at least some cases this might allow the register coalescer to remove the copy all together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298984
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Dean Michael Berris [Wed, 29 Mar 2017 06:10:12 +0000 (06:10 +0000)]
[XRay] Update FDR log reader to be aware of buffer sizes per thread.
Summary:
It is problematic for this reader that it expects to read data from
several threads, but the header or message format does not define
framing. Since the buffers are reused, we can't rely on skipping
zeroed out data as a synchronization method either.
There is an argument that this is not version compatible with the format
the reader expected previously. I argue that since the writer wrote garbage
past the end of buffer record, there is no currently working reader to
compromise.
The corresponding writer change is posted to D31384.
Reviewers: dberris, pelikan
Reviewed By: dberris
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298983
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Dean Michael Berris [Wed, 29 Mar 2017 04:55:45 +0000 (04:55 +0000)]
[XRay][tools] Handle "no subcommand" case for llvm-xray
Summary:
Currently the llvm-xray commandline tool fails to handle the case for
when no subcommand is provided in a graceful manner. This fixes that to
print the help message explaining the subcommands and the available
options.
Reviewers: pcc, pelikan
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298975
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Adam Nemet [Tue, 28 Mar 2017 23:46:14 +0000 (23:46 +0000)]
[SDAG] Remove -enable-fmf-dag
This is no longer needed as spotted by Sanjay in
https://reviews.llvm.org/D31165.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298963
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Adam Nemet [Tue, 28 Mar 2017 23:46:12 +0000 (23:46 +0000)]
[SDAG] Handle VectorReduction in SDNodeFlags::intersectWith
Spotted by Sanjay in https://reviews.llvm.org/D31165
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298962
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Adam Nemet [Tue, 28 Mar 2017 23:46:08 +0000 (23:46 +0000)]
[SDAG] Add AllowContract to SNodeFlags
Properly propagate the FMF from the LLVM IR to this flag.
This is toward moving fp-contraction=fast from an LLVM TargetOption to a
FastMathFlag in order to fix PR25721.
Differential Revision: https://reviews.llvm.org/D31165
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298961
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Peter Collingbourne [Tue, 28 Mar 2017 23:35:34 +0000 (23:35 +0000)]
More accurate header inclusions. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298960
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Craig Topper [Tue, 28 Mar 2017 23:29:35 +0000 (23:29 +0000)]
[AVX-512] Add test case that was supposed to go with r298957.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298959
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Craig Topper [Tue, 28 Mar 2017 23:20:37 +0000 (23:20 +0000)]
[AVX-512] Punt on fast-isel of truncates to i1 when AVX512 is enabled.
We should be masking the value and emitting a register copy like we do in non-fast isel. Instead we were just updating the value map and emitting nothing.
After r298928 we started seeing cases where we would create a copy from GR8 to GR32 because the source register in a VK1 to GR32 copy was replaced by the GR8 going into a truncate.
This fixes PR32451.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298957
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Guozhi Wei [Tue, 28 Mar 2017 22:55:01 +0000 (22:55 +0000)]
[PPC] In PPCBoolRetToInt change the bool value to i64 if the target is ppc64
In PPCBoolRetToInt bool value is changed to i32 type. On ppc64 it may introduce an extra zero extension for the return value. This patch changes the integer type to i64 to avoid the zero extension on ppc64.
This patch fixed PR32442.
Differential Revision: https://reviews.llvm.org/D31407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298955
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Sanjay Patel [Tue, 28 Mar 2017 22:45:53 +0000 (22:45 +0000)]
[DAGCombiner] reduce code duplication with local variables; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298954
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Eric Christopher [Tue, 28 Mar 2017 22:37:43 +0000 (22:37 +0000)]
Add a similar test for tailcall optimization as in r270287 for aarch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298952
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Peter Collingbourne [Tue, 28 Mar 2017 22:31:35 +0000 (22:31 +0000)]
LTO: Replace InputFile::Symbol::getFlags() with predicate accessors. NFC.
This makes the predicates independent of the flag representation
and makes the code a little easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298951
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Sanjay Patel [Tue, 28 Mar 2017 22:25:25 +0000 (22:25 +0000)]
[DAG] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298950
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Sanjay Patel [Tue, 28 Mar 2017 22:22:50 +0000 (22:22 +0000)]
[DAGCombiner] remove redundant conditions and duplicated code; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298949
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Stanislav Mekhanoshin [Tue, 28 Mar 2017 22:13:51 +0000 (22:13 +0000)]
[AMDGPU] Boost unroll threshold for loops reading local memory
This is less important than increase threshold for private memory,
but still brings performance improvements in a wide range of tests.
Unrolling more for local memory serves three purposes: it allows
to combine ds operations if offset becomes static, saves registers
used for offsets in case of static offsets, and allows better lds
latency hiding.
Differential Revision: https://reviews.llvm.org/D31412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298948
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Stanislav Mekhanoshin [Tue, 28 Mar 2017 21:48:54 +0000 (21:48 +0000)]
[AMDGPU] Fix recorded region boundaries in max-occupancy scheduler
This is incorrect to record region boundaries before scheduling,
it may change after scheduling. As a result second pass may see less
instructions to schedule than it should.
Differential Revision: https://reviews.llvm.org/D31434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298945
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Sanjay Patel [Tue, 28 Mar 2017 21:40:41 +0000 (21:40 +0000)]
[DAGCombiner] rename variables in foldAndOfSetCCs for easier reading; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298944
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Simon Pilgrim [Tue, 28 Mar 2017 21:32:11 +0000 (21:32 +0000)]
[X86][MMX] Match MMX fp_to_sint conversions from XMM registers
We currently perform the various fp_to_sint XMM conversion and then transfer to the MMX register (on 32-bit via the stack).
This patch improves support for MOVDQ2Q XMM to MMX transfers and adds the XMM->MMX fp_to_sint direct conversion patterns. The SSE2 specifications are the same as for XMM->XMM and XMM->MMX rounding/exceptions/etc.
Differential Revision: https://reviews.llvm.org/D30868
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298943
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Matt Arsenault [Tue, 28 Mar 2017 20:33:12 +0000 (20:33 +0000)]
Fix crashing on TargetCustom PseudoSourceValues
Default to something more reasonable if printCustom isn't implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298941
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Sanjay Patel [Tue, 28 Mar 2017 20:28:16 +0000 (20:28 +0000)]
[DAGCombiner] clean up foldAndOfSetCCs; NFCI
1. Fix bogus comment.
2. Early exit to reduce indent.
3. Change node pointer param to what it really is: an SDLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298940
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Adam Nemet [Tue, 28 Mar 2017 20:11:52 +0000 (20:11 +0000)]
[IR] Add AllowContract to FastMathFlags
-ffp-contract=fast does not currently work with LTO because it's passed as a
TargetOption to the backend rather than in the IR. This adds it to
FastMathFlags.
This is toward fixing PR25721
Differential Revision: https://reviews.llvm.org/D31164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298939
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Sanjay Patel [Tue, 28 Mar 2017 19:58:46 +0000 (19:58 +0000)]
[DAGCombiner] add helper function for and-of-setcc folds; NFC
This is just a cut and paste followed by clang-format. Clean up to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298938
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Mehdi Amini [Tue, 28 Mar 2017 18:55:44 +0000 (18:55 +0000)]
Add support for -fno-builtin to LTO and ThinLTO to libLTO
Reviewers: tejohnson, pcc
Subscribers: Prazek, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D30791
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298936
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Stanislav Mekhanoshin [Tue, 28 Mar 2017 18:23:24 +0000 (18:23 +0000)]
[AMDGPU] Split -amdgpu-early-inline-all option
Previously it was covered by the internalization. It turns out we cannot
run internalizer in FE, it break separate compilation tests. Thus early
inliner gets its own option.
Differential Revision: https://reviews.llvm.org/D31429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298935
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Sanjay Patel [Tue, 28 Mar 2017 17:23:49 +0000 (17:23 +0000)]
[x86] use VPMOVMSK to replace memcmp libcalls for 32-byte equality
Follow-up to:
https://reviews.llvm.org/rL298775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298933
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Weiming Zhao [Tue, 28 Mar 2017 17:15:11 +0000 (17:15 +0000)]
Revert "Dont emit Mapping symbols for sections that contain only data."
It breaks some lld tests.
This reverts commit
3a50eea6d9732ab40e9a7aebe6be777b53a8b35c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298932
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Nirav Dave [Tue, 28 Mar 2017 17:09:49 +0000 (17:09 +0000)]
[SDAG] Deal with deleted node in PromoteIntShiftOp
Deal with case that initial node is deleted during dag-combine leading
to an assertional failure in promoteIntShiftOp.
Fixes PR32420.
Reviewers: spatel, RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31403
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298931
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Zvi Rackover [Tue, 28 Mar 2017 16:45:23 +0000 (16:45 +0000)]
Add reproducer test for pr32449. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298930
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Simon Pilgrim [Tue, 28 Mar 2017 16:40:38 +0000 (16:40 +0000)]
[X86][AVX2] Add support for combining v16i16 shuffles to VPBLENDW
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298929
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Craig Topper [Tue, 28 Mar 2017 16:35:29 +0000 (16:35 +0000)]
[AVX-512] Fix accidental uses of AH/BH/CH/DH after copies to/from mask registers
We've had several bugs(PR32256, PR32241) recently that resulted from usages of AH/BH/CH/DH either before or after a copy to/from a mask register.
This ultimately occurs because we create COPY_TO_REGCLASS with VK1 and GR8. Then in CopyToFromAsymmetricReg in X86InstrInfo we find a 32-bit super register for the GR8 to emit the KMOV with. But as these tests are demonstrating, its possible for the GR8 register to be a high register and we end up doing an accidental extra or insert from bits 15:8.
I think the best way forward is to stop making copies directly between mask registers and GR8/GR16. Instead I think we should restrict to only copies between mask registers and GR32/GR64 and use EXTRACT_SUBREG/INSERT_SUBREG to handle the conversion from GR32 to GR16/8 or vice versa.
Unfortunately, this complicates fastisel a bit more now to create the subreg extracts where we used to create GR8 copies. We can probably make a helper function to bring down the repitition.
This does result in KMOVD being used for copies when BWI is available because we don't know the original mask register size. This caused a lot of deltas on tests because we have to split the checks for KMOVD vs KMOVW based on BWI.
Differential Revision: https://reviews.llvm.org/D30968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298928
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Sanjay Patel [Tue, 28 Mar 2017 15:55:50 +0000 (15:55 +0000)]
[x86] add separate check prefix for SSE; NFC
We want to check each test on each target, so we need another prefix
when SSE and AVX diverge (as they will if we handle 32-byte and higher).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298926
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Simon Pilgrim [Tue, 28 Mar 2017 15:50:23 +0000 (15:50 +0000)]
[X86][SSE] Refactored shuffle BLEND combining to make future 16i16 support easier. NFCI.
Call the matchVectorShuffleAsBlend test as early as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298925
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Nirav Dave [Tue, 28 Mar 2017 15:41:12 +0000 (15:41 +0000)]
[SDAG] Avoid deleted SDNodes PromoteIntBinOp
Reorder work in PromoteIntBinOp to prevent stale (deleted) nodes from
being used.
Fixes PR32340 and PR32345.
Reviewers: hfinkel, dbabokin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298923
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Nirav Dave [Tue, 28 Mar 2017 14:11:20 +0000 (14:11 +0000)]
[SDAG] Fix Stale SDNode usage in visitAND
Reorder CombineTo Calls to prevent potential use of deleted node.
Fixes PR32372.
Reviewers: jnspaulsson, RKSimon, uweigand, jonpa
Reviewed By: jonpa
Subscribers: jonpa, llvm-commits
Differential Revision: https://reviews.llvm.org/D31346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298920
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Sanjay Patel [Tue, 28 Mar 2017 13:46:50 +0000 (13:46 +0000)]
[x86] add AVX2 run to show 256-bit opportunity; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298918
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Simon Pilgrim [Tue, 28 Mar 2017 13:40:09 +0000 (13:40 +0000)]
Fix signed/unsigned comparison warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298917
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Nirav Dave [Tue, 28 Mar 2017 13:39:50 +0000 (13:39 +0000)]
[SDAG] Minor cleanup of variable usage. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298916
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Simon Pilgrim [Tue, 28 Mar 2017 13:05:48 +0000 (13:05 +0000)]
[X86][SSE] Begin merging vector shuffle to BLEND for lowering and combining.
Split off matchVectorShuffleAsBlend from lowerVectorShuffleAsBlend for reuse in combining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298914
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Simon Pilgrim [Tue, 28 Mar 2017 12:29:09 +0000 (12:29 +0000)]
Wdocumentation fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298911
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Simon Pilgrim [Tue, 28 Mar 2017 12:16:42 +0000 (12:16 +0000)]
[X86][SSE] Set second operand to undef instead of first operand in unary shuffle combines.
Copy isn't necessary after the matchVectorShuffleWithUNPCK refactor and undef value will make some future undef/zero handling easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298910
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Simon Pilgrim [Tue, 28 Mar 2017 11:15:17 +0000 (11:15 +0000)]
Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298909
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Sanne Wouda [Tue, 28 Mar 2017 10:02:56 +0000 (10:02 +0000)]
[AArch64] [Assembler] option to disable negative immediate conversions
Summary:
Similar to the ARM target in https://reviews.llvm.org/rL298380, this
patch adds identical infrastructure for disabling negative immediate
conversions, and converts the existing aliases to the new infrastucture.
Reviewers: rengolin, javed.absar, olista01, SjoerdMeijer, samparker
Reviewed By: samparker
Subscribers: samparker, aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D31243
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298908
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Igor Breger [Tue, 28 Mar 2017 09:35:06 +0000 (09:35 +0000)]
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298907
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Anna Thomas [Tue, 28 Mar 2017 09:32:24 +0000 (09:32 +0000)]
[InstCombine] For select rule, use positive check of constant int for select operand. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298906
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Anna Thomas [Tue, 28 Mar 2017 08:34:07 +0000 (08:34 +0000)]
rename instcombine test file. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298904
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Valery Pykhtin [Tue, 28 Mar 2017 07:19:48 +0000 (07:19 +0000)]
[AMDGPU] Update SI scheduler colorHighLatenciesGroups
Depends on rL298896: MachineScheduler/ScheduleDAG: Add support for GetSubGraph
Patch by Axel Davy (axel.davy@normalesup.org)
Differential revision: https://reviews.llvm.org/D30152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298902
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Weiming Zhao [Tue, 28 Mar 2017 05:40:36 +0000 (05:40 +0000)]
Dont emit Mapping symbols for sections that contain only data.
Summary:
Dont emit mapping symbols for sections that contain only data.
Patched by Shankar Easwaran <shankare@codeaurora.org>
Reviewers: rengolin, peter.smith, weimingz, kparzysz, t.p.northover
Reviewed By: t.p.northover
Subscribers: t.p.northover, llvm-commits
Differential Revision: https://reviews.llvm.org/D30724
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298901
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Craig Topper [Tue, 28 Mar 2017 05:32:55 +0000 (05:32 +0000)]
[APInt] Reformat tc functions to put opening curly braces on the end of the previous line. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298900
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Craig Topper [Tue, 28 Mar 2017 05:32:53 +0000 (05:32 +0000)]
[APInt] Remove an anonymous namespace around static functions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298899
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Craig Topper [Tue, 28 Mar 2017 05:32:52 +0000 (05:32 +0000)]
[APInt] Combine variable declaration and initialization where possible in the tc functions. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298898
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Craig Topper [Tue, 28 Mar 2017 05:32:48 +0000 (05:32 +0000)]
[APInt] Use 'unsigned' instead of 'unsigned int' in the interface to the APInt tc functions. This is more consistent with the rest of the codebase. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298897
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Valery Pykhtin [Tue, 28 Mar 2017 05:12:31 +0000 (05:12 +0000)]
MachineScheduler/ScheduleDAG: Add support for GetSubGraph
Patch by Axel Davy (axel.davy@normalesup.org)
Differential revision: https://reviews.llvm.org/D30626
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298896
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Junmo Park [Tue, 28 Mar 2017 04:14:25 +0000 (04:14 +0000)]
CodeGen : Check LLVM_ENABLE_DUMP definition for dumpMachineInstrRangeWithSlotIndex.
Summary:
Add missing check routine for dumpMachineInstrRangeWithSlotIndex including LLVM_DUMP_METHOD.
Reviewers: bkramer
Differential revision: https://reviews.llvm.org/D30367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298895
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Craig Topper [Tue, 28 Mar 2017 04:00:47 +0000 (04:00 +0000)]
[APInt] Move the single word cases of the bitwise operators inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298894
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Alex Shlyapnikov [Mon, 27 Mar 2017 23:11:50 +0000 (23:11 +0000)]
Revert "[asan] Delay creation of asan ctor."
Speculative revert. Some libfuzzer tests are affected.
This reverts commit r298731.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298890
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Alex Shlyapnikov [Mon, 27 Mar 2017 23:11:47 +0000 (23:11 +0000)]
Revert "[asan] Put ctor/dtor in comdat."
Speculative revert, some libfuzzer tests are affected.
This reverts commit r298756.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298889
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Eric Christopher [Mon, 27 Mar 2017 22:40:51 +0000 (22:40 +0000)]
Remove an oddly unnecessary temporary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298888
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Renato Golin [Mon, 27 Mar 2017 22:38:43 +0000 (22:38 +0000)]
[ARM] Mark falky test unsupported until we find the cause
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298887
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Juergen Ributzka [Mon, 27 Mar 2017 22:33:05 +0000 (22:33 +0000)]
[libfuzzer] Remove XFAIL for OutOfMemory test.
This test is now passing on Darwin.
See rdar://problem/
31282257.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298886
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Javed Absar [Mon, 27 Mar 2017 20:46:37 +0000 (20:46 +0000)]
Improve machine schedulers for in-order processors
This patch enables schedulers to specify instructions that
cannot be issued with any other instructions.
It also fixes BeginGroup/EndGroup.
Reviewed by: Andrew Trick
Differential Revision: https://reviews.llvm.org/D30744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298885
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Kevin Enderby [Mon, 27 Mar 2017 20:09:23 +0000 (20:09 +0000)]
Add the error handling for Mach-O dyld compact lazy bind, weak bind and
rebase entry errors and test cases for each of the error checks.
Also verified with Nick Kledzik that a BIND_OPCODE_SET_ADDEND_SLEB
opcode is legal in a lazy bind table, so code that had that as an error
check was removed.
With MachORebaseEntry and MachOBindEntry classes now returning
an llvm::Error in all cases for malformed input the variables Malformed
and logic to set use them is no longer needed and has been removed
from those classes.
Also in a few places, removed the redundant Done assignment to true
when also calling moveToEnd() as it does that assignment.
This only leaves the dyld compact export entries left to have
error handling yet to be added for the dyld compact info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298883
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Matthew Simpson [Mon, 27 Mar 2017 20:07:38 +0000 (20:07 +0000)]
[LV] Transform truncations of non-primary induction variables
The vectorizer tries to replace truncations of induction variables with new
induction variables having the smaller type. After r295063, this optimization
was applied to all integer induction variables, including non-primary ones.
When optimizing the truncation of a non-primary induction variable, we still
need to transform the new induction so that it has the correct start value.
This should fix PR32419.
Reference: https://bugs.llvm.org/show_bug.cgi?id=32419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298882
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Craig Topper [Mon, 27 Mar 2017 20:07:31 +0000 (20:07 +0000)]
[APInt] Move operator=(uint64_t) inline as its pretty simple and is often used with small constants that the compiler can optimize.
While there recognize that we only need to clearUnusedBits on the single word case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298881
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Krzysztof Parzyszek [Mon, 27 Mar 2017 19:08:24 +0000 (19:08 +0000)]
[TableGen] Print #nnn as a name of an non-native reg unit with id nnn
When using -debug with -gen-register-info, tablegen will crash when
trying to print a name of a non-native register unit. This patch only
affects the debug information generated while running llvm-tblgen,
and has no impact on the compilable code coming out of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298875
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Valery Pykhtin [Mon, 27 Mar 2017 18:22:39 +0000 (18:22 +0000)]
[AMDGPU] SISched: Detect dependency types between blocks
Patch by Axel Davy (axel.davy@normalesup.org)
Differential revision: https://reviews.llvm.org/D30153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298872
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Bruno Cardoso Lopes [Mon, 27 Mar 2017 18:21:31 +0000 (18:21 +0000)]
[Support] Avoid concurrency hazard in signal handler registration
Several static functions from the signal API can be invoked
simultaneously; RemoveFileOnSignal for instance can be called indirectly
by multiple parallel loadModule() invocations, which might lead to
the assertion:
Assertion failed: (NumRegisteredSignals < array_lengthof(RegisteredSignalInfo) && "Out of space for signal handlers!"),
function RegisterHandler, file /llvm/lib/Support/Unix/Signals.inc, line 105.
RemoveFileOnSignal calls RegisterHandlers(), which isn't currently
mutex protected, leading to the behavior above. This potentially affect
a few other users of RegisterHandlers() too.
rdar://problem/
30381224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298871
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Craig Topper [Mon, 27 Mar 2017 18:16:17 +0000 (18:16 +0000)]
[APInt] Move operator&=(uint64_t) inline and use memset to clear the upper words.
This method is pretty new and probably isn't use much in the code base so this should have a negligible size impact. The OR and XOR operators are already inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298870
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Ahmed Bougacha [Mon, 27 Mar 2017 18:14:20 +0000 (18:14 +0000)]
[GlobalISel][AArch64] Extract a variable out of an NDEBUG block. NFC.
r298863 used PtrReg, but that's never defined in release builds. Fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298869
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Craig Topper [Mon, 27 Mar 2017 17:50:54 +0000 (17:50 +0000)]
[APInt] Use memset in setAllBits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298867
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Adrian Prantl [Mon, 27 Mar 2017 17:36:31 +0000 (17:36 +0000)]
Remove redundant check for nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298866
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Adrian Prantl [Mon, 27 Mar 2017 17:34:04 +0000 (17:34 +0000)]
Remove unneccessary virtual destructor from DwarfExpression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298865
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Ahmed Bougacha [Mon, 27 Mar 2017 17:31:56 +0000 (17:31 +0000)]
[GlobalISel][AArch64] Fold FI into LDR/STR ui addressing mode.
A majority of loads and stores at O0 access an alloca.
It's trivial to fold the G_FRAME_INDEX into the instruction; do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298864
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Ahmed Bougacha [Mon, 27 Mar 2017 17:31:52 +0000 (17:31 +0000)]
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode.
We're not to the point of supporting the load/store patterns yet
(because they extensively use PatFrags).
But in the meantime, we can implement some of the simplest addressing
modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298863
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Ahmed Bougacha [Mon, 27 Mar 2017 17:31:48 +0000 (17:31 +0000)]
[GlobalISel][AArch64] Select store of zero to WZR/XZR.
These occur very frequently, and are quite trivial to catch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298862
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Valery Pykhtin [Mon, 27 Mar 2017 17:26:40 +0000 (17:26 +0000)]
[AMDGPU] SISched: Update colorEndsAccordingToDependencies
Patch by Axel Davy (axel.davy@normalesup.org)
Differential revision: https://reviews.llvm.org/D30150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298861
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Craig Topper [Mon, 27 Mar 2017 17:10:21 +0000 (17:10 +0000)]
[APInt] Move the >64 bit case for flipAllBits out of line.
This is more consistent with what we do for other operations. This shrinks the opt binary on my build by ~72k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298858
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Valery Pykhtin [Mon, 27 Mar 2017 17:06:36 +0000 (17:06 +0000)]
[AMDGPU] Fix SI scheduler LiveOut Refcount issue
Patch by Axel Davy (axel.davy@normalesup.org)
Differential revision: https://reviews.llvm.org/D30145
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298857
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Ahmed Bougacha [Mon, 27 Mar 2017 16:35:31 +0000 (16:35 +0000)]
[GlobalISel][AArch64] Select CBZ.
CBZ/CBNZ represent a substantial portion of all conditional branches.
Look through G_ICMP to select them.
We can't use tablegen yet because the existing patterns match an
AArch64ISD node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298856
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Ahmed Bougacha [Mon, 27 Mar 2017 16:35:27 +0000 (16:35 +0000)]
[GlobalISel] Add a 'getConstantVRegVal' helper.
Use it to compare immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298855
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Ahmed Bougacha [Mon, 27 Mar 2017 16:35:23 +0000 (16:35 +0000)]
[GlobalISel][AArch64] Use proper constant types in test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298854
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Dmitry Preobrazhensky [Mon, 27 Mar 2017 15:57:17 +0000 (15:57 +0000)]
[AMDGPU][MC] Fix for Bug 28207 + LIT tests
Enabled clamp and omod for v_cvt_* opcodes which have src0 of an integer type
Reviewers: vpykhtin, arsenm
Differential Revision: https://reviews.llvm.org/D31327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298852
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Chad Rosier [Mon, 27 Mar 2017 15:52:38 +0000 (15:52 +0000)]
[AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as not having side effects.
Among other things, this allows Machine LICM to hoist a costly 'mrs'
instruction from within a loop.
Differential Revision: http://reviews.llvm.org/D31151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298851
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Yaxun Liu [Mon, 27 Mar 2017 14:04:01 +0000 (14:04 +0000)]
[AMDGPU] Get address space mapping by target triple environment
As we introduced target triple environment amdgiz and amdgizcl, the address
space values are no longer enums. We have to decide the value by target triple.
The basic idea is to use struct AMDGPUAS to represent address space values.
For address space values which are not depend on target triple, use static
const members, so that they don't occupy extra memory space and is equivalent
to a compile time constant.
Since the struct is lightweight and cheap, it can be created on the fly at
the point of usage. Or it can be added as member to a pass and created at
the beginning of the run* function.
Differential Revision: https://reviews.llvm.org/D31284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298846
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Anna Thomas [Mon, 27 Mar 2017 13:52:51 +0000 (13:52 +0000)]
[InstCombine] Avoid incorrect folding of select into phi nodes when incoming element is a vector type
Summary:
We are incorrectly folding selects into phi nodes when the incoming value of a phi
node is a constant vector. This optimization is done in `FoldOpIntoPhi` when the
select condition is a phi node with constant incoming values.
Without the fix, we are miscompiling (i.e. incorrectly folding the
select into the phi node) when the vector contains non-zero
elements.
This patch fixes the miscompile and we will correctly fold based on the
select vector operand (see added test cases).
Reviewers: majnemer, sanjoy, spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31189
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298845
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Daniel Sanders [Mon, 27 Mar 2017 13:43:24 +0000 (13:43 +0000)]
Correct OptionCategoryCompare() in the command line library.
Summary:
It should return <0, 0, or >0 for less-than, equal, and greater-than like
strcmp() (according to the history, it used to be implemented with
strcmp()) but it actually returned 0, or 1 for not-equal and equal.
Reviewers: qcolombet
Reviewed By: qcolombet
Subscribers: qcolombet, llvm-commits
Differential Revision: https://reviews.llvm.org/D30996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298844
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Daniel Sanders [Mon, 27 Mar 2017 13:15:13 +0000 (13:15 +0000)]
[tablegen] Use categories on options that only matter to one emitter.
Summary:
The categories are emitted in a strange order in this patch due to a bug in the
CommandLine library.
Reviewers: ab
Reviewed By: ab
Subscribers: ab, llvm-commits
Differential Revision: https://reviews.llvm.org/D30995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298843
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Justin Bogner [Mon, 27 Mar 2017 12:56:12 +0000 (12:56 +0000)]
ADT: Add range helpers for pointer_ and pointee_iterator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298841
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Gadi Haber [Mon, 27 Mar 2017 12:13:37 +0000 (12:13 +0000)]
[X86][AVX2] bugzilla bug 21281 Performance regression in vector interleave in AVX2
This is a patch for an on-going bugzilla bug 21281 on the generated X86 code for a matrix transpose8x8 subroutine which requires vector interleaving. The generated code in AVX2 is currently non-optimal and requires 60 instructions as opposed to only 40 instructions generated for AVX1.
The patch includes a fix for the AVX2 case where vector unpack instructions use less operations than the vector blend operations available in AVX2.
In this case using vector unpack instructions is more efficient.
Reviewers:
zvi
delena
igorb
craig.topper
guyblank
eladcohen
m_zuckerman
aymanmus
RKSimon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298840
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Karl-Johan Karlsson [Mon, 27 Mar 2017 07:13:44 +0000 (07:13 +0000)]
[TableGen] Make CodeGenMapTable understand the namespace field of an instruction
Do not force the backends to use target name as namespace.
Original patch by Mattias Eriksson
Reviewers: stoklund, craig.topper
Reviewed By: stoklund
Subscribers: materi, llvm-commits
Differential Revision: https://reviews.llvm.org/D31322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298834
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Craig Topper [Mon, 27 Mar 2017 05:47:03 +0000 (05:47 +0000)]
[IR] Implement pairs of non-const and const methods using the const version instead of the non-const version. NFCI
This removes a const_cast of the this pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298831
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Craig Topper [Mon, 27 Mar 2017 05:46:58 +0000 (05:46 +0000)]
[IR] Share implementation for pairs of const and non-const methods using const_cast. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298830
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Craig Topper [Mon, 27 Mar 2017 02:38:17 +0000 (02:38 +0000)]
[IR] Share implementation of pairs of const and non-const methods in BasicBlock using the const version instead of the non-const version
Summary:
During post-commit review of a previous change I made it was pointed out that const casting 'this' is technically a bad practice. This patch re-implements all of the methods in BasicBlock that do this to use the const BasicBlock version and const_cast the return value instead.
I think there are still many other classes that do similar things. I may look at more in the future.
Reviewers: dblaikie
Reviewed By: dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298827
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Craig Topper [Sun, 26 Mar 2017 23:23:29 +0000 (23:23 +0000)]
[IR] Make Instruction::isAssociative method inline. Add LLVM_READONLY to the static version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298826
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