OSDN Git Service
Carlo Kok [Thu, 1 Aug 2013 20:17:37 +0000 (20:17 +0000)]
change the inlinefnlocalvar testcase so it uses a triple that's not coff (doesn't seem to matter for the testcase itself, what it tests isn't triple specific), as coff has a slightly different way of emitting what it checks for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187604
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Bob Wilson [Thu, 1 Aug 2013 19:29:26 +0000 (19:29 +0000)]
Temporarily xfail a test that breaks on OS X when building with LTO.
This is another case where internalize hides a symbol that is needed by
a loadable module. I am currently investigating a proper fix but this patch
will get our buildbot to pass in the meantime. <rdar://problem/
14578094>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187601
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Sean Silva [Thu, 1 Aug 2013 18:42:28 +0000 (18:42 +0000)]
Update incorrect file headers.
One of these was spotted in review by Rafael.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187598
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Carlo Kok [Thu, 1 Aug 2013 18:38:14 +0000 (18:38 +0000)]
Bugfix for making the DWARF debug strings and labels to code emitted as secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB.
fixes Bug 16249 - LLVM generates broken debug info on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187597
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Nadav Rotem [Thu, 1 Aug 2013 18:28:15 +0000 (18:28 +0000)]
Only enable SLP-vectorization on O3 builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187595
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Simon Atanasyan [Thu, 1 Aug 2013 18:04:07 +0000 (18:04 +0000)]
Pass -G argument to cmake with the same generator's name as used for the
initial cmake invocation.
Patch reviewed by Reid Kleckner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187591
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Robert Lytton [Thu, 1 Aug 2013 17:17:59 +0000 (17:17 +0000)]
remove executable permission from IntrinsicsXCore.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187584
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Tom Stellard [Thu, 1 Aug 2013 15:23:42 +0000 (15:23 +0000)]
R600: Add 64-bit float load/store support
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582
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Tom Stellard [Thu, 1 Aug 2013 15:23:31 +0000 (15:23 +0000)]
R600: Use 64-bit alignment for 64-bit kernel arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187581
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Tom Stellard [Thu, 1 Aug 2013 15:23:26 +0000 (15:23 +0000)]
R600/SI: Custom lower i64 ZERO_EXTEND
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187580
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Elena Demikhovsky [Thu, 1 Aug 2013 13:34:06 +0000 (13:34 +0000)]
EVEX and compressed displacement encoding for AVX512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187576
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Richard Sandiford [Thu, 1 Aug 2013 10:39:40 +0000 (10:39 +0000)]
[SystemZ] Reuse CC results for integer comparisons with zero
This also fixes a bug in the predication of LR to LOCR: I'd forgotten
that with these in-place instruction builds, the implicit operands need
to be added manually. I think this was latent until now, but is tested
by int-cmp-45.c. It also adds a CC valid mask to STOC, again tested by
int-cmp-45.c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187573
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Richard Sandiford [Thu, 1 Aug 2013 10:29:45 +0000 (10:29 +0000)]
[SystemZ] Prefer comparisons with zero
Convert >= 1 to > 0, etc. Using comparison with zero isn't a win on its own,
but it exposes more opportunities for CC reuse (the next patch).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187571
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Vladimir Medic [Thu, 1 Aug 2013 09:35:25 +0000 (09:35 +0000)]
Add tests for Mips DSP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187570
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Vladimir Medic [Thu, 1 Aug 2013 09:25:27 +0000 (09:25 +0000)]
Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187569
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Tim Northover [Thu, 1 Aug 2013 09:20:35 +0000 (09:20 +0000)]
AArch64: add initial NEON support
Patch by Ana Pazos.
- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise
- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic
- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same
- Intial implementation of instruction class:
Scalar Arithmetic
- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.
- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567
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Robert Lytton [Thu, 1 Aug 2013 08:41:32 +0000 (08:41 +0000)]
XCore target: add GCCBuiltin to four intrinsics
The following are made available by clang in the XCore ABI
__builtin_bitrev
__builtin_getid
__builtin_getps
__builtin_setps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187566
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Robert Lytton [Thu, 1 Aug 2013 08:29:44 +0000 (08:29 +0000)]
XCore target: Fix Vararg handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187565
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Robert Lytton [Thu, 1 Aug 2013 08:18:55 +0000 (08:18 +0000)]
XCore target: Add byval handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187563
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Robert Lytton [Thu, 1 Aug 2013 07:52:05 +0000 (07:52 +0000)]
Xcore target
Fix emitArrayBound() calling OutStreamer.Emit*() multiple times when trying to print a single line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187562
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Reed Kotler [Thu, 1 Aug 2013 02:26:31 +0000 (02:26 +0000)]
Fix some misc. issues with Mips16 fp stubs.
1) They should never be inlined.
2) A naming inconsistency with gcc mips16
3) Stubs should not have the global attribute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187555
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Eric Christopher [Thu, 1 Aug 2013 01:38:16 +0000 (01:38 +0000)]
Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187554
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Reed Kotler [Thu, 1 Aug 2013 00:59:06 +0000 (00:59 +0000)]
Add an omitted IsCall=1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187553
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Hans Wennborg [Wed, 31 Jul 2013 23:28:51 +0000 (23:28 +0000)]
Option parsing: remove non-SUPPORT_ALIASARGS fall-back
The clients of this code have been updated to all support AliasArgs.
This depends on Clang r187538 and lld r187541.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187546
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Hans Wennborg [Wed, 31 Jul 2013 22:44:41 +0000 (22:44 +0000)]
Option parsing: add support for alias arguments.
This makes option aliases more powerful by enabling them to
pass along arguments to the option they're aliasing.
For example, if we have a joined option "-foo=", we can now
specify a flag option "-bar" to be an alias of that, with the
argument "baz".
This is especially useful for the cl.exe compatible clang driver,
where many options are aliases. For example, this patch enables
us to alias "/Ox" to "-O3" (-O is a joined option), and "/WX" to
"-Werror" (again, -W is a joined option).
Differential Revision: http://llvm-reviews.chandlerc.com/D1245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187537
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Nadav Rotem [Wed, 31 Jul 2013 22:17:45 +0000 (22:17 +0000)]
80-col
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187535
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Andrew Trick [Wed, 31 Jul 2013 21:05:54 +0000 (21:05 +0000)]
comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187531
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Kevin Enderby [Wed, 31 Jul 2013 21:05:30 +0000 (21:05 +0000)]
Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match. Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.
rdar://
14214063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530
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Tom Stellard [Wed, 31 Jul 2013 20:43:27 +0000 (20:43 +0000)]
Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit
98ce62780ea7185ba710868bf83c8077e8d7f6d6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526
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Tom Stellard [Wed, 31 Jul 2013 20:43:08 +0000 (20:43 +0000)]
Revert "TableGen: Enumerate Schedule Model too."
This reverts commit
2ca1e4a39c7e0d7a00e66ff5437c6d7ace2404a0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187525
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Tom Stellard [Wed, 31 Jul 2013 20:43:03 +0000 (20:43 +0000)]
Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
This reverts commit
3f1de26cb5cc0543a6a1d71259a7a39d97139051.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187524
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Vincent Lejeune [Wed, 31 Jul 2013 19:32:12 +0000 (19:32 +0000)]
R600: Do not mergevector after a vector reg is used
If we merge vector when a vector is used, it will generate an artificial
antidependency that can prevent 2 tex/vtx instructions to use the same
clause and thus generate extra clauses that reduce performance.
There is no test case as such situation is really hard to predict.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187516
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Vincent Lejeune [Wed, 31 Jul 2013 19:32:07 +0000 (19:32 +0000)]
R600: Avoid more than 4 literals in the same instruction group at scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187515
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Vincent Lejeune [Wed, 31 Jul 2013 19:31:56 +0000 (19:31 +0000)]
R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514
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Vincent Lejeune [Wed, 31 Jul 2013 19:31:41 +0000 (19:31 +0000)]
R600: Don't mix LDS and non-LDS instructions in the same group
There are a lot of restrictions on instruction groups that contain
LDS instructions, so for now we will be conservative and not packetize
anything else with them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187513
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Vincent Lejeune [Wed, 31 Jul 2013 19:31:35 +0000 (19:31 +0000)]
R600: Use SchedModel enum for is{Trans,Vector}Only functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187512
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Vincent Lejeune [Wed, 31 Jul 2013 19:31:20 +0000 (19:31 +0000)]
TableGen: Enumerate Schedule Model too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187511
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Vincent Lejeune [Wed, 31 Jul 2013 19:31:14 +0000 (19:31 +0000)]
R600: Remove predicated_break inst
We were using two instructions for similar purpose : break and
predicated break. Only predicated_break was emitted and it was
lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP.
This commit simplify the situation by making AMDILCFGStructurizer
emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which
is now removed).
There is no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187510
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Matt Arsenault [Wed, 31 Jul 2013 17:49:08 +0000 (17:49 +0000)]
Reject bitcasts between address spaces with different sizes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187506
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Richard Sandiford [Wed, 31 Jul 2013 12:58:26 +0000 (12:58 +0000)]
[SystemZ] Implement isLegalAddressingMode()
The loop optimizers were assuming that scales > 1 were OK. I think this
is actually a bug in TargetLoweringBase::isLegalAddressingMode(),
since it seems to be trying to reject anything that isn't r+i or r+r,
but it has no default case for scales other than 0, 1 or 2. Implementing
the hook for z means that z can no longer test any change there though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187497
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Richard Sandiford [Wed, 31 Jul 2013 12:38:08 +0000 (12:38 +0000)]
[SystemZ] Be more careful about inverting CC masks (conditional loads)
Extend r187495 to conditional loads. I split this out because the
easiest way seemed to be to force a particular operand order in
SystemZISelDAGToDAG.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187496
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Richard Sandiford [Wed, 31 Jul 2013 12:30:20 +0000 (12:30 +0000)]
[SystemZ] Be more careful about inverting CC masks
System z branches have a mask to select which of the 4 CC values should
cause the branch to be taken. We can invert a branch by inverting the mask.
However, not all instructions can produce all 4 CC values, so inverting
the branch like this can lead to some oddities. For example, integer
comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater).
If an integer EQ is reversed to NE before instruction selection,
the branch will test for 1 or 2. If instead the branch is reversed
after instruction selection (by inverting the mask), it will test for
1, 2 or 3. Both are correct, but the second isn't really canonical.
This patch therefore keeps track of which CC values are possible
and uses this when inverting a mask.
Although this is mostly cosmestic, it fixes undefined behavior
for the CIJNLH in branch-08.ll. Another fix would have been
to mask out bit 0 when generating the fused compare and branch,
but the point of this patch is that we shouldn't need to do that
in the first place.
The patch also makes it easier to reuse CC results from other instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495
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Richard Sandiford [Wed, 31 Jul 2013 12:11:07 +0000 (12:11 +0000)]
[SystemZ] Move compare-and-branch generation even later
r187116 moved compare-and-branch generation from the instruction-selection
pass to the peephole optimizer (via optimizeCompare). It turns out that even
this is a bit too early. Fused compare-and-branch instructions don't
interact well with predication, where a CC result is needed. They also
make it harder to reuse the CC side-effects of earlier instructions
(not yet implemented, but the subject of a later patch).
Another problem was that the AnalyzeBranch family of routines weren't
handling compares and branches, so we weren't able to reverse the fused
form in cases where we would reverse a separate branch. This could have
been fixed by extending AnalyzeBranch, but given the other problems,
I've instead moved the fusing to the long-branch pass, which is also
responsible for the opposite transformation: splitting out-of-range
compares and branches into separate compares and long branches.
I've added a test for the AnalyzeBranch problem. A test for the
predication problem is included in the next patch, which fixes a bug
in the choice of CC mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187494
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Elena Demikhovsky [Wed, 31 Jul 2013 12:03:08 +0000 (12:03 +0000)]
Fixed assertion in Extract128BitVector()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187493
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Richard Sandiford [Wed, 31 Jul 2013 11:36:35 +0000 (11:36 +0000)]
[SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()
r186399 aggressively used the RISBG instruction for immediate ANDs,
both because it can handle some values that AND IMMEDIATE can't,
and because it allows the destination register to be different from
the source. I realized later while implementing the distinct-ops
support that it would be better to leave the choice up to
convertToThreeAddress() instead. The AND IMMEDIATE form is shorter
and is less likely to be cracked.
This is a problem for 32-bit ANDs because we assume that all 32-bit
operations will leave the high word untouched, whereas RISBG used in
this way will either clear the high word or copy it from the source
register. The patch uses the z196 instruction RISBLG for this instead.
This means that z10 will be restricted to NILL, NILH and NILF for
32-bit ANDs, but I think that should be OK for now. Although we're
using z10 as the base architecture, the optimization work is going
to be focused more on z196 and zEC12.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492
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Elena Demikhovsky [Wed, 31 Jul 2013 11:35:14 +0000 (11:35 +0000)]
Added INSERT and EXTRACT intructions from AVX-512 ISA.
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491
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Richard Sandiford [Wed, 31 Jul 2013 11:17:35 +0000 (11:17 +0000)]
[SystemZ] Add RISBLG and RISBHG instruction definitions
The next patch will make use of RISBLG for codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187490
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Richard Trieu [Wed, 31 Jul 2013 04:07:28 +0000 (04:07 +0000)]
Add parentheses to silence gcc warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187482
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Andrew Trick [Wed, 31 Jul 2013 03:24:31 +0000 (03:24 +0000)]
Fix register pressure tables on ARM.
The heuristic that merges register pressure sets was bogus for ARM's S/D regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187479
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Andrew Trick [Wed, 31 Jul 2013 03:24:28 +0000 (03:24 +0000)]
Add tracing to the tblgen register pressure table generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187478
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Craig Topper [Wed, 31 Jul 2013 03:22:07 +0000 (03:22 +0000)]
Increment arg_count inside the loop in printInline. Patch by Joe Matarazzo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187477
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Craig Topper [Wed, 31 Jul 2013 02:47:52 +0000 (02:47 +0000)]
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
Patch by Richard Mitton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476
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Andrew Trick [Wed, 31 Jul 2013 02:43:40 +0000 (02:43 +0000)]
Fix a severe compile time problem when forming large SCEV expressions.
This fix is very lightweight. The same fix already existed for AddRec
but was missing for NAry expressions.
This is obviously an improvement and I'm unsure how to test compile
time problems.
Patch by Xiaoyi Guo!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187475
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Craig Topper [Wed, 31 Jul 2013 02:00:15 +0000 (02:00 +0000)]
Remove trailing whitespace and some tab characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187472
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Craig Topper [Wed, 31 Jul 2013 01:50:26 +0000 (01:50 +0000)]
Fixed incorrect disassembly for MOV16o16a when using Intel syntax.
Patch by Richard Mitton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187471
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Eric Christopher [Wed, 31 Jul 2013 01:26:24 +0000 (01:26 +0000)]
Fix crashing on invalid inline asm with matching constraints.
For a testcase like the following:
typedef unsigned long uint64_t;
typedef struct {
uint64_t lo;
uint64_t hi;
} blob128_t;
void add_128_to_128(const blob128_t *in, blob128_t *res) {
asm ("PAND %1, %0" : "+Q"(*res) : "Q"(*in));
}
where we'll fail to allocate the register for the output constraint,
our matching input constraint will not find a register to match,
and could try to search past the end of the current operands array.
On the idea that we'd like to attempt to keep compilation going
to find more errors in the module, change the error cases when
we're visiting inline asm IR to return immediately and avoid
trying to create a node in the DAG. This leaves us with only
a single error message per inline asm instruction, but allows us
to safely keep going in the general case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187470
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Akira Hatanaka [Wed, 31 Jul 2013 00:57:41 +0000 (00:57 +0000)]
[mips] Rename instruction DANDi to ANDi64.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187469
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Akira Hatanaka [Wed, 31 Jul 2013 00:55:34 +0000 (00:55 +0000)]
[mips] Define instruction itineraries IIArith and IILogic.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468
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Matt Arsenault [Wed, 31 Jul 2013 00:17:33 +0000 (00:17 +0000)]
Fix ptr vector inconsistency in CreatePointerCast
One form would accept a vector of pointers, and the other did not.
Make both accept vectors of pointers, and add an assertion
for the number of elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187464
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Rafael Espindola [Wed, 31 Jul 2013 00:10:25 +0000 (00:10 +0000)]
Fix windows' implementation of status when a file doesn't exist.
The unix one was returning no_such_file_or_directory, but the windows one
was return success.
Update the one one caller that was depending on the old behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187463
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Owen Anderson [Tue, 30 Jul 2013 23:53:17 +0000 (23:53 +0000)]
Preserve fast-math flags when folding (fsub x, (fneg y)) to (fadd x, y).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187462
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Eric Christopher [Tue, 30 Jul 2013 22:50:44 +0000 (22:50 +0000)]
Reflow this to be easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187459
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Eric Christopher [Tue, 30 Jul 2013 22:35:06 +0000 (22:35 +0000)]
Make these just inline, not static inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187457
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Eric Christopher [Tue, 30 Jul 2013 22:34:30 +0000 (22:34 +0000)]
Make sure that -gsplit-dwarf isn't passed to the linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187456
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Matt Arsenault [Tue, 30 Jul 2013 22:27:10 +0000 (22:27 +0000)]
Respect address space sizes in isEliminableCastPair.
This avoids constant folding bitcast/ptrtoint/inttoptr combinations
that have illegal bitcasts between differently sized address spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187455
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Matt Arsenault [Tue, 30 Jul 2013 22:02:14 +0000 (22:02 +0000)]
Revert "Remove isCastable since nothing uses it now"
Apparently dragonegg uses it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187454
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Eric Christopher [Tue, 30 Jul 2013 21:44:10 +0000 (21:44 +0000)]
Add capability for building with -gsplit-dwarf to the cmake build.
In limited testing this seems to work. Caveat emptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187452
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Matt Arsenault [Tue, 30 Jul 2013 21:11:17 +0000 (21:11 +0000)]
Remove isCastable since nothing uses it now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187448
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David Majnemer [Tue, 30 Jul 2013 21:01:36 +0000 (21:01 +0000)]
isKnownToBeAPowerOfTwo: Strengthen isKnownToBeAPowerOfTwo's analysis on add instructions
Call into ComputeMaskedBits to figure out which bits are set on both add
operands and determine if the value is a power-of-two-or-zero or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187445
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Matt Arsenault [Tue, 30 Jul 2013 20:45:05 +0000 (20:45 +0000)]
Change behavior of calling bitcasted alias functions.
It will now only convert the arguments / return value and call
the underlying function if the types are able to be bitcasted.
This avoids using fp<->int conversions that would occur before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187444
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Akira Hatanaka [Tue, 30 Jul 2013 20:42:19 +0000 (20:42 +0000)]
[mips] Delete instruction format for "bal".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187443
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Andrew Trick [Tue, 30 Jul 2013 20:34:59 +0000 (20:34 +0000)]
This test may have been sensitive to the ARM ABI...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187442
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Rafael Espindola [Tue, 30 Jul 2013 20:25:53 +0000 (20:25 +0000)]
Implement getUniqueID for directories on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187441
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Akira Hatanaka [Tue, 30 Jul 2013 20:24:24 +0000 (20:24 +0000)]
[mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that
turns "bal" into "bgezal".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187440
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Rafael Espindola [Tue, 30 Jul 2013 20:02:18 +0000 (20:02 +0000)]
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187439
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Andrew Trick [Tue, 30 Jul 2013 19:59:19 +0000 (19:59 +0000)]
Down-scale slot index distance to save bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187438
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Andrew Trick [Tue, 30 Jul 2013 19:59:15 +0000 (19:59 +0000)]
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187437
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Andrew Trick [Tue, 30 Jul 2013 19:59:12 +0000 (19:59 +0000)]
MI Sched: Track live-thru registers.
When registers must be live throughout the scheduling region, increase
the limit for the register class. Once we exceed the original limit,
they will be spilled, and there's no point further reducing pressure.
This isn't a perfect heuristics but avoids a situation where the
scheduler could become trapped by trying to achieve the impossible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187436
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Andrew Trick [Tue, 30 Jul 2013 19:59:08 +0000 (19:59 +0000)]
MI Sched fix: assert "Disconnected LRG within the scheduling region."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187435
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Venkatraman Govindaraju [Tue, 30 Jul 2013 19:53:10 +0000 (19:53 +0000)]
[Sparc] Rewrite MBB's live-in registers for leaf functions. Also, add
register i7 as a live-in if current function's return address is taken.
This revision fixes PR16269.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187433
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Rui Ueyama [Tue, 30 Jul 2013 19:03:20 +0000 (19:03 +0000)]
Implement TokenizeWindowsCommandLine.
This is a follow up patch for r187390 to implement the parser for the
Windows-style command line. This should follow the rule as described
at http://msdn.microsoft.com/en-us/library/windows/desktop/17w5ykft(v=vs.85).aspx
Differential Revision: http://llvm-reviews.chandlerc.com/D1235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187430
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Daniel Malea [Tue, 30 Jul 2013 16:16:11 +0000 (16:16 +0000)]
Fix parameter ordering bug in createDebugIRPass()
- Thanks to Ilia Filippov for pointing out the inconsistency!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187424
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Tom Stellard [Tue, 30 Jul 2013 14:31:03 +0000 (14:31 +0000)]
R600/SI: Expand vector fp <-> int conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187421
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Vladimir Medic [Tue, 30 Jul 2013 10:12:14 +0000 (10:12 +0000)]
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410
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Bill Wendling [Tue, 30 Jul 2013 08:26:24 +0000 (08:26 +0000)]
Fix underscore to be the proper length.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187406
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Saleem Abdulrasool [Tue, 30 Jul 2013 04:43:08 +0000 (04:43 +0000)]
[ARM] check bitwidth in PerformORCombine
When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the
bitwidth of the second operands to both ands match before comparing the negation
of the values.
Split the check of the value of the second operands to the ands. Move the cast
and variable declaration slightly higher to make it slightly easier to follow.
Bug-Id: 16700
Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187404
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Rafael Espindola [Tue, 30 Jul 2013 04:06:06 +0000 (04:06 +0000)]
Remove more dead documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187403
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Venkatraman Govindaraju [Tue, 30 Jul 2013 02:26:29 +0000 (02:26 +0000)]
[Sparc] Use call's debugloc for the unimp instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187402
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Bill Schmidt [Tue, 30 Jul 2013 00:50:39 +0000 (00:50 +0000)]
[PowerPC] Skeletal FastISel support for 64-bit PowerPC ELF.
This is the first of many upcoming patches for PowerPC fast
instruction selection support. This patch implements the minimum
necessary for a functional (but extremely limited) FastISel pass. It
allows the table-generated portions of the selector to be created and
used, but in most cases selection will fall back to the DAG selector.
None of the block terminator instructions are implemented yet, and
most interesting instructions require some special handling.
Therefore there aren't any new test cases with this patch. There will
be quite a few tests coming with future patches.
This patch adds the make/CMake support for the new code (including
tablegen -gen-fast-isel) and creates the FastISel object for PPC64 ELF
only. It instantiates the necessary virtual functions
(TargetSelectInstruction, TargetMaterializeConstant,
TargetMaterializeAlloca, tryToFoldLoadIntoMI, and FastLowerArguments),
but of these, only TargetMaterializeConstant contains any useful
implementation. This is present since the table-generated code
requires the ability to materialize integer constants for some
instructions.
This patch has been tested by building and running the
projects/test-suite code with -O0. All tests passed with the
exception of a couple of long-running tests that time out using -O0
code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187399
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Quentin Colombet [Tue, 30 Jul 2013 00:27:16 +0000 (00:27 +0000)]
[R600] Replicate old DAGCombiner behavior in target specific DAG combine.
build_vector is lowered to REG_SEQUENCE, which is something the register
allocator does a good job at optimizing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187397
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Quentin Colombet [Tue, 30 Jul 2013 00:24:09 +0000 (00:24 +0000)]
[DAGCombiner] insert_vector_elt: Avoid building a vector twice.
This patch prevents the following combine when the input vector is used more
than once.
insert_vector_elt (build_vector elt0, ..., eltN), NewEltIdx, idx
=>
build_vector elt0, ..., NewEltIdx, ..., eltN
The reasons are:
- Building a vector may be expensive, so try to reuse the existing part of a
vector instead of creating a new one (think big vectors).
- elt0 to eltN now have two users instead of one. This may prevent some other
optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187396
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Eric Christopher [Tue, 30 Jul 2013 00:20:06 +0000 (00:20 +0000)]
Move file to X86 and add a triple to fix darwin bots for now.
The problem is due to the section name being explicitly mentioned in
the IR and differing between the two platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187394
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Eric Christopher [Mon, 29 Jul 2013 23:53:08 +0000 (23:53 +0000)]
Fix a truly egregious thinko in anonymous namespace check,
update testcase to make sure we generate debug info for walrus
by adding a non-trivial constructor and verify that we don't
emit an ODR signature for the type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187393
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Eric Christopher [Mon, 29 Jul 2013 23:53:05 +0000 (23:53 +0000)]
Make sure we don't emit an ODR hash for types with no name and make
sure the comments for each testcase are a bit easier to distinguish.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187392
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Eric Christopher [Mon, 29 Jul 2013 23:53:01 +0000 (23:53 +0000)]
Clarify comments for types contained in anonymous namespaces and
odr hashes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187391
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Eric Christopher [Mon, 29 Jul 2013 22:24:32 +0000 (22:24 +0000)]
Elaborate a bit on the type unit and ODR conditional code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187385
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Rafael Espindola [Mon, 29 Jul 2013 21:55:38 +0000 (21:55 +0000)]
Make file_status::getUniqueID const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187383
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Rafael Espindola [Mon, 29 Jul 2013 21:35:48 +0000 (21:35 +0000)]
Delete documentation for deleted options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187380
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Rafael Espindola [Mon, 29 Jul 2013 21:26:49 +0000 (21:26 +0000)]
Include st_dev to make the result of getUniqueID actually unique.
This will let us use getUniqueID instead of st_dev directly on clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187378
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Manman Ren [Mon, 29 Jul 2013 20:18:19 +0000 (20:18 +0000)]
Debug Info: enable verifier for testing cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187375
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