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Brian Paul [Tue, 16 Aug 2011 22:30:52 +0000 (16:30 -0600)]
st/mesa: fix incorrect loop over instruction src regs
The array of src regs is of size 3, not 4.
Lauri Kasanen [Fri, 1 Jul 2011 09:57:06 +0000 (12:57 +0300)]
st/dri: Indent driconf options
Lauri Kasanen [Fri, 1 Jul 2011 10:01:00 +0000 (13:01 +0300)]
xmlpool.h: fix a typo
Lauri Kasanen [Fri, 1 Jul 2011 10:49:18 +0000 (13:49 +0300)]
xmlconfig: Make the error message more informative
Ian Romanick [Thu, 4 Aug 2011 00:12:29 +0000 (17:12 -0700)]
mesa: Bump instruction execution limit to 65536
Shader Model 3.0[1] requires that shaders be able to execute at least
65536 instructions. Bump Mesa maxExec to that limit. This allows
several vertex shaders in the OpenGL ES 2.0 conformance test suite to
run to completion.
1: http://en.wikipedia.org/wiki/High_Level_Shader_Language
Reviewed-by: Eric Anholt <eric@anholt.net>
Ian Romanick [Thu, 10 Feb 2011 23:48:27 +0000 (15:48 -0800)]
mesa: Add partial constant propagation pass for Mesa IR
This cleans up some code generated by the IR-to-Mesa pass for i915.
In particular, some shaders involving arrays of constant matrices
result in really bad code.
v2: Silence several warnings from merging the gl_constant_value work.
Fix DP[23] folding. Add support for a bunch more opcodes that appear
in piglit runs on i915.
Reviewed-by: Eric Anholt <eric@anholt.net>
Ian Romanick [Tue, 2 Aug 2011 19:17:20 +0000 (12:17 -0700)]
ir_to_mesa: Emit a MAD(b, -a, b) for !a && b
!a && b occurs frequently when nexted if-statements have been
flattened. It should also be possible use a MAD for (a && b) || c,
though that would require a MAD_SAT.
Reviewed-by: Eric Anholt <eric@anholt.net>
Ian Romanick [Wed, 3 Aug 2011 22:42:05 +0000 (15:42 -0700)]
ir_to_mesa: Implement ir_binop_all_equal using DP4 w/SGE
The operation ir_binop_all_equal is !(a.x != b.x || a.y != b.y || a.z
!= b.z || a.w != b.w). Logical-or is implemented using addition
(followed by clampling to [0,1]) on values of 0.0 and 1.0. Replacing
the logical-or operators with addition gives !bool((int(a.x != b.x) +
int(a.y == b.y) + int(a.z == b.z) + int(a.w == b.w)). This can be
implemented using a dot-product with a vector of all 1.0. After the
dot-product, the value will be an integer on the range [0,4].
Previously a SEQ instruction was used to clamp the resulting logic
value to [0,1] and invert the result. Using an SGE instruction on the
negation of the dot-product result has the same effect. Many older
shader architectures do not support the SEQ instruction. It must be
emulated using two SGE instructions and a MUL. On these
architectures, the single SGE saves two instructions.
Reviewed-by: Eric Anholt <eric@anholt.net>
Ian Romanick [Wed, 3 Aug 2011 22:35:01 +0000 (15:35 -0700)]
ir_to_mesa: Implement ir_binop_any_nequal using DP4 w/saturate or DP4 w/SLT
The operation ir_binop_any_nequal is (a.x != b.x) || (a.y != b.y) ||
(a.z != b.z) || (a.w != b.w), and that is the same as any(bvec4(a.x !=
b.x, a.y != b.y, a.z != b.z, a.w != b.w)). Implement the any() part
the same way the regular ir_unop_any is implemented.
Reviewed-by: Eric Anholt <eric@anholt.net>
Ian Romanick [Wed, 3 Aug 2011 22:27:43 +0000 (15:27 -0700)]
ir_to_mesa: Implement ir_unop_any using DP4 w/saturate or DP4 w/SLT
This is just like the ir_binop_logic_or case. The operation
ir_unop_any is (a.x || a.y || a.z || a.w). Logical-or is implemented
using addition (followed by clampling to [0,1]) on values of 0.0 and
1.0. Replacing the logical-or operators with addition gives (a.x +
a.y + a.z + a.w). This can be implemented using a dot-product with a
vector of all 1.0.
Previously a SNE instruction was used to clamp the resulting logic
value to [0,1]. In a fragment shader, using a saturate on the
dot-product has the same effect. Adding the saturate to the
dot-product is free, so (at least) one instruction is saved.
In a vertex shader, using an SLT on the negation of the dot-product
result has the same effect. Many older shader architectures do not
support the SNE instruction. It must be emulated using two SLT
instructions and an ADD. On these architectures, the single SLT saves
two instructions.
Reviewed-by: Eric Anholt <eric@anholt.net>
Ian Romanick [Sat, 30 Jul 2011 17:45:35 +0000 (10:45 -0700)]
ir_to_mesa: Make ir_to_mesa_visitor::emit_dp return the instruction
Reviewed-by: Eric Anholt <eric@anholt.net>
Ian Romanick [Sat, 30 Jul 2011 17:49:49 +0000 (10:49 -0700)]
ir_to_mesa: Implement ir_binop_logic_or using an add w/saturate or add w/SLT
Logical-or is implemented using addition (followed by clampling to
[0,1]) on values of 0.0 and 1.0. Replacing the logical-or operators
with addition gives a + b which has a result on the range [0, 2].
Previously a SNE instruction was used to clamp the resulting logic
value to [0,1]. In a fragment shader, using a saturate on the add has
the same effect. Adding the saturate to the add is free, so (at
least) one instruction is saved.
In a vertex shader, using an SLT on the negation of the add result has
the same effect. Many older shader architectures do not support the
SNE instruction. It must be emulated using two SLT instructions and
an ADD. On these architectures, the single SLT saves two
instructions.
Reviewed-by: Eric Anholt <eric@anholt.net>
Ian Romanick [Sat, 30 Jul 2011 17:48:10 +0000 (10:48 -0700)]
ir_to_mesa: Implement ir_unop_logic_not using 1-x
Since our logic values are 0.0 (false) and 1.0 (true), 1.0 - x
accurately implements logical not.
Reviewed-by: Eric Anholt <eric@anholt.net>
Chad Versace [Mon, 15 Aug 2011 20:29:15 +0000 (13:29 -0700)]
mesa: Add Android to list of platforms that define fpclassify()
This is a fix for the Android build.
Signed-off-by: Chad Versace <chad@chad-versace.us>
Chad Versace [Mon, 15 Aug 2011 20:26:21 +0000 (13:26 -0700)]
mesa: Fix Android build by #ifdef'ing out locale support
Bionic does not support locales. This commit #ifdef's out the locale usage
in _mesa_strtof().
Signed-off-by: Chad Versace <chad@chad-versace.us>
Chad Versace [Mon, 15 Aug 2011 17:58:25 +0000 (10:58 -0700)]
mesa: Remove use of fpu_control.h
Remove the inclusion of fpu_control.h from compiler.h. Since Bionic lacks
fpu_control.h, this fixes the Android build.
Also remove the sole use of the fpu_control bits, which was in debug.c.
Those were brianp's debug bits, and he approved of their removal.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
Eric Anholt [Tue, 16 Aug 2011 04:02:10 +0000 (21:02 -0700)]
i965/vs: Fix multiplies to actually do 32-bit multiplies.
Fixes vs-op-mult-int-int and friends.
Eric Anholt [Tue, 16 Aug 2011 03:59:24 +0000 (20:59 -0700)]
i965/vs: Add support for conversion of FIXED_HW_REG src_reg to/from dst_reg.
This was quietly occurring in some emit code I produced, and failed.
Eric Anholt [Tue, 16 Aug 2011 03:43:42 +0000 (20:43 -0700)]
i965/vs: Fix memory leak of ralloc context for the visitor.
Eric Anholt [Tue, 16 Aug 2011 03:13:53 +0000 (20:13 -0700)]
i965/vs: Fix condition code for scalar expression all_equals.
Fixes vs-op-eq-bool-bool.
Eric Anholt [Fri, 12 Aug 2011 12:32:25 +0000 (05:32 -0700)]
i965/vs: Don't assertion fail on vertex texturing.
The linker will reject the program, but we need to survive until then.
Fixes abort in glsl1-2D Texture lookup with explicit lod (Vertex
shader)
Eric Anholt [Fri, 12 Aug 2011 12:28:53 +0000 (05:28 -0700)]
i965/gen6: Force WHILE exec size to 8.
We can't just look at the instruction that happens to appear at the
start of the loop, because it might be some other exec size and cause
us to only loop on the first N channels. We always want 8 in our
current code (since 16 doesn't work so we don't do 16-wide fragment in
that case).
Fixes loop-03.vert, which was triggering the assertions.
Eric Anholt [Fri, 12 Aug 2011 12:15:50 +0000 (05:15 -0700)]
i965/vs: Remove remaining use of foreach_iter.
Eric Anholt [Thu, 11 Aug 2011 23:27:41 +0000 (16:27 -0700)]
i965/vs: Fix abs/negate handling on attributes.
Fixes glsl-vs-neg-attribute and glsl-vs-abs-attribute.
Eric Anholt [Thu, 11 Aug 2011 15:09:10 +0000 (08:09 -0700)]
i965/vs: Avoid generating a MOV for most ir_assignment handling.
Removes an average of 11.5% of instructions in 54% of vertex shaders
in shader-db.
Eric Anholt [Thu, 11 Aug 2011 16:52:08 +0000 (09:52 -0700)]
i965/vs: Run the shader backend at link time and return compile failures.
Link failure is something that shouldn't happen, but we sometimes want
it during development. The precompile also allows analysis of shader
codegen with shader-db.
Eric Anholt [Tue, 16 Aug 2011 01:40:14 +0000 (18:40 -0700)]
i965: Fix assertion failure on a loop consisting of while (true) { break }.
On enabling the precompile step in the VS, we tripped over this
assertion failure in glsl-link-bug-30552.
Eric Anholt [Thu, 11 Aug 2011 16:17:18 +0000 (09:17 -0700)]
i965/vs: Fix the trivial register allocator's failure path.
Eric Anholt [Wed, 10 Aug 2011 21:13:23 +0000 (14:13 -0700)]
i965/vs: Add support for if(any(bvec)) on gen6.
Eric Anholt [Wed, 10 Aug 2011 18:38:42 +0000 (11:38 -0700)]
i965/vs: Add support for GL_FIXED attributes.
Fixes arb_es2_compatibility-fixed-type
Eric Anholt [Tue, 9 Aug 2011 22:19:26 +0000 (15:19 -0700)]
i965/vs: Clamp vertex color outputs when required by ARB_color_buffer_float.
Fixes glsl-vs-vertex-color.
Eric Anholt [Tue, 9 Aug 2011 22:08:47 +0000 (15:08 -0700)]
i965/vs: Fix access of attribute arrays.
By leaving out the column index, we were reading an unallocated
attribute on glsl-mat-attribute.
Eric Anholt [Tue, 9 Aug 2011 21:49:29 +0000 (14:49 -0700)]
i965/vs: Fix builtin uniform setup.
I want to intelligently pack them at some point, but for now we have
the params set up in groups of 4. Fixes glsl-vs-normalscale.
Eric Anholt [Tue, 9 Aug 2011 21:35:38 +0000 (14:35 -0700)]
i965/vs: Add support for loops.
This is copied from brw_fs.cpp, instead of doing the temporary IR
generation that ir_to_mesa does. Fixes glsl-vs-loop and friends.
Eric Anholt [Tue, 9 Aug 2011 19:30:41 +0000 (12:30 -0700)]
i965/vs: Add support for ir_binop_pow.
Fixes vs-pow-float-float.
Eric Anholt [Tue, 9 Aug 2011 18:00:28 +0000 (11:00 -0700)]
i965/vs: Respect the gen6 limitation that math opcodes can't be align16.
Fixes vs-acos-vec3 and friends.
Eric Anholt [Tue, 9 Aug 2011 17:57:09 +0000 (10:57 -0700)]
i965/vs: Fix implementation of ir_unop_any.
We were inheriting whatever previous predicate existed.
Eric Anholt [Mon, 8 Aug 2011 22:56:11 +0000 (15:56 -0700)]
i965/vs: Slightly improve the trivial reg allocator to skip unused regs.
This fixes most of the regressions in the vs array test set from the
varying array indexing work, since the giant array that was originally
allocated in virtual GRF space never gets used and is only ever
read/stored from scratch space.
Eric Anholt [Mon, 8 Aug 2011 00:09:12 +0000 (17:09 -0700)]
i965: Add gen6 disassembly for DP render cache messages.
Eric Anholt [Sun, 7 Aug 2011 20:38:50 +0000 (13:38 -0700)]
i965/vs: Enable variable array indexing in the VS.
Eric Anholt [Sun, 7 Aug 2011 20:36:11 +0000 (13:36 -0700)]
i965/vs: Add support for scratch read/write codegen.
Eric Anholt [Sun, 7 Aug 2011 20:16:06 +0000 (13:16 -0700)]
i965: Make some EU emit code for DP read/write messages non-static.
We keep building these strange interfaces for DP read/write where
there's a helper function with some partially-specific,
partially-general controls, which is used in exactly one place in code
generation. Making these public will let us set up those instructions
in the one place they're to be generated.
Eric Anholt [Sun, 7 Aug 2011 19:15:26 +0000 (12:15 -0700)]
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
Eric Anholt [Sun, 7 Aug 2011 22:21:25 +0000 (15:21 -0700)]
i965/vs: Reserve MRF 14/15 for array loads/register unspilling.
Eric Anholt [Sun, 7 Aug 2011 17:59:39 +0000 (10:59 -0700)]
i965/vs: Track the variable index of array accesses.
This isn't used currently, as we lower all array accesses.
Eric Anholt [Sun, 7 Aug 2011 17:47:54 +0000 (10:47 -0700)]
i965: Add remaining scratch space setup emit to unit states.
Eric Anholt [Sun, 7 Aug 2011 17:44:15 +0000 (10:44 -0700)]
i965: Set up allocation of a VS scratch space if required.
Eric Anholt [Sun, 7 Aug 2011 17:43:49 +0000 (10:43 -0700)]
i965: Remove dead brw->wm.max_threads field.
Eric Anholt [Sat, 6 Aug 2011 04:53:00 +0000 (21:53 -0700)]
i965/vs: Add support for VUEs larger than a single URB write.
Fixes glsl-max-varyings.
Eric Anholt [Sat, 6 Aug 2011 04:22:36 +0000 (21:22 -0700)]
i965/vs: Avoid generating extra moves when setting up large ir_constants.
We were also screwing up the types in the process, and just not
emitting moves was easier.
Eric Anholt [Sat, 6 Aug 2011 03:54:25 +0000 (20:54 -0700)]
i965/vs: Fix types of varying outputs.
For structs/arrays/matrices, they were ending up as uint because we
forgot to set them. All varyings in GLSL 1.20 are of base type float,
so just force the matter here (which gets inherited at
emit_urb_writes() time).
Fixes vs-varying-array-mat2-col-rd.
Eric Anholt [Sat, 6 Aug 2011 03:46:03 +0000 (20:46 -0700)]
i965/vs: Handle assignment of structures/arrays/matrices better.
This gets the right types on the instructions, as well as emitting
minimal swizzles/writemasks.
Eric Anholt [Sat, 6 Aug 2011 03:26:48 +0000 (20:26 -0700)]
i965/vs: Don't forget to set up assignment condition code for arrays/structs.
Fixes vs-uniform-array-mat2-index-col-rd.
Eric Anholt [Sat, 6 Aug 2011 03:16:21 +0000 (20:16 -0700)]
i965/vs: Apply the gen6 math workaround for math1 instructions.
Fixes glsl-vs-masked-cos.
Eric Anholt [Sat, 6 Aug 2011 03:03:31 +0000 (20:03 -0700)]
i965/vs: Add support for if(any_nequal()) and if(all_equal()) on gen6.
Fixes vs-temp-array-mat2-col-rd.shader_test.
Eric Anholt [Sat, 6 Aug 2011 02:40:46 +0000 (19:40 -0700)]
i965/vs: Add support for dot product opcodes.
Fixes glsl-vs-dot-vec2.
Eric Anholt [Sat, 6 Aug 2011 02:38:44 +0000 (19:38 -0700)]
i965/vs: Fix the types of array/struct dereferences.
Fixes glsl-vs-arrays-3.
Eric Anholt [Sat, 6 Aug 2011 02:31:53 +0000 (19:31 -0700)]
i965/vs: Drop the assertion about dst.reg_offset == 0.
Adding the offset is the right thing to do here, and fixes
glsl-vs-mat-add-1.
Eric Anholt [Sat, 6 Aug 2011 02:29:41 +0000 (19:29 -0700)]
i965/vs: Use an appropriate swizzle on src regs from variables.
Fixes glsl-vs-if-bool.
Eric Anholt [Sat, 6 Aug 2011 02:18:31 +0000 (19:18 -0700)]
i965/vs: Fix support for zero uniforms in use.
We were looking for attributes in the wrong place, and pointlessly
doing the work on gen6 at all.
Eric Anholt [Sat, 6 Aug 2011 02:12:16 +0000 (19:12 -0700)]
i965/vs: Fix support for "IF" instructions by copying brw_fs_visitor.cpp.
Fixes glsl-vs-if-greater.
Eric Anholt [Sat, 6 Aug 2011 02:05:42 +0000 (19:05 -0700)]
i965/vs: Disable loops for now until rendering is generally correct.
Eric Anholt [Fri, 5 Aug 2011 23:37:18 +0000 (16:37 -0700)]
i965/vs: Fix ir_swizzle handling.
I decided to refactor it a bit in adapting ir_to_mesa.cpp code, and
mangled it. Fixes glsl-vs-cross-2.
Eric Anholt [Fri, 5 Aug 2011 23:35:24 +0000 (16:35 -0700)]
i965/vs: Allocate storage for "auto" variables just like temps.
Fixes segfault in glsl-vs-cross-2.
Eric Anholt [Fri, 5 Aug 2011 23:31:30 +0000 (16:31 -0700)]
i965/vs: Allow scalar values in assignments, too.
Fixes glsl-vs-all-02 and many other tests.
Eric Anholt [Fri, 5 Aug 2011 23:29:48 +0000 (16:29 -0700)]
i965/vs: Don't emit an extra copy of the vertex position.
Fixes glsl-vs-abs-neg, glsl-vs-all-01, and probably many other tests.
Eric Anholt [Fri, 5 Aug 2011 23:23:42 +0000 (16:23 -0700)]
i965/vs: Port the fix for clip plane writemasks from brw_vs_emit.c.
Eric Anholt [Fri, 5 Aug 2011 23:18:00 +0000 (16:18 -0700)]
i965/vs: Fix constant vector construction.
Fixes some issues noticed in glsl-vs-all-01.
Eric Anholt [Wed, 4 May 2011 19:50:16 +0000 (12:50 -0700)]
i965/vs: Start adding support for uniforms
There's no clever packing here, no pull constants, and no array support.
Eric Anholt [Mon, 2 May 2011 16:45:40 +0000 (09:45 -0700)]
i965: Start adding the VS visitor and codegen.
The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's
currently controlled by the INTEL_NEW_VS=1 environment variable, and
only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
Eric Anholt [Fri, 5 Aug 2011 19:38:58 +0000 (12:38 -0700)]
i965: Rename math FS_OPCODE_* to SHADER_OPCODE_*.
I want to just use the same enums in the VS.
Eric Anholt [Tue, 3 May 2011 17:55:50 +0000 (10:55 -0700)]
i965: Create a shared enum for hardware and compiler-internal opcodes.
This should make gdbing more pleasant, and it might be used in sharing
part of the codegen between the VS and FS backends.
Eric Anholt [Tue, 3 May 2011 22:27:38 +0000 (15:27 -0700)]
i965: Generate driver-specific IR for non-fragment shaders as well.
This will be used by the new vertex shader backend. The scalarizing
passes are skipped for non-fragment, since vertex and geometry threads
are based on vec4s.
Brian Paul [Tue, 16 Aug 2011 19:05:26 +0000 (13:05 -0600)]
mesa: ChooseTextureFormat() returns gl_format, not GLuint
Paul Berry [Fri, 12 Aug 2011 17:20:34 +0000 (10:20 -0700)]
glsl: Fix type error when lowering integer divisions
This patch fixes a bug when lowering an integer division:
x/y
to a multiplication by a reciprocal:
int(float(x)*reciprocal(float(y)))
If x was a plain int and y was an ivecN, the lowering pass
incorrectly assigned the type of the product to be float, when in fact
it should be vecN. This caused mesa to abort with an IR validation
error.
Fixes piglit tests {fs,vs}-op-div-int-ivec{2,3,4}.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Tue, 16 Aug 2011 17:06:55 +0000 (19:06 +0200)]
softpipe: fix an obvious copy-paste error in get_query_result
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Tue, 16 Aug 2011 16:48:11 +0000 (18:48 +0200)]
st/dri: remove an unused-but-set variable
Marek Olšák [Tue, 16 Aug 2011 17:35:10 +0000 (19:35 +0200)]
r600g: rename bc -> bytecode
It took me a while to figure out what it stands for.
Benjamin Franzke [Tue, 16 Aug 2011 17:23:18 +0000 (19:23 +0200)]
egl: Add include paths for platform autodetection
Needed since commit
85fe9484.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40145
Cooper Yuan [Tue, 16 Aug 2011 12:37:13 +0000 (20:37 +0800)]
dri2: check if context is valid before flushing the pipe
Marek Olšák [Mon, 15 Aug 2011 21:37:44 +0000 (23:37 +0200)]
r600g: expose ARB_ES2_compatibility by claiming fixed-point format support
I also needed to make some changes in u_vbuf_mgr in order to override
the caps from the driver and enable the fallback even though the driver
claims the format is supported.
Marek Olšák [Mon, 15 Aug 2011 17:37:33 +0000 (19:37 +0200)]
noop: redirect the get_param/is_format.. queries to the underlying driver
Marek Olšák [Mon, 15 Aug 2011 18:52:44 +0000 (20:52 +0200)]
u_blitter: restore some states conditionally
Marek Olšák [Wed, 10 Aug 2011 00:58:40 +0000 (02:58 +0200)]
u_blitter: rename util_blitter_copy_region -> util_blitter_copy_texture
Marek Olšák [Sun, 14 Aug 2011 19:21:38 +0000 (21:21 +0200)]
r600g: consolidate two files r600d.h
Marek Olšák [Sun, 7 Aug 2011 19:14:38 +0000 (21:14 +0200)]
r600g: set read/write usage flags for each relocation
This takes advantage of the new GEM_WAIT ioctl when mapping buffers.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Sun, 7 Aug 2011 17:18:16 +0000 (19:18 +0200)]
winsys/radeon: take advantage of the new ioctl
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Sun, 7 Aug 2011 17:04:37 +0000 (19:04 +0200)]
winsys/radeon: hook up the new DRM_RADEON_GEM_WAIT ioctl
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Sun, 7 Aug 2011 16:42:29 +0000 (18:42 +0200)]
winsys/radeon: remove broken bo-is-busy-for-write guessing
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 05:05:07 +0000 (07:05 +0200)]
r600g: enable thread offloading
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 04:33:04 +0000 (06:33 +0200)]
r600g: undefine RADEON_CTX_MAX_PM4
winsys/radeon has its own definition.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 04:23:59 +0000 (06:23 +0200)]
r600g: don't include radeon_drm.h and xf86drm.h
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 04:19:17 +0000 (06:19 +0200)]
winsys/radeon: remove the device file descriptor from the interface
r600g doesn't need it anymore.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 04:17:39 +0000 (06:17 +0200)]
r600g: remove an unused parameter from r600_bo_destroy
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 04:11:45 +0000 (06:11 +0200)]
r600g: merge radeon_bo with r600_bo
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 03:40:16 +0000 (05:40 +0200)]
r600g: remove radeon_bo::handle
This should be private to radeon_winsys.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 02:27:48 +0000 (04:27 +0200)]
r600g: use buffer_map/unmap from radeon_winsys
This also drops the unneeded bo_busy/wait functions.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 01:38:20 +0000 (03:38 +0200)]
r600g: set the flush callback in radeon_winsys
I have also renamed the winsys function.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 01:19:33 +0000 (03:19 +0200)]
r600g: get tiling flags using radeon_winsys
Also remove some unused fence-related leftovers.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 4 Aug 2011 01:07:42 +0000 (03:07 +0200)]
r600g: get winsys_handle using radeon_winsys
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>