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Hans Wennborg [Thu, 16 May 2019 12:08:34 +0000 (12:08 +0000)]
Revert r360876 "[Object] Change object::SectionRef::getContents() to return Expected<StringRef>"
It broke the Clang build, see llvm-commits thread.
> Expected<ArrayRef<uint8_t>> may be better but use Expected<StringRef> for now.
>
> Follow-up of D61781.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360878
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Matt Arsenault [Thu, 16 May 2019 12:06:41 +0000 (12:06 +0000)]
AMDGPU/GlobalISel: Correct regbank for 1-bit and/or/xor
Bool values should use the scc/vcc regbank since r350611.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360877
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Fangrui Song [Thu, 16 May 2019 11:33:48 +0000 (11:33 +0000)]
[Object] Change object::SectionRef::getContents() to return Expected<StringRef>
Expected<ArrayRef<uint8_t>> may be better but use Expected<StringRef> for now.
Follow-up of D61781.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360876
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Cullen Rhodes [Thu, 16 May 2019 09:42:22 +0000 (09:42 +0000)]
[AArch64][SVE2] Asm: implement CMLA/SQRDCMLAH instructions
Summary:
This patch adds support for the indexed and unpredicated vectors forms
of the CMLA and SQRDCMLAH instructions.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D61906
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360871
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Cullen Rhodes [Thu, 16 May 2019 09:33:44 +0000 (09:33 +0000)]
[AArch64][SVE2] Asm: implement CDOT instruction
Summary:
The complex DOT instructions perform a dot-product on quadtuplets from
two source vectors and the resuling wide real or wide imaginary is
accumulated into the destination register. The instructions come in two
forms:
Vector form, e.g.
cdot z0.s, z1.b, z2.b, #90 - complex dot product on four 8-bit quad-tuplets,
accumulating results in 32-bit elements. The
complex numbers in the second source vector are
rotated by 90 degrees.
cdot z0.d, z1.h, z2.h, #180 - complex dot product on four 16-bit quad-tuplets,
accumulating results in 64-bit elements.
The complex numbers in the second source
vector are rotated by 180 degrees.
Indexed form, e.g.
cdot z0.s, z1.b, z2.b[3], #0 - complex dot product on four 8-bit quad-tuplets,
with specified quadtuplet from second source vector,
accumulating results in 32-bit elements.
cdot z0.d, z1.h, z2.h[1], #0 - complex dot product on four 16-bit quad-tuplets,
with specified quadtuplet from second source vector,
accumulating results in 64-bit elements.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer, rovka
Differential Revision: https://reviews.llvm.org/D61903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360870
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Cullen Rhodes [Thu, 16 May 2019 09:07:26 +0000 (09:07 +0000)]
[AArch64][SVE2] Asm: add unpredicated integer multiply instructions
Summary:
Add support for the following instructions:
* MUL (indexed and unpredicated vectors forms)
* SQDMULH (indexed and unpredicated vectors forms)
* SQRDMULH (indexed and unpredicated vectors forms)
* SMULH (unpredicated, predicated form added in SVE)
* UMULH (unpredicated, predicated form added in SVE)
* PMUL (unpredicated)
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer, rovka
Differential Revision: https://reviews.llvm.org/D61902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360867
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Fangrui Song [Thu, 16 May 2019 08:31:22 +0000 (08:31 +0000)]
Add Triple::isPPC64()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360864
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George Rimar [Thu, 16 May 2019 06:22:51 +0000 (06:22 +0000)]
[llvm-readobj] - Revert r360676 partially. NFC.
In the r360676 "Apply clang format. NFC" I applied clang-format
for whole ELFDumper.cpp. It caused a little discussion,
one of the points mentioned was that previously nicely lined up
tables are not so nice now.
This patch reverts them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360860
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Clement Courbet [Thu, 16 May 2019 06:18:02 +0000 (06:18 +0000)]
Reland r360771 "[MergeICmps] Simplify the code."
This revision does not seem to be the culprit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360859
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Igor Kudrin [Thu, 16 May 2019 05:23:13 +0000 (05:23 +0000)]
[IRMover] Improve diagnostic messages for conflicting metadata
This does the similar for error messages as rL344011 has done for warnings.
With llvm::lto::LTO, the error might appear when LTO::run() is executed.
In that case, the calling code cannot know which module causes the error
and, subsequently, cannot hint the user.
Differential Revision: https://reviews.llvm.org/D61880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360857
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Matt Arsenault [Thu, 16 May 2019 04:09:06 +0000 (04:09 +0000)]
GlobalISel: Add buildFConstant for APFloat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360853
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Matt Arsenault [Thu, 16 May 2019 04:08:55 +0000 (04:08 +0000)]
GlobalISel: Add some FP instructions to MachineIRBuilder
This makes FP legalization code more convenient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360852
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Matt Arsenault [Thu, 16 May 2019 04:08:46 +0000 (04:08 +0000)]
GlobalISel: Fix indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360851
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Matt Arsenault [Thu, 16 May 2019 04:08:39 +0000 (04:08 +0000)]
GlobalISel: Add G_FCOPYSIGN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360850
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Matt Arsenault [Thu, 16 May 2019 04:08:25 +0000 (04:08 +0000)]
Fix missing const
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360849
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Yevgeny Rouban [Thu, 16 May 2019 03:39:09 +0000 (03:39 +0000)]
Fix prof branch_weights in entry_counts_missing_dbginfo.ll test
Removed extra parameter from !prof branch_weights metadata of
a call instruction according to the spec.
Differential Revision: https://reviews.llvm.org/D61932
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360843
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Eric Christopher [Thu, 16 May 2019 01:07:54 +0000 (01:07 +0000)]
Fix typo in comment of CSAction -> Action.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360834
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Lang Hames [Thu, 16 May 2019 00:21:10 +0000 (00:21 +0000)]
[ORC] Modify DenseMap hashing for SymbolStringPtrs.
Modifies the DenseMapInfo<SymbolStringPtr>::getHashValue method to take its
argument by const-ref rather than by value (to avoid unnecessary ref-counting
operations) and to defer to DenseMapInfo<void*> for the hash value computation
(since SymbolStringPtrs are just pointers under the hood).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360831
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Lang Hames [Thu, 16 May 2019 00:21:07 +0000 (00:21 +0000)]
[JITLink][MachO] Use getSymbol64TableEntry for 64-bit MachO files.
Fixes a think-o. No test case: The nlist and nlist64 data structures happen to
line up for this field, so there's no way to construct a failing test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360830
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Vitaly Buka [Thu, 16 May 2019 00:19:37 +0000 (00:19 +0000)]
Fix GN build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360829
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Craig Topper [Wed, 15 May 2019 21:59:53 +0000 (21:59 +0000)]
[X86] Delay creating index register negations during address matching until after we know for sure the match will succeed
If we're trying to match an LEA, its possible the LEA match will be deemed unprofitable. In which case the negation we created in matchAddress would be left dangling in the SelectionDAG. This could artificially increase use counts for other nodes in the DAG. Though I don't have an example of that. But it just seems like bad form to have dangling nodes in isel.
Differential Revision: https://reviews.llvm.org/D61047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360823
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Reid Kleckner [Wed, 15 May 2019 21:46:05 +0000 (21:46 +0000)]
[codeview] Fix SDNode representation of annotation labels
Before this change, they were erroneously constructed with the EH_LABEL
SDNode opcode, which caused other passes to interact with them in
incorrect ways. See the FIXME about fastisel that this addresses in the
existing test case.
Fixes PR41890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360818
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Simon Atanasyan [Wed, 15 May 2019 21:26:25 +0000 (21:26 +0000)]
[mips] Use range-based `for` loops. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360817
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Mandeep Singh Grang [Wed, 15 May 2019 21:23:41 +0000 (21:23 +0000)]
[AArch64] only indicate CFI on Windows if we emitted CFI
Summary:
Otherwise, we emit directives for CFI without any actual CFI opcodes to
go with them, which causes tools to malfunction. The technique is
similar to what the x86 backend already does.
Fixes https://bugs.llvm.org/show_bug.cgi?id=40876
Patch by: froydnj (Nathan Froyd)
Reviewers: mstorsjo, eli.friedman, rnk, mgrang, ssijaric
Reviewed By: rnk
Subscribers: javed.absar, kristof.beyls, llvm-commits, dmajor
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61960
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360816
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Craig Topper [Wed, 15 May 2019 21:16:28 +0000 (21:16 +0000)]
[X86] Strengthen type constraints on some specialized X86 ISD opcodes that don't have any flexibility. NFC
These particular instructions only operate on 128-bit vectors and have no wider equivalents. And the
element size is always known.
One could argue that MOVSS/MOVSD could be merged, but that's probably disruptive to code in
X86ISelLowering and probably low value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360815
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Roman Lebedev [Wed, 15 May 2019 21:15:44 +0000 (21:15 +0000)]
[NFC][InstCombine] Add some more tests for pulling binops through shifts
The ashr variant may see relaxation in https://reviews.llvm.org/D61938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360814
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Reid Kleckner [Wed, 15 May 2019 20:53:39 +0000 (20:53 +0000)]
[codeview] Finish support for reading and writing S_ANNOTATION records
Implement dumping via llvm-pdbutil and llvm-readobj.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360813
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Cameron McInally [Wed, 15 May 2019 20:48:50 +0000 (20:48 +0000)]
Revert llvm-svn: 360807
Somehow submitted this patch twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360812
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Cameron McInally [Wed, 15 May 2019 20:27:37 +0000 (20:27 +0000)]
Pre-commit unary fneg tests to InstSimplify
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360808
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Cameron McInally [Wed, 15 May 2019 20:27:35 +0000 (20:27 +0000)]
Add unary fneg to InstSimplify/fp-nan.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360807
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Pete Couperus [Wed, 15 May 2019 19:46:17 +0000 (19:46 +0000)]
Uncomment LLVM_FALLTHROUGH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360798
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Cameron McInally [Wed, 15 May 2019 19:37:03 +0000 (19:37 +0000)]
Add unary fneg to InstSimplify/fp-nan.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360797
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Taewook Oh [Wed, 15 May 2019 19:35:38 +0000 (19:35 +0000)]
[PredicateInfo] Do not process unreachable operands.
Summary: We should excluded unreachable operands from processing as their DFS visitation order is undefined. When `renameUses` function sorts `OpsToRename` (https://fburl.com/d2wubn60), the comparator assumes that the parent block of the operand has a corresponding dominator tree node. This is not the case for unreachable operands and crashes the compiler.
Reviewers: dberlin, mgrang, davide
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360796
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Nicolai Haehnle [Wed, 15 May 2019 17:48:10 +0000 (17:48 +0000)]
[MachineOperand] Add a ChangeToGA method
Summary:
Analogous to the other ChangeToXXX methods. See the next patch for a
use case.
Change-Id: I6548d614706834fb9109ab3c8fe915e9c6ece2a7
Reviewers: arsenm, kzhuravl
Subscribers: wdng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360789
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Nicolai Haehnle [Wed, 15 May 2019 17:29:58 +0000 (17:29 +0000)]
RegAlloc: try to fail more gracefully when out of registers
Summary:
The emitError path allows the program to continue, unlike report_fatal_error.
This is friendlier to use cases where LLVM is embedded in a larger program,
because the caller may be able to deal with the error somewhat gracefully.
Change the number of requested NOP bytes in the AArch64 and PowerPC
test cases to avoid triggering an unrelated assertion. The compilation
still fails, as verified by the test.
Change-Id: Iafb9ca341002a597b82e59ddc7a1f13c78758e3d
Reviewers: arsenm, MatzeB
Subscribers: qcolombet, nemanjai, wdng, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360786
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Thomas Preud'homme [Wed, 15 May 2019 15:20:45 +0000 (15:20 +0000)]
[FileCheck] Fix sphinx error: Make input be gas block
Summary:
Change example of input text from being llvm block to being gas block
since that text is made-up assembly.
Reviewers: jhenderson, jdenny, probinson, arichardson
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360781
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Hiroshi Yamauchi [Wed, 15 May 2019 15:15:16 +0000 (15:15 +0000)]
[JumpThreading] A bug fix for stale loop info after unfold select
Summary:
The return value of a TryToUnfoldSelect call was not checked, which led to an
incorrectly preserved loop info and some crash.
The original crash was reported on https://reviews.llvm.org/D59514.
Reviewers: davidxl, amehsan
Reviewed By: davidxl
Subscribers: fhahn, brzycki, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360780
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Ryan Taylor [Wed, 15 May 2019 14:43:55 +0000 (14:43 +0000)]
[AMDGPU] Increases available SGPR for Calling Convention
Summary:
SGPR in CC can be either hw initialized or set by other chained shaders
and so this increases the SGPR count availalbe to CC to 105.
Change-Id: I3dfadc750fe4a3e2bd07117a2899fd13f3e2fef3
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61261
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360778
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Cameron McInally [Wed, 15 May 2019 14:31:33 +0000 (14:31 +0000)]
Teach InstSimplify -X + X --> 0.0 about unary FNeg
Differential Revision: https://reviews.llvm.org/D61916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360777
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Clement Courbet [Wed, 15 May 2019 14:21:59 +0000 (14:21 +0000)]
Revert r360771 "[MergeICmps] Simplify the code."
Breaks a bunch of builbdots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360776
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Clement Courbet [Wed, 15 May 2019 14:00:45 +0000 (14:00 +0000)]
[MergeICmps] Fix r360771.
Twine references a StringRef by reference, not value...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360775
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Stephen Tozer [Wed, 15 May 2019 13:41:44 +0000 (13:41 +0000)]
Revert "[Salvage] Change salvage debug info implementation to use DW_OP_LLVM_convert where needed"
This reverts r360772 due to build issues.
Reverted commit:
17dd4d7403770bd683675e45f5517e0cdb8f9b2b.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360773
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Stephen Tozer [Wed, 15 May 2019 13:15:48 +0000 (13:15 +0000)]
[Salvage] Change salvage debug info implementation to use DW_OP_LLVM_convert where needed
Fixes issue: https://bugs.llvm.org/show_bug.cgi?id=40645
Previously, LLVM had no functional way of performing casts inside of a
DIExpression(), which made salvaging cast instructions other than Noop
casts impossible. With the recent addition of DW_OP_LLVM_convert this
salvaging is now possible, and so can be used to fix the attached bug as
well as any cases where SExt instruction results are lost in the
debugging metadata. This patch introduces this fix by expanding the
salvage debug info method to cover these cases using the new operator.
Differential revision: https://reviews.llvm.org/D61184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360772
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Clement Courbet [Wed, 15 May 2019 13:04:24 +0000 (13:04 +0000)]
[MergeICmps] Simplify the code.
Instead of patching the original blocks, we now generate new blocks and
delete the old blocks. This results in simpler code with a less twisted
control flow (see the change in `entry-block-shuffled.ll`).
This will make https://reviews.llvm.org/D60318 simpler by making it more
obvious where control flow created and deleted.
Reviewers: gchatelet
Subscribers: hiraditya, llvm-commits, spatel
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360771
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Simon Pilgrim [Wed, 15 May 2019 13:03:10 +0000 (13:03 +0000)]
Revert rL360675 : [APFloat] APFloat::Storage::Storage - fix use after move
This was mentioned both in https://www.viva64.com/en/b/0629/ and by scan-build checks
........
There's concerns this may just introduce a use-after-free instead.....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360770
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David Green [Wed, 15 May 2019 12:58:02 +0000 (12:58 +0000)]
[ARM] Don't use the Machine Scheduler for cortex-m at minsize
The new cortex-m schedule in rL360768 helps performance, but can increase the
amount of high-registers used. This, on average, ends up increasing the
codesize by a fair amount (because less instructions are converted from T2 to
T1). On cortex-m at -Oz, where we are quite size-paranoid, it is better to use
the existing DAG scheduler with the RegPressure scheduling preference (at least
until the issues around T2 vs T1 instructions can be improved).
I have also made sure that the Sched::RegPressure dag scheduler is always
chosen for MinSize.
The test shows one case where we increase the number of registers used.
Differential Revision: https://reviews.llvm.org/D61882
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360769
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David Green [Wed, 15 May 2019 12:41:58 +0000 (12:41 +0000)]
[ARM] Cortex-M4 schedule
This patch adds a simple Cortex-M4 schedule, renaming the existing M3
schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM:
https://developer.arm.com/docs/ddi0439/latest
Most of these are 1, with the important exception being loads taking 2
cycles. A few others are also higher, but I don't believe they make a
large difference. I've repurposed the M3 schedule as the latencies are
mostly the same between the two cores, with the M4 having more FP and
DSP instructions. We also turn on MISched and UseAA for the cores that
now use this.
It also adds some schedule Write's to various instruction to make things
simpler.
Differential Revision: https://reviews.llvm.org/D54142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360768
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Nico Weber [Wed, 15 May 2019 12:08:45 +0000 (12:08 +0000)]
gn build: Merge r360671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360766
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Simon Atanasyan [Wed, 15 May 2019 12:05:27 +0000 (12:05 +0000)]
[mips] LLVM and GAS now use same instructions for CFA Definition. NFCI
LLVM previously used `DW_CFA_def_cfa` instruction in .eh_frame to set
the register and offset for current CFA rule. We change it to
`DW_CFA_def_cfa_register` which is the same one used by GAS that only
changes the register but keeping the old offset.
Patch by Mirko Brkusanin.
Differential Revision: https://reviews.llvm.org/D61899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360765
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Nico Weber [Wed, 15 May 2019 12:03:10 +0000 (12:03 +0000)]
gn build: Run `git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360764
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Tim Northover [Wed, 15 May 2019 12:01:04 +0000 (12:01 +0000)]
arm64_32: add some unittests that were in the wrong commit.
Accidentally dropped them when committing the arm64_32 binutils support.
There's no change to real code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360763
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Roman Lebedev [Wed, 15 May 2019 10:24:38 +0000 (10:24 +0000)]
[NFC][InstCombine] Regenerate trunc.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360759
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Florian Hahn [Wed, 15 May 2019 10:05:49 +0000 (10:05 +0000)]
[LV] Move getScalarizationOverhead and vector call cost computations to CM. (NFC)
This reduces the number of parameters we need to pass in and they seem a
natural fit in LoopVectorizationCostModel. Also simplifies things for
D59995.
As a follow up refactoring, we could only expose a expose a
shouldUseVectorIntrinsic() helper in LoopVectorizationCostModel, instead
of calling getVectorCallCost/getVectorIntrinsicCost in
InnerLoopVectorizer/VPRecipeBuilder.
Reviewers: Ayal, hsaito, dcaballe, rengolin
Reviewed By: rengolin
Differential Revision: https://reviews.llvm.org/D61638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360758
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Clement Courbet [Wed, 15 May 2019 08:21:18 +0000 (08:21 +0000)]
[[DAGCombiner][NFC] Add a comment.
As suggested in D61846.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360755
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Craig Topper [Wed, 15 May 2019 04:15:46 +0000 (04:15 +0000)]
[X86] Use OR32mi8Locked instead of LOCK_OR32mi8 in emitLockedStackOp.
They encode the same way, but OR32mi8Locked sets hasUnmodeledSideEffects set
which should be stronger than the mayLoad/mayStore on LOCK_OR32mi8. I think
this makes sense since we are using it as a fence.
This also seems to hide the operation from the speculative load hardening pass
so I've reverted r360511.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360747
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Fangrui Song [Wed, 15 May 2019 03:08:21 +0000 (03:08 +0000)]
Fix 2-field llvm.global_ctors `REQUIRES: asserts` tests after rL360742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360743
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Fangrui Song [Wed, 15 May 2019 02:35:32 +0000 (02:35 +0000)]
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
The 3-field form was introduced by D3499 in 2014 and the legacy 2-field
form was planned to be removed in LLVM 4.0
For the textual format, this patch migrates the existing 2-field form to
use the 3-field form and deletes the compatibility code.
test/Verifier/global-ctors-2.ll checks we have a friendly error message.
For bitcode, lib/IR/AutoUpgrade UpgradeGlobalVariables will upgrade the
2-field form (add i8* null as the third field).
Reviewed By: rnk, dexonsmith
Differential Revision: https://reviews.llvm.org/D61547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360742
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Philip Reames [Wed, 15 May 2019 01:39:07 +0000 (01:39 +0000)]
[NFC] Reuse a helper function to eliminate duplicate code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360740
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Richard Trieu [Wed, 15 May 2019 01:28:30 +0000 (01:28 +0000)]
[XCore] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360738
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Richard Trieu [Wed, 15 May 2019 01:17:58 +0000 (01:17 +0000)]
[X86] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360736
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Richard Trieu [Wed, 15 May 2019 01:03:00 +0000 (01:03 +0000)]
[WebAssembly] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360735
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Richard Trieu [Wed, 15 May 2019 00:46:18 +0000 (00:46 +0000)]
[SystemZ] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360734
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Richard Trieu [Wed, 15 May 2019 00:35:37 +0000 (00:35 +0000)]
[Sparc] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360733
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Richard Trieu [Wed, 15 May 2019 00:24:15 +0000 (00:24 +0000)]
[RISCV] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360732
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Richard Trieu [Wed, 15 May 2019 00:09:58 +0000 (00:09 +0000)]
[PowerPC] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360731
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Richard Trieu [Tue, 14 May 2019 23:56:18 +0000 (23:56 +0000)]
[NVPTX] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360729
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Richard Trieu [Tue, 14 May 2019 23:45:18 +0000 (23:45 +0000)]
[MSP430] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360728
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Richard Trieu [Tue, 14 May 2019 23:34:37 +0000 (23:34 +0000)]
[Mips] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360727
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Richard Trieu [Tue, 14 May 2019 23:17:18 +0000 (23:17 +0000)]
[Lanai] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360726
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Richard Trieu [Tue, 14 May 2019 23:04:55 +0000 (23:04 +0000)]
[Hexagon] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360724
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Richard Trieu [Tue, 14 May 2019 22:54:06 +0000 (22:54 +0000)]
[BPF] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360722
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Richard Trieu [Tue, 14 May 2019 22:41:58 +0000 (22:41 +0000)]
[AVR] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360721
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Philip Reames [Tue, 14 May 2019 22:32:42 +0000 (22:32 +0000)]
Use an offset from TOS for idempotent rmw locked op lowering
This was the portion split off D58632 so that it could follow the redzone API cleanup. Note that I changed the offset preferred from -8 to -64. The difference should be very minor, but I thought it might help address one concern which had been previously raised.
Differential Revision: https://reviews.llvm.org/D61862
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360719
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Richard Trieu [Tue, 14 May 2019 22:29:50 +0000 (22:29 +0000)]
[ARM] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360718
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Richard Trieu [Tue, 14 May 2019 22:06:04 +0000 (22:06 +0000)]
[ARC] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360716
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Richard Trieu [Tue, 14 May 2019 21:54:37 +0000 (21:54 +0000)]
[AMDGPU] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360713
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Richard Trieu [Tue, 14 May 2019 21:33:53 +0000 (21:33 +0000)]
[AArch64] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360709
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Leonard Chan [Tue, 14 May 2019 21:17:21 +0000 (21:17 +0000)]
[NewPM] Port HWASan and Kernel HWASan
Port hardware assisted address sanitizer to new PM following the same guidelines as msan and tsan.
Changes:
- Separate HWAddressSanitizer into a pass class and a sanitizer class.
- Create new PM wrapper pass for the sanitizer class.
- Use the getOrINsert pattern for some module level initialization declarations.
- Also enable kernel-kwasan in new PM
- Update llvm tests and add clang test.
Differential Revision: https://reviews.llvm.org/D61709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360707
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Roman Lebedev [Tue, 14 May 2019 20:17:04 +0000 (20:17 +0000)]
[NFC][CodeGen][X86][AArch64] Add and-const-mask + const-shift pattern tests
Unlike instcombine, we currently don't turn and+shift into shift+and.
We probably should, likely unconditionally.
While i'm adding only all-ones (potentially shifted) mask,
this obviously isn't limited to any particular mask pattern:
https://rise4fun.com/Alive/kmX
Related to https://bugs.llvm.org/show_bug.cgi?id=41874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360706
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Florian Hahn [Tue, 14 May 2019 19:41:36 +0000 (19:41 +0000)]
[LICM] Allow AliasSetMap to contain top-level loops.
When an outer loop gets deleted by a different pass, before LICM visits
it, we cannot clean up its sub-loops in AliasSetMap, because at the
point we receive the deleteAnalysisLoop callback for the outer loop, the loop
object is already invalid and we cannot access its sub-loops any longer.
Reviewers: asbirlea, sanjoy, chandlerc
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D61904
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360704
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Dmitry Preobrazhensky [Tue, 14 May 2019 19:16:24 +0000 (19:16 +0000)]
[AMDGPU][GFX8][GFX9] Corrected predicate of v_*_co_u32 aliases
Reviewers: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D61905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360702
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Nikita Popov [Tue, 14 May 2019 18:53:47 +0000 (18:53 +0000)]
[LVI][CVP] Add support for abs/nabs select pattern flavor
Based on ConstantRange support added in D61084, we can now handle
abs and nabs select pattern flavors in LVI.
Differential Revision: https://reviews.llvm.org/D61794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360700
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Alina Sbirlea [Tue, 14 May 2019 18:07:18 +0000 (18:07 +0000)]
[MemorySSA] LoopSimplify preserves MemorySSA only when flag is flipped.
LoopSimplify can preserve MemorySSA after r360270.
But the MemorySSA analysis is retrieved and preserved only when the
EnableMSSALoopDependency is set to true. Use the same conditional to
mark the pass as preserved, otherwise subsequent passes will get an
invalid analysis.
Resolves PR41853.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360697
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Philip Reames [Tue, 14 May 2019 17:50:06 +0000 (17:50 +0000)]
Fix a release mode warning introduced in r360694
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360696
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Philip Reames [Tue, 14 May 2019 17:20:10 +0000 (17:20 +0000)]
[IndVars] Extend reasoning about loop invariant exits to non-header blocks
Noticed while glancing through the code for other reasons. The extension is trivial enough, decided to just do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360694
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Cameron McInally [Tue, 14 May 2019 16:51:18 +0000 (16:51 +0000)]
Support FNeg in SpeculativeExecution pass
Differential Revision: https://reviews.llvm.org/D61910
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360692
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Philip Reames [Tue, 14 May 2019 16:37:29 +0000 (16:37 +0000)]
[Test] Autogen a test for ease of later changing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360690
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Stanislav Mekhanoshin [Tue, 14 May 2019 16:18:00 +0000 (16:18 +0000)]
[AMDGPU] Fixed handling of imemdiate i1 literals
This bug was exposed by the rL360395.
Differential Revision: https://reviews.llvm.org/D61812
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360689
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Tim Renouf [Tue, 14 May 2019 16:17:14 +0000 (16:17 +0000)]
[AMDGPU] Fixed +DumpCode
The +DumpCode attribute is a horrible hack in AMDGPU to embed the
disassembly of the generated code into the elf file. It is used by LLPC
to implement an extension that allows the application to read back the
disassembly of the code. Longer term, we should re-implement that by
using the LLVM disassembler from the Vulkan driver.
Recent LLVM changes broke +DumpCode. With -filetype=asm it crashed, and
with -filetype=obj I think it did not include any instructions, only the
labels. Fixed with this commit: now it has no effect with -filetype=asm,
and works as intended with -filetype=obj.
Differential Revision: https://reviews.llvm.org/D60682
Change-Id: I6436d86fe2ea220d74a643a85e64753747c9366b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360688
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Javed Absar [Tue, 14 May 2019 16:14:24 +0000 (16:14 +0000)]
[ARM][CMSE] Add cmse intrinsics for TT instructions
Defines intrinsics cmse_TT, cmse_TTT, cmse_TTA, cmse_TTAT.
No tests here as the tests are in patches that uses these.
Reviewed By: Todd Snider, Dave Green
Differential Revision: https://reviews.llvm.org/D59888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360687
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Stanislav Mekhanoshin [Tue, 14 May 2019 16:04:03 +0000 (16:04 +0000)]
[AMDGPU] gfx1010 Strengthen some SMEM WAR hazard unit tests. NFC.
Tighten conditions on SMEM WAR hazard unit tests to ensure rejection
of workaround insertion where a s_waitcnt is present in dependency
chain. The current workaround code already conforms to these revise
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360686
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Simon Pilgrim [Tue, 14 May 2019 15:21:28 +0000 (15:21 +0000)]
[X86] Disable shouldFoldConstantShiftPairToMask for scalar shifts on AMD targets (PR40758)
D61068 handled vector shifts, this patch does the same for scalars where there are similar number of pipes for shifts as bit ops - this is true almost entirely for AMD targets where the scalar ALUs are well balanced.
This combine avoids AND immediate mask which usually means we reduce encoding size.
Some tests show use of (slow, scaled) LEA instead of SHL in some cases, but thats due to particular shift immediates - shift+mask generate these just as easily.
Differential Revision: https://reviews.llvm.org/D61830
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360684
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Cullen Rhodes [Tue, 14 May 2019 15:10:16 +0000 (15:10 +0000)]
[AArch64][SVE2] Asm: add SQRDMLAH/SQRDMLSH instructions
Summary:
This patch adds support for the indexed and unpredicated vectors forms of the
SQRDMLAH and SQRDMLSH instructions.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: rovka
Differential Revision: https://reviews.llvm.org/D61515
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360683
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Cullen Rhodes [Tue, 14 May 2019 15:01:00 +0000 (15:01 +0000)]
[AArch64][SVE2] Asm: add integer multiply-add/subtract (indexed) instructions
Summary:
This patch adds support for the following instructions:
MLA mul-add, writing addend (Zda = Zda + Zn * Zm[idx])
MLS mul-sub, writing addend (Zda = Zda + -Zn * Zm[idx])
Predicated forms of these instructions were added in SVE.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: rovka
Differential Revision: https://reviews.llvm.org/D61514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360682
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Paul Robinson [Tue, 14 May 2019 14:51:54 +0000 (14:51 +0000)]
Replace lit feature keyword 'not_COFF' with 'uses_COFF'.
Differential Revision: https://reviews.llvm.org/D61791
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360680
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Fangrui Song [Tue, 14 May 2019 14:37:26 +0000 (14:37 +0000)]
DWARF v5: emit DW_AT_addr_base if DW_AT_low_pc references .debug_addr
The condition !AddrPool.empty() is tested before attachRangesOrLowHighPC(), which may add an entry to AddrPool. We emit DW_AT_low_pc (DW_FORM_addrx) but may incorrectly omit DW_AT_addr_base for LineTablesOnly. This can be easily reproduced:
clang -gdwarf-5 -gmlt -c a.cc
Fix this by moving !AddrPool.empty() below.
This was discovered while investigating an lld crash (fixed by D61889) on such object files: ld.lld --gdb-index a.o
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D61891
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360678
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Lei Huang [Tue, 14 May 2019 14:27:06 +0000 (14:27 +0000)]
[PowerPC] Custom lower known CR bit spills
For known CRBit spills, CRSET/CRUNSET, it is more efficient to load and spill
the known value instead of extracting the bit.
eg. This sequence is currently used to spill a CRUNSET:
crclr 4*cr5+lt
mfocrf r3,4
rlwinm r3,r3,20,0,0
stw r3,132(r1)
This patch custom lower it to:
li r3,0
stw r3,132(r1)
Differential Revision: https://reviews.llvm.org/D61754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360677
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George Rimar [Tue, 14 May 2019 14:22:44 +0000 (14:22 +0000)]
[llvm-readobj] - Apply clang format. NFC.
I am a bit tired of the formatting issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360676
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Simon Pilgrim [Tue, 14 May 2019 14:13:30 +0000 (14:13 +0000)]
[APFloat] APFloat::Storage::Storage - fix use after move
This was mentioned both in https://www.viva64.com/en/b/0629/ and by scan-build checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360675
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Xing Xue [Tue, 14 May 2019 13:54:33 +0000 (13:54 +0000)]
[lit][tests]Add feature libcxx-used and use it in llvm-*-fuzzer tests
When a LLVM binary such as llvm-*-fuzzer is built with libc++, it has dependency on libc++. The path to find shared libraries specified in llvm-*-fuzzer is relative. As a result, these binaries cannot be copied to an arbitrary directory and launched from there. Changes in this patch add a LIT feature to indicate that libc++ is used to build and, based on the feature exclude test cases that test by copying llvm-*-fuzzer binaries to a directory.
Reviewers: hubert.reinterpretcast, dberris, amyk, jasonliu, EricWF
Reviewed By: hubert.reinterpretcast, amyk
Subscribers: javed.absar, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360672
91177308-0d34-0410-b5e6-
96231b3b80d8