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Mandeep Singh Grang [Tue, 24 Apr 2018 21:25:57 +0000 (21:25 +0000)]
[docs] Add a note on non-deterministic sorting order of equal elements
Reviewers: RKSimon, t.p.northover, dexonsmith
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330773
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Roman Lebedev [Tue, 24 Apr 2018 21:23:22 +0000 (21:23 +0000)]
[X86][AArch64][NFC] Add tests for masked merge unfolding with %y = const
The fold was added in D45733.
This appears to be a regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330771
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Daniel Neilson [Tue, 24 Apr 2018 21:12:45 +0000 (21:12 +0000)]
[CaptureTracking] Fixup const correctness of DomTree arg (NFC)
Summary:
The PointerMayBeCapturedBefore function's DomTree arg should be
const instead of non-const. There are no non-const uses of it
in the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330769
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Sanjay Patel [Tue, 24 Apr 2018 21:06:06 +0000 (21:06 +0000)]
[InstCombine] move tests for select with bit-test of condition; NFC
These are all but 1 of the select-of-constant tests that appear
to be transformed within foldSelectICmpAnd() and the block above
it predicated by decomposeBitTestICmp().
As discussed in D45862 (and can be seen in several tests here),
we probably want to stop doing those transforms because they
can increase the instruction count without benefitting other
passes or codegen.
The 1 test not included here is a urem test where the bit hackery
allows us to remove a urem. To preserve killing that urem, we
should do some stronger known-bits analysis or pattern matching of
'urem x, (select-of-pow2-constants)'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330768
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Tom Stellard [Tue, 24 Apr 2018 20:51:28 +0000 (20:51 +0000)]
AMDGPU/GlobalISel: Add support for amdgpu_ps calling convention
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330767
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Chandler Carruth [Tue, 24 Apr 2018 20:30:56 +0000 (20:30 +0000)]
[wasm] Fix uninitialized memory introduced in r330749.
Found with MSan. This was causing all the WASM MC tests to fail about
10% of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330764
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Rafael Espindola [Tue, 24 Apr 2018 20:15:27 +0000 (20:15 +0000)]
[bugpoint] Fix crash when testing for miscompilation.
Method BugDriver::performFinalCleanups(...) would delete Module object
it worked on, which was also deleted by its caller
(e.g. TestCodeGenerator(...)). Changed the code to avoid double delete
and make Module ownership slightly clearer.
Patch by Andrzej Janik.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330763
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Sam McCall [Tue, 24 Apr 2018 20:08:05 +0000 (20:08 +0000)]
[Support] fix countLeadingZeros for types shorter than int
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330762
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Shoaib Meenai [Tue, 24 Apr 2018 19:47:39 +0000 (19:47 +0000)]
[cmake] Fix libc++ detection
-stdlib=libc++ is added to both the compilation and the link flags, but
the logic for adding it was only checking if it was supported during
compilation and not linking. This could lead to false positives, for
example when using clang with libstdc++ (where the compiler would
support -stdlib=libc++ but then linking would fail because of libc++
actually being unavailable).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330761
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Simon Pilgrim [Tue, 24 Apr 2018 19:22:01 +0000 (19:22 +0000)]
[X86][SKX] Setup WriteFMul and remove unnecessary InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330760
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Vedant Kumar [Tue, 24 Apr 2018 19:20:18 +0000 (19:20 +0000)]
[test] Update llc checks for CodeGen/X86/avg.ll
The output of update_llc_test_checks.py on this test file has changed,
so the test file should be updated to minimize source changes in future
patches.
The test updates for this file appear to be limited to relaxations of
the form:
-; SSE2-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill
+; SSE2-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
This was suggested in https://reviews.llvm.org/D45995.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330758
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Andrea Di Biagio [Tue, 24 Apr 2018 19:14:56 +0000 (19:14 +0000)]
[llvm-mca] Remove unused flag -verbose. NFC
I forgot to remove it at r329794.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330757
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Simon Pilgrim [Tue, 24 Apr 2018 18:49:25 +0000 (18:49 +0000)]
[X86] Split off PHMINPOSUW to their own schedule class
This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330756
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Joel E. Denny [Tue, 24 Apr 2018 18:43:25 +0000 (18:43 +0000)]
[lit] Report line number for failed RUN command
When debugging test failures with -vv (or -v in the case of the
internal shell), this makes it easier to locate the RUN line that
failed. For example, clang's test/Driver/linux-ld.c has 892 total RUN
lines, and clang's test/Driver/arm-cortex-cpus.c has 424 RUN lines
after concatenation for line continuations.
When reading the generated shell script, this also makes it easier to
locate the RUN line that produced each command.
To support reporting RUN line numbers in the case of the internal
shell, this patch extends the internal shell to support the null
command, ":", except pipelines are not supported.
Reviewed By: asmith, delcypher
Differential Revision: https://reviews.llvm.org/D44598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330755
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Stanislav Mekhanoshin [Tue, 24 Apr 2018 18:17:55 +0000 (18:17 +0000)]
[AMDGPU] Truncate packed inline constant
If a packed inline constant is sign extended it must be truncated
after the shift. I.e. a constant (0xH0000, 0xHBC00), will be represented
as 0xFFFFFFFFBC000000 in the IR because the immediate is sign extended
to 64 bit. After the value shifted right by 16 to use it in a low part
with op_sel_hi it becomes 0xFFFFFFFFBC00 and does not qualify as inline
constant any longer.
Fixed the error and added verification code. Without the fix and with
the verification bug is causing pk_max_f16_literal.ll to fail.
Differential Revision: https://reviews.llvm.org/D45987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330752
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Simon Pilgrim [Tue, 24 Apr 2018 18:13:57 +0000 (18:13 +0000)]
[XOP] v4i32 IFMA 'VPMACS' instructions should use the WritePMULLD schedule class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330751
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Sam Clegg [Tue, 24 Apr 2018 18:11:36 +0000 (18:11 +0000)]
[WebAssembly] Use section index in relocation section header
Rather than referring to sections my their code, use the
absolute index of the target section within the module.
See https://github.com/WebAssembly/tool-conventions/issues/52
Differential Revision: https://reviews.llvm.org/D45980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330749
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Florian Hahn [Tue, 24 Apr 2018 18:10:52 +0000 (18:10 +0000)]
[LoopInterchange] Add REQUIRES: asserts to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330748
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Simon Pilgrim [Tue, 24 Apr 2018 17:59:54 +0000 (17:59 +0000)]
[AVX512] VPERMQ/VPERMPD/VPERMIL single op shuffles are not variable shuffles
These variants all take an immediate shuffle mask value and should be scheduled as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330747
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Nico Weber [Tue, 24 Apr 2018 17:29:05 +0000 (17:29 +0000)]
Let TableGen write output only if it changed, instead of doing so in cmake.
Removes one subprocess and one temp file from the build for each tablegen
invocation.
No intended behavior change.
https://reviews.llvm.org/D45899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330742
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Simon Dardis [Tue, 24 Apr 2018 17:11:37 +0000 (17:11 +0000)]
Reland "[mips] Guard traps for microMIPS correctly"
This is part of fixing the instruction predicates for MIPS.
Reviewers: atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D44212
This patch relands r327409, hopefully without the problematic part of the
tests that cause FileCheck to assert on the windows expensive checks bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330741
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Diego Caballero [Tue, 24 Apr 2018 17:04:17 +0000 (17:04 +0000)]
[LV][VPlan] Detect outer loops for explicit vectorization.
Patch #2 from VPlan Outer Loop Vectorization Patch Series #1
(RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html).
This patch introduces the basic infrastructure to detect, legality check
and process outer loops annotated with hints for explicit vectorization.
All these changes are protected under the feature flag
-enable-vplan-native-path. This should make this patch NFC for the existing
inner loop vectorizer.
Reviewers: hfinkel, mkuper, rengolin, fhahn, aemerson, mssimpso.
Differential Revision: https://reviews.llvm.org/D42447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330739
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Florian Hahn [Tue, 24 Apr 2018 16:55:32 +0000 (16:55 +0000)]
[LoopInterchange] Make isProfitableForVectorization slightly more conservative.
After D43236, we started interchanging loops with empty dependence
matrices. In isProfitableForVectorization, we try to determine if
interchanging makes the loop dependences more friendly to the
vectorizer. If there are no dependences, we should not interchange,
based on that heuristic.
Reviewers: efriedma, mcrosier, karthikthecool, blitz.opensource
Reviewed By: mcrosier
Differential Revision: https://reviews.llvm.org/D45208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330738
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Simon Pilgrim [Tue, 24 Apr 2018 16:43:07 +0000 (16:43 +0000)]
[X86][F16C] Add WriteCvtF2FSt scheduling class
Fixes the classification of VCVTPS2PHmr/VCVTPS2PHYmr which were tagged as WriteCvtF2FLd_WriteRMW (PR36887)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330737
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Fangrui Song [Tue, 24 Apr 2018 16:32:55 +0000 (16:32 +0000)]
[ADT] Remove ilist_default_traits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330736
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Simon Pilgrim [Tue, 24 Apr 2018 16:26:51 +0000 (16:26 +0000)]
[X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latencies
These are stores, not loads, so don't need to account for load latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330735
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Simon Pilgrim [Tue, 24 Apr 2018 16:22:59 +0000 (16:22 +0000)]
[X86][IVB] Add F16C resource tests.
Note this is IvyBridge (which shares the model) NOT SandyBridge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330734
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Andrea Di Biagio [Tue, 24 Apr 2018 16:19:08 +0000 (16:19 +0000)]
[llvm-mca] Default the output asm dialect used by the instruction printer to the input asm dialect.
The instruction printer used by llvm-mca to generate the performance report now
defaults the output assembly format to the format used for the input assembly
file.
On x86, the asm format can be either AT&T or Intel, depending on the
presence/absence of directive `.intel_syntax`.
Users can still specify a different assembly dialect with the command line flag
-output-asm-variant=<uint>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330733
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Simon Atanasyan [Tue, 24 Apr 2018 16:14:00 +0000 (16:14 +0000)]
[mips] Show an error if register number is out of range
Current code does not check that a register number is in the 0-31 range.
Sometimes the parser checks that later for some kinds of instructions,
but that leads to unclear / incorrect error messages like that:
% cat test.s
.text
lb $4, 8($32)
% llvm-mc test.s -triple=mips64-unknown-linux
test.s:2:10: error: expected memory with 16-bit signed offset
lb $4, 8($32)
^
Sometimes the parser just crashes:
% cat test.s
.text
lw $4, 8($32)
% llvm-mc test.s -triple=mips64-unknown-linux
This patch resolves the problem by checking that register number after
'$' sign is in the 0-31 range. If the number is out of the range the
parser shows the `invalid register number` error, but treats invalid
register number as a normal one to continue parsing and catch other
possible errors.
Differential Revision: https://reviews.llvm.org/D45919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330732
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Sanjay Patel [Tue, 24 Apr 2018 16:08:03 +0000 (16:08 +0000)]
[InstCombine] regenerate checks; NFC
The first step in fixing problems raised in D45862
is to make the problems visible. Now we can more easily
see/update cases where selects have been turned into
multiple instructions with no apparent improvement in
analysis or benefits for other passes (vectorization).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330731
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Mark Searles [Tue, 24 Apr 2018 15:59:59 +0000 (15:59 +0000)]
[AMDGPU][Waitcnt] NFC. Cleanup some code/naming consistency:
- s/SWaitcnt/Waitcnt s/WaitCnt/Waitcnt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330730
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Sanjay Patel [Tue, 24 Apr 2018 15:42:30 +0000 (15:42 +0000)]
[InstCombine] regenerate checks; NFC
The current version of the script uses regex for params.
This could mask a bug (param values got wrongly swapped),
but it seems unlikely in practice, so let's just update
the whole file to reduce diffs when there is a meaningful
change here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330729
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Dan Liew [Tue, 24 Apr 2018 15:42:00 +0000 (15:42 +0000)]
[lit] Remove spurious `-` in invocation of lit in
`shtest-xunit-output.py` test.
Although there is no `-` file Jeremy Morse has reported to me that it
causes problems in their setup because lit tries to find it and ends up
loading an out of tree lit configuration file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330728
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Nico Weber [Tue, 24 Apr 2018 15:41:02 +0000 (15:41 +0000)]
Remove LLVM_INSTALL_CCTOOLS_SYMLINKS
It used to symlink dsymutil to llvm-dsymutil, but after r327790 llvm's dsymutil
binary is now called dsymutil without prefix.
r327792 then reversed the direction of the symlink if
LLVM_INSTALL_CCTOOLS_SYMLINKS was set, but that looks like a buildfix and not
like something anyone should need.
https://reviews.llvm.org/D45966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330727
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David Blaikie [Tue, 24 Apr 2018 15:40:07 +0000 (15:40 +0000)]
Fix some layering in AggressiveInstCombine (avoiding inclusion of Scalar.h)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330726
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Benjamin Kramer [Tue, 24 Apr 2018 15:28:47 +0000 (15:28 +0000)]
[LoadStoreVectorize] Ignore interleaved invariant loads.
The memory location an invariant load is using can never be clobbered by
any store, so it's safe to move the load ahead of the store.
Differential Revision: https://reviews.llvm.org/D46011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330725
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Andrea Di Biagio [Tue, 24 Apr 2018 14:53:16 +0000 (14:53 +0000)]
[llvm-mca] Refactor the Scheduler interface in preparation for PR36663.
Zero latency instructions are now scheduled the same way as other instructions.
Before this patch, there was a specialzed code path for those instructions.
All scheduler events are now generated from method `scheduleInstruction()` and
from method `cycleEvent()`. This will make easier to implement a "execution
stage", and let that stage publish all the scheduler events.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330723
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Simon Pilgrim [Tue, 24 Apr 2018 14:47:11 +0000 (14:47 +0000)]
[X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330720
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Ulrich Weigand [Tue, 24 Apr 2018 14:03:21 +0000 (14:03 +0000)]
[SystemZ] Use preferred 16-byte function alignment
While not necessary for correctness, it is preferable for
performance reasons on all architectures we currently support
to align functions to 16-byte boundaries by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330718
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Simon Pilgrim [Tue, 24 Apr 2018 13:38:26 +0000 (13:38 +0000)]
Fix Wdocumentation warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330716
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Simon Pilgrim [Tue, 24 Apr 2018 13:24:56 +0000 (13:24 +0000)]
[X86] Fix missing cfi from sitofp checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330715
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Simon Pilgrim [Tue, 24 Apr 2018 13:21:41 +0000 (13:21 +0000)]
[X86] Add vector element insertion/extraction scheduler classes
Split off pinsr/pextr and extractps instructions.
(Mostly) fixes PR36887.
Note: It might be worth adding a WriteFInsertLd class as well in the future.
Differential Revision: https://reviews.llvm.org/D45929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330714
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Simon Pilgrim [Tue, 24 Apr 2018 13:01:03 +0000 (13:01 +0000)]
[MC] Remove orphan MCSchedModel::computeReciprocalThroughput declaration. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330713
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Alexander Ivchenko [Tue, 24 Apr 2018 12:57:51 +0000 (12:57 +0000)]
[X86] Replace action Promote with Expand for operation ISD::SINT_TO_FP
Summary:
If attribute "use-soft-float"="true" is set then X86ISelLowering.cpp sets
'Promote' action for ISD::SINT_TO_FP operation on type i32.
But 'Promote' action is not proper in this case since lib function
__floatsidf is available for casting from signed int to float type.
Thus Expand action is more suitable here.
The Expand action should be set for ISD::UINT_TO_FP for soft float as well.
If function attribute "use-soft-float"="true" is set then infinite looping
can happen in DAG combining, function visitSINT_TO_FP() replaces SINT_TO_FP
node with UINT_TO_FP node and function combineUIntToFP() replace vice versa in cycle.
The fix prevents it.
Patch by vrybalov
Differential Revision: https://reviews.llvm.org/D45572
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330711
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Francis Visoiu Mistrih [Tue, 24 Apr 2018 11:00:46 +0000 (11:00 +0000)]
[CodeGen] Print user-friendly debug locations as MI comments
If available, print the file, line and column of the DebugLoc attached
to the MachineInstr:
MOV16mr $rbp, 1, $noreg, -112, $noreg, killed renamable $ax, debug-location !56 :: (store 2 into %ir.._value12); stepping.swift:10:17
renamable $edx = MOVZX32rm16 $rbp, 1, $noreg, -112, $noreg, debug-location !62 :: (dereferenceable load 2 from %ir.._value13); stepping.swift:10:17
Differential Revision: https://reviews.llvm.org/D45992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330709
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Chandler Carruth [Tue, 24 Apr 2018 10:33:08 +0000 (10:33 +0000)]
[PM/LoopUnswitch] Fix a bug in the loop block set formation of the new
loop unswitch.
This code incorrectly added the header to the loop block set early. As
a consequence we would incorrectly conclude that a nested loop body had
already been visited when the header of the outer loop was the preheader
of the nested loop. In retrospect, adding the header eagerly doesn't
really make sense. It seems nicer to let the cycle be formed naturally.
This will catch crazy bugs in the CFG reconstruction where we can't
correctly form the cycle earlier rather than later, and makes the rest
of the logic just fall out.
I've also added various asserts that make these issues *much* easier to
debug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330707
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Petar Jovanovic [Tue, 24 Apr 2018 10:32:08 +0000 (10:32 +0000)]
Correct dwarf unwind information in function epilogue
This patch aims to provide correct dwarf unwind information in function
epilogue for X86.
It consists of two parts. The first part inserts CFI instructions that set
appropriate cfa offset and cfa register in emitEpilogue() in
X86FrameLowering. This part is X86 specific.
The second part is platform independent and ensures that:
* CFI instructions do not affect code generation (they are not counted as
instructions when tail duplicating or tail merging)
* Unwind information remains correct when a function is modified by
different passes. This is done in a late pass by analyzing information
about cfa offset and cfa register in BBs and inserting additional CFI
directives where necessary.
Added CFIInstrInserter pass:
* analyzes each basic block to determine cfa offset and register are valid
at its entry and exit
* verifies that outgoing cfa offset and register of predecessor blocks match
incoming values of their successors
* inserts additional CFI directives at basic block beginning to correct the
rule for calculating CFA
Having CFI instructions in function epilogue can cause incorrect CFA
calculation rule for some basic blocks. This can happen if, due to basic
block reordering, or the existence of multiple epilogue blocks, some of the
blocks have wrong cfa offset and register values set by the epilogue block
above them.
CFIInstrInserter is currently run only on X86, but can be used by any target
that implements support for adding CFI instructions in epilogue.
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D42848
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330706
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Simon Dardis [Tue, 24 Apr 2018 10:19:29 +0000 (10:19 +0000)]
[mips] Correct the patterns for bswap
Guard the MIPS64 variant correctly for i64, mark the MIPS32 version as not
in microMIPS and provide the microMIPS version.
Additionally, remove a related stale XFAIL'd test as bswap has its own test
case providing coverage.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D45816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330705
91177308-0d34-0410-b5e6-
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Andrea Di Biagio [Tue, 24 Apr 2018 10:09:32 +0000 (10:09 +0000)]
[llvm-mca][CommandGuide] Fix typo in example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330703
91177308-0d34-0410-b5e6-
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Andrei Elovikov [Tue, 24 Apr 2018 09:24:29 +0000 (09:24 +0000)]
[CodeGen] Do not allow opt-bisect-limit to skip ScalarizeMaskedMemIntrin.
Summary:
The pass is supposed to scalarize such intrinsics if the target does not support
them natively, so if the scalarization does not happen instruction selection
crashes due to inability to lower these intrinsics.
Reviewers: andrew.w.kaylor, craig.topper
Reviewed By: andrew.w.kaylor
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330700
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Max Kazantsev [Tue, 24 Apr 2018 09:11:01 +0000 (09:11 +0000)]
[NFC] Remove recently added SE verification because it may be false-positive
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330699
91177308-0d34-0410-b5e6-
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Florian Hahn [Tue, 24 Apr 2018 09:10:05 +0000 (09:10 +0000)]
[LoopInfo] Verify BBMap tracks innermost loops for BBs.
By checking that none of the child loops contain a BB we make sure BBMap
contains the innermost loop defining BB. This invariant was violated in
LoopInterchange and got caught by this assertion.
Reviewers: chandlerc, mzolotukhin, sanjoy, mehdi_amini, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D45971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330698
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Sander de Smalen [Tue, 24 Apr 2018 08:59:08 +0000 (08:59 +0000)]
[AArch64][SVE] Asm: Support for contiguous, first-faulting LDFF1 (scalar+scalar) load instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: rengolin
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330697
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Roman Lebedev [Tue, 24 Apr 2018 08:40:37 +0000 (08:40 +0000)]
Link to AggressiveInstCombine in a few places. Unbreaks build for me.
/usr/local/bin/ld.lld: error: undefined symbol: llvm::createAggressiveInstCombinerPass()
>>> referenced by cc1_main.cpp
>>> tools/clang/tools/driver/CMakeFiles/clang.dir/cc1_main.cpp.o:(_GLOBAL__sub_I_cc1_main.cpp)
And so on
The bot coverage is clearly missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330693
91177308-0d34-0410-b5e6-
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Pavel Labath [Tue, 24 Apr 2018 08:29:20 +0000 (08:29 +0000)]
[Support/Path] Add more tests and improve failure messages of existing ones
Summary:
I am preparing a patch to the path function. While working on it, I
noticed that some of the areas are lacking test coverage (e.g. filename
and parent_path functions), so I add more tests to guard against
regressions there.
I have also found the failure messages hard to understand, so I rewrote
some existing test to give more actionable messages when they fail:
- for tests which run over multiple inputs, I use SCOPED_TRACE, to show
which of the inputs caused the actual failure.
- for comparisons of vectors, I use gmock's container matchers, which
will print out the full container contents (and the elements that
differ) when they fail to match.
Reviewers: zturner, espindola
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45941
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330691
91177308-0d34-0410-b5e6-
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Xin Tong [Tue, 24 Apr 2018 07:38:07 +0000 (07:38 +0000)]
[LVI] Fix typo. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330688
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Alexander Shaposhnikov [Tue, 24 Apr 2018 06:23:22 +0000 (06:23 +0000)]
[llvm-objcopy] Adjust the code for the old versions of msvc
Follow-up for r330685.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330686
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Alexander Shaposhnikov [Tue, 24 Apr 2018 05:43:32 +0000 (05:43 +0000)]
Recommit "[llvm-objcopy] Switch over to using TableGen for parsing arguments"
Add explicit dependency on ObjcopyTableGen
and rerun the tests on Windows.
I will double-check the build bots
and revert this commit if necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330685
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Max Kazantsev [Tue, 24 Apr 2018 04:42:37 +0000 (04:42 +0000)]
[NFC] Use FileCheck in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330684
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Max Kazantsev [Tue, 24 Apr 2018 04:33:04 +0000 (04:33 +0000)]
[NFC] Use forgetTopmostLoop instead of logic duplication
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330683
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Craig Topper [Tue, 24 Apr 2018 04:28:02 +0000 (04:28 +0000)]
[X86] Add a BSWAP16 instruction using the 32-bit encoding plus a 0x66 prefix.
This encoding is recognized by the CPU, but the behavior is undefined. This makes the disassembler handle it correctly so we don't print bswapl with a 16-bit register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330682
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Chandler Carruth [Tue, 24 Apr 2018 03:27:00 +0000 (03:27 +0000)]
[PM/LoopUnswitch] Remove another over-aggressive assert.
This code path can very clearly be called in a context where we have
baselined all the cloned blocks to a particular loop and are trying to
handle nested subloops. There is no harm in this, so just relax the
assert. I've added a test case that will make sure we actually exercise
this code path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330680
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Eric Christopher [Tue, 24 Apr 2018 02:10:59 +0000 (02:10 +0000)]
Remove unused function HexagonEarlyIfConversion::replacePhiEdges. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330678
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Max Kazantsev [Tue, 24 Apr 2018 02:08:05 +0000 (02:08 +0000)]
[NFC] Add clarification comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330677
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Eric Christopher [Tue, 24 Apr 2018 01:57:03 +0000 (01:57 +0000)]
Reflow formatting after previous NFC commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330676
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Eric Christopher [Tue, 24 Apr 2018 01:57:02 +0000 (01:57 +0000)]
Change if-conditionals to else-if as they should all be mutually exclusive.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330675
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Nico Weber [Tue, 24 Apr 2018 01:24:42 +0000 (01:24 +0000)]
Mostly revert r330672.
The test is apparently needed e.g. for check-cfi on Windows where we get
'C:/b/slave/sanitizer-windows/build/./bin/clang.exe': command not found
without it. Try to fix the problem that was fixed by r330672 by also checking
for isabs() instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330673
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Nico Weber [Tue, 24 Apr 2018 01:05:04 +0000 (01:05 +0000)]
Remove code that's almost always dead, and harmful if not.
lit's util.which() would check if the passed-in path existed directly,
and if so return it as-is. This is never the case when running llvm's, clang's,
or lld's tests normally. But when running `./llvm-lit path/to/clang/test`
with a cwd of llvm-build/bin, this if would detect that clang exists at path
'clang' and return 'clang' as the discovered clang binary -- and then lit would
use the " clang " -> "*** Do not use 'clang' in tests, use '%clang'. ***"
substitution to replace that with a broken test. By removing this early
return, lit ends up with the usual absolute path and everything works even
in this uncommon case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330672
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David Blaikie [Tue, 24 Apr 2018 00:58:57 +0000 (00:58 +0000)]
Fix build breaks in examples due to moving stuff from Scalar.h to InstCombine.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330670
91177308-0d34-0410-b5e6-
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David Blaikie [Tue, 24 Apr 2018 00:48:59 +0000 (00:48 +0000)]
InstCombine: Fix layering by not including Scalar.h in InstCombine
(notionally Scalar.h is part of libLLVMScalarOpts, so it shouldn't be
included by InstCombine which doesn't/shouldn't need to depend on
ScalarOpts)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330669
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Craig Topper [Tue, 24 Apr 2018 00:39:29 +0000 (00:39 +0000)]
[AggressiveInstCombine] Add aggressive inst combiner to the LLVM C API.
I just tried to copy what was done for regular InstCombine. Hopefully I didn't miss anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330668
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George Burgess IV [Tue, 24 Apr 2018 00:25:01 +0000 (00:25 +0000)]
Reland r301880(!): "[InstSimplify] Handle selects of GEPs with 0 offset"
I was reminded today that this patch got reverted in r301885. I can no
longer reproduce the failure that caused the revert locally (...almost
one year later), and the patch applied pretty cleanly, so I guess we'll
see if the bots still get angry about it.
The original breakage was InstSimplify complaining (in "assertion
failed" form) about getting passed some crazy IR when running `ninja
check-sanitizer`. I'm unable to find traces of what, exactly, said crazy
IR was. I suppose we'll find out pretty soon if that's still the case.
:)
Original commit:
Author: gbiv
Date: Mon May 1 18:12:08 2017
New Revision: 301880
URL: http://llvm.org/viewvc/llvm-project?rev=301880&view=rev
Log:
[InstSimplify] Handle selects of GEPs with 0 offset
In particular (since it wouldn't fit nicely in the summary):
(select (icmp eq V 0) P (getelementptr P V)) -> (getelementptr P V)
Differential Revision: https://reviews.llvm.org/D31435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330667
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Alex Shlyapnikov [Tue, 24 Apr 2018 00:16:54 +0000 (00:16 +0000)]
[HWASan] Use dynamic shadow memory on Android only (LLVM)
There're issues with IFUNC support on other platforms.
DIfferential Revision: https://reviews.llvm.org/D45840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330665
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Craig Topper [Tue, 24 Apr 2018 00:11:04 +0000 (00:11 +0000)]
[AggressiveInstCombine] Add createAggressiveInstCombinerPass to LinkAllPasses.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330664
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Craig Topper [Tue, 24 Apr 2018 00:05:21 +0000 (00:05 +0000)]
[AggressiveInstCombine] Add library initializer routine for AggressiveInstCombine library. Use it in bugpoint and llvm-opt-fuzzer to match regular InstCombine.
This should make aggressive instcombine usable with these tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330663
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Simon Pilgrim [Mon, 23 Apr 2018 22:45:04 +0000 (22:45 +0000)]
[X86] Remove unnecessary vector memory folded InstRW overrides.
We have test coverage for these with resources-sse*/avx*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330662
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Robert Widmann [Mon, 23 Apr 2018 22:31:49 +0000 (22:31 +0000)]
[LLVM-C] DIBuilder Bindings For Variable Expressions
Summary: Add DIBuilder bindings for (global) variable expressions, variable value expressions, and debug value intrinsic insertion.
Reviewers: harlanhaskins, deadalnix, whitequark
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45979
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330661
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Roman Tereshin [Mon, 23 Apr 2018 22:28:36 +0000 (22:28 +0000)]
[GlobalISel][Legalizer] Look thro copies while combining G_UNMERGE's
As we're becoming stricter w/ respect to not allowing vregs having LLTs
and regclasses assigned both mid-globalisel pipeline, the number of
extra copies grows, some of which separate G_UNMERGE's from their
corresponding G_MERGE's, becoming a performance concern.
It's worth mentioning that we're already looking through copies while
combining legalization artifacts for every kind of artifact but
G_UNMERGE.
Reviewed By: aditya_nandakumar
Reviewers: ab, t.p.northover, volkan, javed.absar
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330660
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Simon Pilgrim [Mon, 23 Apr 2018 22:19:55 +0000 (22:19 +0000)]
[X86] Remove unnecessary BMI2 InstRW overrides.
We have test coverage for these with resources-bmi2.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330659
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Florian Hahn [Mon, 23 Apr 2018 21:38:19 +0000 (21:38 +0000)]
[LoopInterchange] Do not change LI for BBs in child loops.
If a loop with child loops becomes our new inner loop after
interchanging, we only need to update LoopInfo for the blocks defined in
the old outer loop. BBs in child loops will stay there.
Reviewers: efriedma, karthikthecool, mcrosier
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D45970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330653
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Mon, 23 Apr 2018 21:04:23 +0000 (21:04 +0000)]
[X86] Remove unnecessary WriteLEA InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330648
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Roman Lebedev [Mon, 23 Apr 2018 20:38:49 +0000 (20:38 +0000)]
[DAGCombiner] Unfold scalar masked merge if profitable
Summary:
This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]].
[[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly.
Previously, `andl`+`andn`/`andps`+`andnps` / `bic`/`bsl` would be generated. (see `@out`)
Now, they would no longer be generated (see `@in`).
So we need to make sure that they are still generated.
If the mask is constant, we do nothing. InstCombine should have unfolded it.
Else, i use `hasAndNot()` TLI hook.
For now, only handle scalars.
https://rise4fun.com/Alive/bO6
----
I *really* don't like the code i wrote in `DAGCombiner::unfoldMaskedMerge()`.
It is super fragile. Is there something like IR Pattern Matchers for this?
Reviewers: spatel, craig.topper, RKSimon, javed.absar
Reviewed By: spatel
Subscribers: andreadb, courbet, kristof.beyls, javed.absar, rengolin, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D45733
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330646
91177308-0d34-0410-b5e6-
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Roman Lebedev [Mon, 23 Apr 2018 20:38:42 +0000 (20:38 +0000)]
[X86][AArch64][NFC] Add tests for masked merge unfolding
Summary:
This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]].
[[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly.
Previously, `andl`+`andn`/`andps`+`andnps` / `bic`/`bsl` would be generated. (see `@out`)
Now, they would no longer be generated (see `@in`).
I'm guessing `llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp` should be able to unfold this.
Reviewers: spatel, craig.topper, RKSimon, javed.absar
Reviewed By: spatel
Subscribers: nemanjai, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330645
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Sanjay Patel [Mon, 23 Apr 2018 20:20:32 +0000 (20:20 +0000)]
[AggressiveInstCombine] add tests for PR37098; NFC
I'm not sure if this is where we should try to fold these
patterns inspired by:
https://bugs.llvm.org/show_bug.cgi?id=37098
...if this isn't the right place, we can move the tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330642
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Xin Tong [Mon, 23 Apr 2018 20:09:08 +0000 (20:09 +0000)]
[CallSiteSplit] Make sure we remove nonnull if the parameter turns out to be a constant.
Summary: We do not need nonull attribute if we know an argument is going to be constant.
Reviewers: junbuml, davide, fhahn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330641
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Gabor Buella [Mon, 23 Apr 2018 20:05:51 +0000 (20:05 +0000)]
[X86] Revert r330638 - accidental commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330640
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George Burgess IV [Mon, 23 Apr 2018 20:03:00 +0000 (20:03 +0000)]
Fix a broken typedef; NFCI
Richard Smith noted that `typedef typename iplist::iplist_impl_type
iplist_impl_type` is incorrect, per
http://eel.is/c++draft/basic.scope#class-2
It seems that neither clang nor gcc get too angry about this, but a
newer version of msvc does.
Thanks to jcmac on IRC for pointing this out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330639
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Gabor Buella [Mon, 23 Apr 2018 20:00:59 +0000 (20:00 +0000)]
[X86] movdiri and movdir64b instructions
Reviewers: craig.topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330638
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Bjorn Pettersson [Mon, 23 Apr 2018 19:55:04 +0000 (19:55 +0000)]
[MemCpyOpt] Skip optimizing basic blocks not reachable from entry
Summary:
Skip basic blocks not reachable from the entry node
in MemCpyOptPass::iterateOnFunction.
Code that is unreachable may have properties that do not exist
for reachable code (an instruction in a basic block can for
example be dominated by a later instruction in the same basic
block, for example if there is a single block loop).
MemCpyOptPass::processStore is only safe to use for reachable
basic blocks, since it may iterate past the basic block
beginning when used for unreachable blocks. By simply skipping
to optimize unreachable basic blocks we can avoid asserts such
as "Assertion `!NodePtr->isKnownSentinel()' failed."
in MemCpyOptPass::processStore.
The problem was detected by fuzz tests.
Reviewers: eli.friedman, dneilson, efriedma
Reviewed By: efriedma
Subscribers: efriedma, llvm-commits
Differential Revision: https://reviews.llvm.org/D45889
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330635
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Sam Clegg [Mon, 23 Apr 2018 19:16:19 +0000 (19:16 +0000)]
[WebAssembly] MC: Refactor section creation code
Remove the use of default argument in favor of a separate
startCustomSection method.
Differential Revision: https://reviews.llvm.org/D45794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330632
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Quentin Colombet [Mon, 23 Apr 2018 19:09:49 +0000 (19:09 +0000)]
[CODE_OWNERS] Update my email address.
NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330631
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Peter Collingbourne [Mon, 23 Apr 2018 19:09:34 +0000 (19:09 +0000)]
Reland r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses.", with a fix for the bot failure.
This reland includes a check to prevent the DAG combiner from folding an
offset that is smaller than the existing one. This can cause oscillations
between two possible DAGs, which was the cause of the hang and later assertion
failure observed on the lnt-ctmark-aarch64-O3-flto bot.
http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/
Original commit message:
> This is a code size win in code that takes offseted addresses
> frequently, such as C++ constructors that typically need to compute
> an offseted address of a vtable. This reduces the size of Chromium
> for Android's .text section by 108KB.
Differential Revision: https://reviews.llvm.org/D45199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330630
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Daniel Neilson [Mon, 23 Apr 2018 19:06:49 +0000 (19:06 +0000)]
[DSE] Teach the pass that atomic memory intrinsics are stores.
Summary:
This change teaches DSE that the atomic memory intrinsics are stores
that can be eliminated, and can allow other stores to be eliminated.
This change specifically does not teach DSE that these intrinsics
can be partially eliminated (i.e. length reduced, and dest/src changed);
that will be handled in another change.
Reviewers: mkazantsev, skatkov, apilipenko, efriedma, rsmith
Reviewed By: efriedma
Subscribers: dmgreen, llvm-commits
Differential Revision: https://reviews.llvm.org/D45535
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330629
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Matthew Simpson [Mon, 23 Apr 2018 18:21:29 +0000 (18:21 +0000)]
[AArch64] Add cost model test case for transpose
This patch adds a cost model test case for vector shuffles having transpose
masks. The given costs are inaccurate and will be updated in a follow-on patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330625
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Alex Shlyapnikov [Mon, 23 Apr 2018 18:14:39 +0000 (18:14 +0000)]
[HWASan] Switch back to fixed shadow mapping for x86-64
For now switch back to fixed shadow mapping for x86-64 due to the issues
with IFUNC linking on older binutils. More details will be added to
https://bugs.chromium.org/p/chromium/issues/detail?id=835864
Differential Revision: https://reviews.llvm.org/D45840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330623
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Craig Topper [Mon, 23 Apr 2018 17:47:33 +0000 (17:47 +0000)]
[X86] Add disassembler test cases for bswap.
This demonstrates a bug where the encoding for a 16-bit bswap prints a 16-bit register and a 32-bit mnemonic. Intel docs say 16-bit bswap is undefined. We should either claim it as an invalid encoding or we should print a 16-bit mnemonic.
objdump does print the encoding as bswap with a 16-bit register. But it doesn't seem to ever print a suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330621
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Vedant Kumar [Mon, 23 Apr 2018 17:18:24 +0000 (17:18 +0000)]
[SelectionDAG] Dump debug locs in SDNodes
This helps debug issues where selection-dag assigns the wrong location
to an instruction.
Differential Revision: https://reviews.llvm.org/D45913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330618
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Simon Pilgrim [Mon, 23 Apr 2018 16:59:06 +0000 (16:59 +0000)]
[MC] Remove MachineInstr reference in MC layer (PR37160)
Only add support for getSchedInfoStr(const MachineInstr &MI) at the TargetSubtargetInfo level.
Really, the getSchedInfoStr calls need to be removed entirely, we should just return a latency/rthroughput through the subtarget and keep a string creation helper function somewhere else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330615
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Reid Kleckner [Mon, 23 Apr 2018 16:47:27 +0000 (16:47 +0000)]
Fix -Wtautological-compare warning with npos on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330614
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Matt Arsenault [Mon, 23 Apr 2018 16:13:30 +0000 (16:13 +0000)]
AMDGPU: Move a flawed assert when spilling SGPRs
It's possible to validly spill the frame offset register
in a call sequence to a VGPR. There are definitely issues
with SGPR spilling to memory, so move the assert later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330612
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