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Yoshihiro Shimoda [Tue, 8 Nov 2022 00:55:00 +0000 (09:55 +0900)]
phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8
Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0).
The datasheet describes initialization procedure without any information
about registers' name/bits. So, this is all black magic to initialize
the hardware. Especially, all channels should be initialized at once.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221108005500.3011449-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Yoshihiro Shimoda [Tue, 8 Nov 2022 00:54:59 +0000 (09:54 +0900)]
dt-bindings: phy: renesas: Document Renesas Ethernet SERDES
Document Renesas Etherent SERDES for R-Car S4-8 (r8a779f0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221108005500.3011449-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Manivannan Sadhasivam [Wed, 2 Nov 2022 08:18:35 +0000 (13:48 +0530)]
phy: qcom-qmp-pcie: Fix sm8450_qmp_gen4x2_pcie_pcs_tbl[] register names
sm8450_qmp_gen4x2_pcie_pcs_tbl[] contains the init sequence for PCS
registers of QMP PHY v5.20. So use the v5.20 specific register names.
Only major change is the rename of PCS_EQ_CONFIG{2/3} registers to
PCS_EQ_CONFIG{4/5}.
Fixes:
2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20221102081835.41892-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Manivannan Sadhasivam [Wed, 2 Nov 2022 08:18:34 +0000 (13:48 +0530)]
phy: qcom-qmp-pcie: Fix high latency with 4x2 PHY when ASPM is enabled
The PCIe QMP 4x2 RC PHY generates high latency when ASPM is enabled. This
seem to be fixed by clearing the QPHY_V5_20_PCS_PCIE_PRESET_P10_POST
register of the pcs_misc register space.
Fixes:
2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20221102081835.41892-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Christian Marangi [Thu, 3 Nov 2022 21:21:24 +0000 (22:21 +0100)]
phy: qcom-qmp-pcie: split pcs_misc init cfg for ipq8074 pcs table
Commit
af6643242d3a ("phy: qcom-qmp-pcie: split pcs_misc region for ipq6018
pcie gen3") reworked the pcs regs values and removed the 0x400 offset
for each pcs_misc regs.
This change caused the malfunction of ipq8074 downstream since it still
has the legacy pcs table where pcs_misc are not placed on a different
table and instead put together assuming the offset of 0x400 for the
related pcs_misc regs.
Split pcs_misc init cfg from the ipq8074 pcs init table to be handled
correctly to prepare for actual support for gen3 pcie for ipq8074.
Fixes:
af6643242d3a ("phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3")
Reported-by: Robert Marko <robimarko@gmail.com>
Tested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20221103212125.17156-1-ansuelsmth@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:39 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: add support for sc8280xp 4-lane PHYs
The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in
4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as
PCIe2A and PCIe2B).
Add support for fetching the 4-lane configuration from the TCSR and
programming the lane registers of the second port when in 4-lane mode.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-17-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:38 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: add support for sc8280xp
Add support for the single and dual-lane PHYs found on SC8280XP.
Note that the SC8280XP binding does not try to describe every register
subregion and instead the driver holds the corresponding offsets.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-16-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:37 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: add support for pipediv2 clock
Some QMP PHYs have a second fixed-divider pipe clock that needs to be
enabled along with the pipe clock.
Add support for an optional "pipediv2" clock.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-15-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:36 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: fix initialisation reset
Add the missing delay after asserting reset. This is specifically needed
for the reset to have any effect on SC8280XP.
The vendor driver uses a 1 ms delay, but that seems a bit excessive.
Instead use a 200 us delay which appears to be more than enough and also
matches the UFS reset delay added by commit
870b1279c7a0 ("scsi:
ufs-qcom: Add reset control support for host controller").
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-14-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:35 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: restructure PHY creation
In preparation for supporting devicetree bindings which do not use a
child node, move the PHY creation to probe() proper and parse the serdes
resource in what is now the legacy devicetree helper.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-13-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:34 +0000 (15:59 +0100)]
dt-bindings: phy: qcom,qmp-pcie: add sc8280xp bindings
Add bindings for the PCIe QMP PHYs found on SC8280XP.
The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in
4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as
PCIe2A and PCIe2B).
The configuration for a specific system can be read from a TCSR register.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-12-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:33 +0000 (15:59 +0100)]
dt-bindings: phy: qcom,qmp-pcie: rename current bindings
The current QMP PCIe PHY bindings are based on the original MSM8996
binding which provided multiple PHYs per IP block and these in turn were
described by child nodes.
Later QMP PCIe PHY blocks only provide a single PHY and the remnant
child node does not really reflect the hardware.
The original MSM8996 binding also ended up describing the individual
register blocks as belonging to either the wrapper node or the PHY child
nodes.
This is an unnecessary level of detail which has lead to problems when
later IP blocks using different register layouts have been forced to fit
the original mould rather than updating the binding. The bindings are
arguable also incomplete as they only the describe register blocks used
by the current Linux drivers (e.g. does not include the per lane PCS
registers).
In preparation for adding new bindings for SC8280XP which further
bindings can be based on, rename the current schema file after IPQ8074,
which was the first SoC added to the bindings after MSM8996 (which has
already been split out), and add a reference to the SC8280XP bindings.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-11-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:32 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: add register init helper
Generalise the serdes initialisation helper so that it can be used to
initialise all the PHY registers (e.g. serdes, tx, rx, pcs).
Note that this defers the ungating of the PIPE clock somewhat, which is
fine as it isn't needed until starting the PHY.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-10-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:31 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: use shorter tables identifiers
The QMP drivers all use 'tbl' to refer to their register initialisation
tables.
For consistency use 'tbls' rather than 'tables' to refer to the new
aggregate table structures.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221105145939.20318-9-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:30 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: clean up PHY lane init
Clean up the PHY lane initialisation somewhat by adding further
temporary variables and programming both tx and rx for the second lane
after the first lane.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-8-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:29 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: rename PHY ops structure
Rename the PHY operation structure so that it has a "phy_ops" suffix and
move it next to the implementation.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-7-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:28 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: clean up probe initialisation
Stop abusing the driver data pointer and instead pass the driver state
structure directly to the initialisation helpers during probe.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-6-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:27 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: clean up device-tree parsing
Since the QMP driver split there will be at most a single child node so
drop the obsolete iteration construct.
While at it, drop the verbose error logging that would have been
printed also on probe deferrals.
Note that there's no need to check if there are additional child nodes
(the kernel is not a devicetree validator), but let's return an error if
there are no child nodes at all for now.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-5-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:26 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: merge driver data
The PCIe QMP PHY driver only manages a single PHY so merge the old
qcom_qmp and qmp_phy structures and drop the PHY array.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-4-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:25 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: move device-id table
Move the device-id table below probe() and next to the driver structure
to keep the driver callback functions grouped together.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-3-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Sat, 5 Nov 2022 14:59:24 +0000 (15:59 +0100)]
phy: qcom-qmp-pcie: sort device-id table
Sort the device-id table by compatible string to make it easier to find
and add new entries.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-2-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Sean Anderson [Tue, 18 Oct 2022 17:58:41 +0000 (13:58 -0400)]
doc: phy: Document typical order of API calls
Document the typical order of API calls to used by new drivers and
controllers. Many existing controllers follow this order, but some do
not. This is especially true for controllers designed to work with one
particular PHY driver, which may not need a call to (for example)
phy_init.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Link: https://lore.kernel.org/r/20221018175841.1906611-1-sean.anderson@seco.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Wayne Chang [Wed, 5 Oct 2022 08:40:31 +0000 (16:40 +0800)]
phy: tegra: xusb: Remove usb3 supply
Remove redundant codes for getting the vbus supply of usb3 ports because
we get and control the vbus supply by the companion usb2 ports
Signed-off-by: Wayne Chang <waynec@nvidia.com>
Signed-off-by: Haotien Hsu <haotienh@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20221005084031.2154251-1-haotienh@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Florian Fainelli [Wed, 26 Oct 2022 22:44:49 +0000 (15:44 -0700)]
phy: phy-brcm-usb: Utilize platform_get_irq_byname_optional()
The wake-up interrupt lines are entirely optional, avoid printing
messages that interrupts were not found by switching to the _optional
variant.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Justin Chen <justinpopo6@gmail.com>
Link: https://lore.kernel.org/r/20221026224450.2958762-1-f.fainelli@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Siddharth Vadapalli [Wed, 26 Oct 2022 07:45:32 +0000 (13:15 +0530)]
phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J721e
Each of the CPSW9G ports in J721e support additional modes like QSGMII.
Add a new compatible for J721e to support the additional modes.
In TI's J721e, each of the CPSW9G ethernet interfaces can act as a
QSGMII main or QSGMII-SUB port. The QSGMII main interface is responsible
for performing auto-negotiation between the MAC and the PHY while the rest
of the interfaces are designated as QSGMII-SUB interfaces, indicating that
they will not be taking part in the auto-negotiation process.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20221026074532.109220-4-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Siddharth Vadapalli [Wed, 26 Oct 2022 07:45:31 +0000 (13:15 +0530)]
phy: ti: gmii-sel: Update methods for fetching and using qsgmii main port
The number of QSGMII main ports are specific to the device. TI's J7200 for
which the QSGMII main port property is fetched from the device-tree has
only one QSGMII main port. However, devices like TI's J721e support up to
two QSGMII main ports. Thus, the existing methods for fetching and using
the QSGMII main port are not scalable.
Update the existing methods for handling the QSGMII main ports and its
associated requirements to make it scalable for future devices.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20221026074532.109220-3-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Siddharth Vadapalli [Wed, 26 Oct 2022 07:45:30 +0000 (13:15 +0530)]
dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e
TI's J721e SoC supports additional PHY modes like QSGMII and SGMII
that are not supported on earlier SoCs. Add a compatible for it.
Extend ti,qsgmii-main-ports property to support selection of upto
two main ports at once across the two QSGMII interfaces.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221026074532.109220-2-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Andre Przywara [Mon, 31 Oct 2022 11:13:55 +0000 (11:13 +0000)]
phy: sun4i-usb: Add support for the H616 USB PHY
The USB PHY used in the Allwinner H616 SoC inherits some traits from its
various predecessors: it has four full PHYs like the H3, needs some
extra bits to be set like the H6, and puts SIDDQ on a different bit like
the A100. Plus it needs this weird PHY2 quirk.
Name all those properties in a new config struct and assign a new
compatible name to it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221031111358.3387297-5-andre.przywara@arm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Andre Przywara [Mon, 31 Oct 2022 11:13:54 +0000 (11:13 +0000)]
phy: sun4i-usb: Introduce port2 SIDDQ quirk
At least the Allwinner H616 SoC requires a weird quirk to make most
USB PHYs work: Only port2 works out of the box, but all other ports
need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
the PMU PHY control register needs to be cleared. For this register to
be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....
Instead of disguising this as some generic feature, treat it more like
a quirk (what it really is):
If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
this one special clock, and clear the SIDDQ bit. We also pick the clock
and reset from PHY2 and enable them as well.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20221031111358.3387297-4-andre.przywara@arm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Andre Przywara [Mon, 31 Oct 2022 11:13:53 +0000 (11:13 +0000)]
dt-bindings: phy: Add special clock for Allwinner H616 PHY
The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
some resources from port 2's PHY and HCI IP. In particular the PMU clock
for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
register of port 2. To allow each USB port to be controlled
independently of port 2, we need a handle to that particular PMU clock
in the *PHY* node, as the HCI and PHY part might be handled by separate
drivers.
Add that clock to the requirements of the H616 PHY binding, so that a
PHY driver can apply the quirk in isolation, without requiring help from
port 2's HCI driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221031111358.3387297-3-andre.przywara@arm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Justin Chen [Wed, 5 Oct 2022 21:30:18 +0000 (14:30 -0700)]
phy: usb: Fix clock imbalance for suspend/resume
We should be disabling clocks when wake from USB is not needed. Since
this wasn't done, we had a clock imbalance since clocks were always
being enabled on resume.
Fixes:
ae532b2b7aa5 ("phy: usb: Add "wake on" functionality for newer Synopsis XHCI controllers")
Fixes:
b0c0b66c0b43 ("phy: usb: Add support for wake and USB low power mode for 7211 S2/S5")
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/1665005418-15807-7-git-send-email-justinpopo6@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Justin Chen [Wed, 5 Oct 2022 21:30:17 +0000 (14:30 -0700)]
phy: usb: Use slow clock for wake enabled suspend
The logic was incorrect when switching to slow clock. We want the slow
clock if wake_enabled is set.
Fixes:
ae532b2b7aa5 ("phy: usb: Add "wake on" functionality for newer Synopsis XHCI controllers")
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/1665005418-15807-6-git-send-email-justinpopo6@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Justin Chen [Wed, 5 Oct 2022 21:30:16 +0000 (14:30 -0700)]
phy: usb: Disable phy auto-suspend
The BDC block requires the PLL lock in order to grab the PLL clock.
The phy auto-suspend feature turns off the phy when nothing is attached
leading to the PLL to not lock. This leads the BDC block to grab the AUX
clock instead of the PLL clock. This is not ideal, so lets turn this
feature off.
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/1665005418-15807-5-git-send-email-justinpopo6@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Justin Chen [Wed, 5 Oct 2022 21:30:15 +0000 (14:30 -0700)]
phy: usb: Migrate to BIT and BITMASK macros
Using BIT and BITMASK macros makes it much easier to read and make
modifications. Also reordered some constants to be in numerical order.
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/1665005418-15807-4-git-send-email-justinpopo6@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Al Cooper [Wed, 5 Oct 2022 21:30:14 +0000 (14:30 -0700)]
phy: usb: s2 WoL wakeup_count not incremented for USB->Eth devices
The PHY's "wakeup_count" is not incrementing when waking from
WoL. The wakeup count can be found in sysfs at:
/sys/bus/platform/devices/rdb/*.usb-phy/power/wakeup_count.
The problem is that the system wakup event handler was being passed
the wrong "device" by the PHY driver.
Fixes:
f1c0db40a3ad ("phy: usb: Add "wake on" functionality")
Signed-off-by: Al Cooper <alcooperx@gmail.com>
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/1665005418-15807-3-git-send-email-justinpopo6@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Justin Chen [Wed, 5 Oct 2022 21:30:13 +0000 (14:30 -0700)]
phy: usb: Improve port mode selection
Split port modes into two different variables. Supported port modes
is what the hardware supports. While port mode is how the hardware
is currently configured and can be dynamically changed through the
sysfs. We initialize all supported port modes on init even though
the port mode may not be selected because we cannot guarantee the
downstream interface from the phy will be active or not.
This also fixes an issue where port modes selected via sysfs were
not being saved through suspend/resume.
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/1665005418-15807-2-git-send-email-justinpopo6@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:35 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: add support for updated sc8280xp binding
Add support for the new SC8280XP binding.
Note that the binding does not try to describe every register subregion
and instead the driver holds the corresponding offsets. This includes
the PCS_USB region which was initially overlooked.
Note that the driver will no longer accept the old binding due to the
fixed "phy_phy" reset name.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-14-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:34 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: restructure PHY creation
In preparation for supporting devicetree bindings which do not use a
child node, move the PHY creation to probe() proper and parse the serdes
and dp_com resources in what is now the legacy devicetree helper.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-13-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:33 +0000 (18:04 +0200)]
dt-bindings: phy: qcom,qmp-usb: fix sc8280xp binding
The current QMP USB PHY bindings are based on the original MSM8996 PCIe
PHY binding which provided multiple PHYs per IP block and these in turn
were described by child nodes.
The QMP USB PHY block only provide a single PHY and the remnant child
node does not really reflect the hardware.
The original MSM8996 binding also ended up describing the individual
register blocks as belonging to either the wrapper node or the PHY child
nodes.
This is an unnecessary level of detail which has lead to problems when
later IP blocks using different register layouts have been forced to fit
the original mould rather than updating the binding. The bindings are
arguable also incomplete as they only the describe register blocks used
by the current Linux drivers (e.g. does not include the per lane PCS
registers).
Note that PCS_USB region is also not described by the current bindings
despite being used by the driver and this has led to people increasing
the size of the PCS region in the devicetree so that it includes PCS_USB
registers even though other regions like TX and RX may lie in between.
Add a new binding for the QMP USB PHYs found on SC8280XP which further
bindings can be based on.
Note that this also fixes the SC8280XP "phy_phy" reset name.
Also note that the current binding is simply removed instead of being
deprecated as it was only recently merged and support for SC8280XP is
still under development. And, specifically, there is no support in
mainline for the multiport controller that uses these PHYs.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-12-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:32 +0000 (18:04 +0200)]
dt-bindings: phy: qcom,qmp-usb: rename current bindings
The current QMP USB PHY bindings are based on the original MSM8996
binding which provided multiple PHYs per IP block and these in turn were
described by child nodes.
Later QMP USB PHY blocks only provide a single PHY and the remnant child
node does not really reflect the hardware.
The original MSM8996 binding also ended up describing the individual
register blocks as belonging to either the wrapper node or the PHY child
nodes.
This is an unnecessary level of detail which has lead to problems when
later IP blocks using different register layouts have been forced to fit
the original mould rather than updating the binding. The bindings are
arguable also incomplete as they only the describe register blocks used
by the current Linux drivers (e.g. does not include the per lane PCS
registers).
In preparation for adding new bindings for SC8280XP which further
bindings can be based on, rename the current bindings after MSM8996 and
add a reference to the SC8280XP bindings.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-11-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:31 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: clean up PHY init
Clean up the PHY initialisation somewhat by programming both tx and rx
for the second lane after the first lane.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-10-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:30 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: rename PHY ops structure
Rename the PHY operation structure so that it has a "phy_ops" suffix and
move it next to the implementation.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-9-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:29 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: clean up probe initialisation
Stop abusing the driver data pointer and instead pass the driver state
structure directly to the initialisation helpers during probe.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-8-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:28 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: clean up device-tree parsing
Since the QMP driver split there will be at most a single child node so
drop the obsolete iteration construct.
While at it, drop the verbose error logging that would have been
printed also on probe deferrals.
Note that there's no need to check if there are additional child nodes
(the kernel is not a devicetree validator), but let's return an error if
there are no child nodes at all for now.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-7-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:27 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: merge driver data
The USB QMP PHY driver only manages a single PHY so merge the old
qcom_qmp and qmp_phy structures and drop the PHY array.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-6-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:26 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: move pm ops
Move the PM ops structure next to the implementation to keep the driver
callbacks grouped.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-5-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:25 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: move device-id table
Move the device-id table below probe() and next to the driver structure
to keep the driver callback functions grouped together.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-4-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:24 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: sort device-id table
Sort the device-id table by compatible string to make it easier to find
and add new entries.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-3-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Fri, 28 Oct 2022 16:04:23 +0000 (18:04 +0200)]
phy: qcom-qmp-usb: fix sc8280xp PCS_USB offset
The PCS_USB register block lives at an offset of 0x1000 from the PCS
region on SC8280XP so add the missing offset to avoid corrupting
unrelated registers on runtime suspend.
Note that the current binding is broken as it does not describe the
PCS_USB region and the PCS register size does not cover PCS_USB and the
regions in between. As Linux currently maps full pages, simply adding
the offset to driver works until the binding has been fixed.
Fixes:
c0c7769cdae2 ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221028160435.26948-2-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Vinod Koul [Fri, 28 Oct 2022 13:09:28 +0000 (18:39 +0530)]
Merge branch 'fixes' into next
Merge the fixes to next as both carry qmp-phy patches
Johan Hovold [Mon, 24 Oct 2022 09:00:41 +0000 (11:00 +0200)]
phy: qcom-qmp-ufs: add support for updated sc8280xp binding
Add support for the new SC8280XP binding.
Note that the binding does not try to describe every register subregion
and instead the driver holds the corresponding offsets.
Also note that the driver will continue to accept the old binding, at
least for the time being.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221024090041.19574-11-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 24 Oct 2022 09:00:40 +0000 (11:00 +0200)]
phy: qcom-qmp-ufs: restructure PHY creation
In preparation for supporting devicetree bindings which do not use a
child node, move the PHY creation to probe() proper and parse the serdes
resource in what is now the legacy devicetree helper.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221024090041.19574-10-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 24 Oct 2022 09:00:39 +0000 (11:00 +0200)]
dt-bindings: phy: qcom,qmp-ufs: fix sc8280xp binding
The current QMP UFS PHY bindings are based on the original MSM8996 PCIe
PHY binding which provided multiple PHYs per IP block and these in turn
were described by child nodes.
The QMP UFS PHY block only provide a single PHY and the remnant child
node does not really reflect the hardware.
The original MSM8996 binding also ended up describing the individual
register blocks as belonging to either the wrapper node or the PHY child
nodes.
This is an unnecessary level of detail which has lead to problems when
later IP blocks using different register layouts have been forced to fit
the original mould rather than updating the binding. The bindings are
arguable also incomplete as they only the describe register blocks used
by the current Linux drivers.
Add a new binding for the UFS QMP PHYs found on SC8280XP which further
bindings can be based on.
Note that the current binding is simply removed instead of being
deprecated as it was only recently merged and support for SC8280XP is
still under development.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221024090041.19574-9-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 24 Oct 2022 09:00:38 +0000 (11:00 +0200)]
dt-bindings: phy: qcom,qmp-ufs: rename current bindings
The current QMP UFS PHY bindings are based on the original MSM8996 PCIe
PHY binding which provided multiple PHYs per IP block and these in turn
were described by child nodes.
The QMP UFS PHY block only provide a single PHY and the remnant child
node does not really reflect the hardware.
The original MSM8996 binding also ended up describing the individual
register blocks as belonging to either the wrapper node or the PHY child
nodes.
This is an unnecessary level of detail which has lead to problems when
later IP blocks using different register layouts have been forced to fit
the original mould rather than updating the binding. The bindings are
arguable also incomplete as they only the describe register blocks used
by the current Linux drivers.
In preparation for adding new bindings for SC8280XP which further
bindings can be based on, rename the current bindings after MSM8996 and
add a reference to the SC8280XP bindings.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221024090041.19574-8-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 24 Oct 2022 09:00:37 +0000 (11:00 +0200)]
phy: qcom-qmp-ufs: clean up PHY init
Clean up the PHY initialisation somewhat programming both tx and rx for
the second lane after the first lane.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221024090041.19574-7-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 24 Oct 2022 09:00:36 +0000 (11:00 +0200)]
phy: qcom-qmp-ufs: rename PHY ops structure
Rename the PHY operation structure so that it has a "phy_ops" suffix and
move it next to the implementation.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221024090041.19574-6-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 24 Oct 2022 09:00:35 +0000 (11:00 +0200)]
phy: qcom-qmp-ufs: clean up probe initialisation
Stop abusing the driver data pointer and instead pass the driver state
structure directly to the initialisation helpers during probe.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221024090041.19574-5-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 24 Oct 2022 09:00:34 +0000 (11:00 +0200)]
phy: qcom-qmp-ufs: clean up device-tree parsing
Since the QMP driver split there will be at most a single child node so
drop the obsolete iteration construct.
While at it, drop the verbose error logging that would have been
printed also on probe deferrals.
Note that there's no need to check if there are additional child nodes
(the kernel is not a devicetree validator), but let's return an error if
there are no child nodes at all for now.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221024090041.19574-4-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 24 Oct 2022 09:00:33 +0000 (11:00 +0200)]
phy: qcom-qmp-ufs: merge driver data
The UFS QMP PHY driver only manages a single PHY so merge the old
qcom_qmp and qmp_phy structures and drop the PHY array.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221024090041.19574-3-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 24 Oct 2022 09:00:32 +0000 (11:00 +0200)]
phy: qcom-qmp-ufs: move device-id table
Move the device-id table below probe() and next to the driver structure
to keep the driver callback functions grouped together.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221024090041.19574-2-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 26 Oct 2022 16:21:16 +0000 (18:21 +0200)]
phy: qcom-qmp-combo: fix NULL-deref on runtime resume
Commit
fc64623637da ("phy: qcom-qmp-combo,usb: add support for separate
PCS_USB region") started treating the PCS_USB registers as potentially
separate from the PCS registers but used the wrong base when no PCS_USB
offset has been provided.
Fix the PCS_USB base used at runtime resume to prevent dereferencing a
NULL pointer on platforms that do not provide a PCS_USB offset (e.g.
SC7180).
Fixes:
fc64623637da ("phy: qcom-qmp-combo,usb: add support for separate PCS_USB region")
Cc: stable@vger.kernel.org # 5.20
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20221026162116.26462-1-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Dmitry Baryshkov [Thu, 29 Sep 2022 19:00:17 +0000 (22:00 +0300)]
phy: qcom-qmp-usb: correct registers layout for IPQ8074 USB3 PHY
According to the kernel 4.4 sources from NHSS.QSDK.9.0.2 and according
to hardware docs, the PHY registers layout used for IPQ8074 USB3 PHY is
incorrect. This platform uses offset 0x174 for the PCS_STATUS register,
0xd8 for PCS_AUTONOMOUS_MODE_CTRL, etc.
Correct the PHY registers layout.
Fixes:
94a407cc17a4 ("phy: qcom-qmp: create copies of QMP PHY driver")
Fixes:
507156f5a99f ("phy: qcom-qmp: Add USB QMP PHY support for IPQ8074")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Kathiravan T<quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20220929190017.529207-1-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:50:02 +0000 (10:50 +0200)]
phy: qcom-qmp-usb: drop start and pwrdn-ctrl abstraction
Drop the start and pwrdn-ctrl abstractions which are no longer needed
since the QMP driver split.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-20-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:50:01 +0000 (10:50 +0200)]
phy: qcom-qmp-ufs: drop start and pwrdn-ctrl abstraction
Drop the start and pwrdn-ctrl abstractions which are no longer needed
since the QMP driver split.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-19-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:50:00 +0000 (10:50 +0200)]
phy: qcom-qmp-pcie-msm8996: drop start and pwrdn-ctrl abstraction
Drop the start and pwrdn-ctrl abstractions which are no longer needed
since the QMP driver split.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-18-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:59 +0000 (10:49 +0200)]
phy: qcom-qmp-pcie: add config sanity checks
The driver expects every configuration to set the pwrdn_ctrl and
phy_status masks. Add some probe WARN_ON_ONCE() to probe to catch any
new driver support that fails to provide them.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-17-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:58 +0000 (10:49 +0200)]
phy: qcom-qmp-pcie: drop start-ctrl abstraction
All PCIe PHYs need to start and stop the SerDes and PCS so drop the
start-ctrl abstraction which is no longer needed since the QMP driver
split.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-16-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:57 +0000 (10:49 +0200)]
phy: qcom-qmp-combo: drop start and pwrdn-ctrl abstraction
All USB PHYs need to start and stop the SerDes and PCS so drop the
start-ctrl abstraction which is no longer needed since the QMP driver
split.
Similarly, drop the pwrdn-ctrl abstraction which also is not needed
since the split.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-15-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:56 +0000 (10:49 +0200)]
phy: qcom-qmp-usb: increase status polling period
It typically takes between one and two milliseconds for the PHY to
become ready after starting it. Increase the tight 3--10 us polling
period to the more reasonable 51--200 us.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012085002.24099-14-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:55 +0000 (10:49 +0200)]
phy: qcom-qmp-usb: clean up status polling
Clean up the PHY status polling by dropping the configuration mask which
is no longer needed since the QMP driver split.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-13-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:54 +0000 (10:49 +0200)]
phy: qcom-qmp-ufs: increase ready polling period
It typically takes between one and two milliseconds for the PHY to
become ready after starting it. Increase the tight 3--10 us polling
period to the more reasonable 51--200 us.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012085002.24099-12-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:53 +0000 (10:49 +0200)]
phy: qcom-qmp-ufs: clean up ready polling
Clean up the PHY ready polling by dropping the mask variables which are
no longer needed since the QMP driver split.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-11-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:52 +0000 (10:49 +0200)]
phy: qcom-qmp-ufs: drop unused phy-status config
Drop the unused phy-status configuration mask which has never been used
for UFS PHYs.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-10-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:51 +0000 (10:49 +0200)]
phy: qcom-qmp-combo: increase status polling period
It typically takes between one and two milliseconds for the PHY to
become ready after starting it. Increase the tight 3--10 us polling
period to the more reasonable 51--200 us.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012085002.24099-9-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:50 +0000 (10:49 +0200)]
phy: qcom-qmp-combo: clean up status polling
Clean up the PHY status polling by dropping the configuration mask which
is no longer needed since the QMP driver split.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-8-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:49 +0000 (10:49 +0200)]
phy: qcom-qmp-pcie-msm8996: increase status polling period
It typically takes between one and two milliseconds for the PHY to
become ready after starting it. Increase the tight 3--10 us polling
period to the more reasonable 51--200 us.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012085002.24099-7-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:48 +0000 (10:49 +0200)]
phy: qcom-qmp-pcie-msm8996: clean up ready and status polling
Clean up the PHY ready and status polling by dropping the configuration
masks which are no longer needed since the QMP driver split.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-6-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:47 +0000 (10:49 +0200)]
phy: qcom-qmp-pcie: increase status polling period
It typically takes between one and two milliseconds for the PHY to
become ready after starting it. Increase the tight 3--10 us polling
period to the more reasonable 51--200 us.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012085002.24099-5-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:46 +0000 (10:49 +0200)]
phy: qcom-qmp-pcie: clean up status polling
Clean up the status polling by dropping the ready bit mask which is no
longer needed since the QMP driver split.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-4-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:45 +0000 (10:49 +0200)]
phy: qcom-qmp-pcie: fix ipq6018 initialisation
The phy_status mask was never set for IPQ6018 which meant that the
driver would not wait for the PHY to be initialised during power-on and
would never detect PHY initialisation timeouts.
Fixes:
520264db3bf9 ("phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-3-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:44 +0000 (10:49 +0200)]
phy: qcom-qmp-pcie: fix ipq8074-gen3 initialisation
The phy_status mask was never set for IPQ8074 (gen3) which meant that
the driver would not wait for the PHY to be initialised during power-on
and would never detect PHY initialisation timeouts.
Fixes:
334fad185415 ("phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-2-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:49:43 +0000 (10:49 +0200)]
phy: qcom-qmp-pcie: fix sc8180x initialisation
The phy_status mask was never set for SC8180X which meant that the
driver would not wait for the PHY to be initialised during power-on and
would never detect PHY initialisation timeouts.
Fixes:
f839f14e24f2 ("phy: qcom-qmp: Add sc8180x PCIe support")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-1-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Vidya Sagar [Thu, 13 Oct 2022 18:38:41 +0000 (00:08 +0530)]
phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration
Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change
to Gen1 during initialization. This helps in the below surprise link down
cases,
- Surprise link down happens at Gen3/Gen4 link speed.
- Surprise link down happens and external REFCLK is cut off, which causes
UPHY PLL rate to deviate to an invalid rate.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Link: https://lore.kernel.org/r/20221013183854.21087-9-vidyas@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:41 +0000 (10:12 +0200)]
phy: qcom-qmp-usb: drop power-down delay config
The power-down delay was included in the first version of the QMP driver
as an optional delay after powering on the PHY (using
POWER_DOWN_CONTROL) and just before starting it. Later changes modified
this sequence by powering on before initialising the PHY, but the
optional delay stayed where it was (i.e. before starting the PHY).
The vendor driver does not use a delay before starting the PHY and this
is likely not needed on any platform unless there is a corresponding
delay in the vendor kernel init sequence tables (i.e. in devicetree).
Let's keep the delay for now, but drop the redundant delay period
configuration while increasing the unnecessarily low timer slack
somewhat.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-15-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:40 +0000 (10:12 +0200)]
phy: qcom-qmp-usb: drop sc8280xp power-down delay
The SC8280XP PHY does not need a delay before starting the PHY (which is
what the has_pwrdn_delay config option really controls) so drop the
unnecessary delay.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012081241.18273-14-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:39 +0000 (10:12 +0200)]
phy: qcom-qmp-combo: drop power-down delay config
The power-down delay was included in the first version of the QMP driver
as an optional delay after powering on the PHY (using
POWER_DOWN_CONTROL) and just before starting it. Later changes modified
this sequence by powering on before initialising the PHY, but the
optional delay stayed where it was (i.e. before starting the PHY).
The vendor driver does not use a delay before starting the PHY and this
is likely not needed on any platform unless there is a corresponding
delay in the vendor kernel init sequence tables (i.e. in devicetree).
Let's keep the delay for now, but drop the redundant delay period
configuration while increasing the unnecessarily low timer slack
somewhat.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-13-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:38 +0000 (10:12 +0200)]
phy: qcom-qmp-combo: drop sc8280xp power-down delay
The SC8280XP combo PHY does not need a delay before starting the USB PHY
(which is what the has_pwrdn_delay config option really controls) so
drop the unnecessary delay.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012081241.18273-12-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:37 +0000 (10:12 +0200)]
phy: qcom-qmp-pcie-msm8996: drop power-down delay config
The power-down delay was included in the first version of the QMP driver
for MSM8996 as an optional delay after powering on the PHY (using
POWER_DOWN_CONTROL) and just before starting it. Later changes modified
this sequence by powering on before initialising the PHY, but the
optional delay stayed where it was (i.e. before starting the PHY).
The vendor driver does not use a delay before starting the PHY and this
is likely not needed on any platform unless there is a corresponding
delay in the vendor kernel init sequence tables (i.e. in devicetree).
Let's keep the delay for now, but drop the redundant configuration
options while increasing the unnecessarily low timer slack somewhat.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-11-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:36 +0000 (10:12 +0200)]
phy: qcom-qmp-pcie: replace power-down delay
The power-down delay was included in the first version of the QMP driver
as an optional delay after powering on the PHY (using
POWER_DOWN_CONTROL) and just before starting it. Later changes modified
this sequence by powering on before initialising the PHY, but the
optional delay stayed where it was (i.e. before starting the PHY).
The vendor driver does not use a delay before starting the PHY and this
is likely not needed on any platform unless there is a corresponding
delay in the vendor kernel init sequence tables (i.e. in devicetree).
But as the vendor kernel do have a 1 ms delay *after* starting the PHY
and before starting to poll the status it is possible that later
contributors have simply not noticed that the mainline power-down delay
is not equivalent.
As the current delay before even starting the PHY is pretty much
pointless and likely a mistake, move the delay after starting the PHY
which avoids a few iterations of polling and speeds up startup by 1 ms
(the poll loop otherwise takes about 1.8 ms).
Note that MSM8998 has never used a power-down delay so add a flag to
skip the delay in case starting the PHY is faster on MSM8998. This can
be removed after someone takes a measurement.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012081241.18273-10-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:35 +0000 (10:12 +0200)]
phy: qcom-qmp-pcie: drop power-down delay config
The power-down delay was included in the first version of the QMP driver
as an optional delay after powering on the PHY (using
POWER_DOWN_CONTROL) and just before starting it. Later changes modified
this sequence by powering on before initialising the PHY, but the
optional delay stayed where it was (i.e. before starting the PHY).
The vendor driver does not use a delay before starting the PHY and this
is likely not needed on any platform unless there is a corresponding
delay in the vendor kernel init sequence tables (i.e. in devicetree).
Let's keep the delay for now, but drop the redundant delay period
configuration while increasing the unnecessarily low timer slack
somewhat.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-9-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:34 +0000 (10:12 +0200)]
phy: qcom-qmp-usb: drop unused in-layout configuration
The QMP USB PHY driver does not use the "in-layout" configuration macro
to configure registers that are typically accessed using "regs_layout"
arrays (e.g. QPHY_START_CTRL) so drop this unused feature.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012081241.18273-8-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:33 +0000 (10:12 +0200)]
phy: qcom-qmp-ufs: drop unused in-layout configuration
The QMP UFS PHY driver does not use the "in-layout" configuration macro
to configure registers that are typically accessed using "regs_layout"
arrays (e.g. QPHY_START_CTRL) so drop this unused feature.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-7-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:32 +0000 (10:12 +0200)]
phy: qcom-qmp-pcie-msm8996: drop unused in-layout configuration
The MSM8996 QMP PCIe PHY driver no longer uses the "in-layout"
configuration macro to configure registers that are typically accessed
using "regs_layout" arrays (e.g. QPHY_START_CTRL) so drop this unused
feature.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-6-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:31 +0000 (10:12 +0200)]
phy: qcom-qmp-pcie: drop redundant ipq8074 power on
The PCS initialisation table for IPQ8074 includes updates of the reset
and start-control registers which is already handled explicitly by the
driver during power on.
Drop the redundant register write from the IPQ8074 configuration table
and along with it the now unused "in-layout" configuration macro and
code.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-5-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:30 +0000 (10:12 +0200)]
phy: qcom-qmp-combo: drop unused in-layout configuration
The QMP combo PHY driver does not use the "in-layout" configuration
macro to configure registers that are typically accessed using
"regs_layout" arrays (e.g. QPHY_START_CTRL) so drop this unused
feature.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-4-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:29 +0000 (10:12 +0200)]
phy: qcom-qmp: drop superfluous comments
Drop some unnecessary or incorrect comments.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-3-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Wed, 12 Oct 2022 08:12:28 +0000 (10:12 +0200)]
phy: qcom-qmp: drop regulator error message
Regulator core already logs an error message in case requesting a
regulator fails so drop the mostly redundant error message from probe.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-2-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 17 Oct 2022 06:50:13 +0000 (08:50 +0200)]
phy: qcom-qmp-pcie: drop bogus register update
Since commit
0d58280cf1e6 ("phy: Update PHY power control sequence") the
PHY is powered on before configuring the registers and only the MSM8996
PCIe PHY, which includes the POWER_DOWN_CONTROL register in its PCS
initialisation table, may possibly require a second update afterwards.
To make things worse, the POWER_DOWN_CONTROL register lies at a
different offset on more recent SoCs so that the second update, which
still used a hard-coded offset, would write to an unrelated register
(e.g. a revision-id register on SC8280XP).
As the MSM8996 PCIe PHY is now handled by a separate driver, simply drop
the bogus register update.
Fixes:
e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") added support
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #RB3
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221017065013.19647-12-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 17 Oct 2022 06:50:12 +0000 (08:50 +0200)]
phy: qcom-qmp-pcie: clean up clock lists
Keep the clock lists together and sorted by symbol name.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221017065013.19647-11-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Johan Hovold [Mon, 17 Oct 2022 06:50:11 +0000 (08:50 +0200)]
phy: qcom-qmp-usb: clean up power-down handling
Always define the POWER_DOWN_CONTROL register instead of falling back to
the v2 (and v3) offset during power on and power off.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221017065013.19647-10-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>