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Xiang, Haihao [Fri, 18 Apr 2014 16:12:42 +0000 (00:12 +0800)]
Remove unnecessary check with IS_GEN8()
It is always true or false
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
42258e128f19b93aa102672d5f61eb73d9f9808f)
Gwenole Beauchesne [Wed, 4 Jun 2014 08:36:28 +0000 (10:36 +0200)]
decoder: h264: don't allocate bottom DMV buffer on Broadwell.
Broadwell now uses a unique DMV buffer, irrespective of any field
coding mode. The dmv_buffer is not used, so it doesn't need to be
allocated at all.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Wed, 4 Jun 2014 09:17:52 +0000 (11:17 +0200)]
decoder: h264: only allocate tiled surfaces for Sandybridge an newer.
Don't allocate tiled surfaces on Ironlake platforms and earlier, stick
to linear surfaces.
This is a regression from
6d76944.
Reported-by: Haihao Xiang <haihao.xiang@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Fri, 9 May 2014 16:52:00 +0000 (18:52 +0200)]
decoder: h264: optimize support for grayscale surfaces.
Optimize support for grayscale surfaces in two aspects: (i) space
by only allocating the luminance component ; (ii) speed by avoiding
initialization of the (now inexistent) chrominance planes.
Keep backward compatibility with older codec layers that only
supported YUV 4:2:0 and not grayscale formats properly.
v2: fix check for extra H.264 chroma formats [Haihao]
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Wed, 14 May 2014 11:59:25 +0000 (13:59 +0200)]
decoder: h264: factor out allocation of reconstructed surfaces.
Add new avc_ensure_surface_bo() helper function to factor out the
allocatiion and initialization processes of the reconstructed VA
surface buffer stores.
Keep preferred native format (NV12) and initialize chroma values
to 0.0 (0x80) when needed for "fake" grayscale (Y800) surfaces
implemented on top of existing NV12.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Fri, 9 May 2014 16:15:23 +0000 (18:15 +0200)]
config: fix supported set of chroma formats for JPEG decode.
If the hardware supports JPEG decoding, then we have to expose the
right set of chroma formats for the output (decoded) VA surface. In
particular, we could support YUV 4:0:0, 4:1:0, 4:2:2 and 4:4:4.
v2: export support for YUV 4:0:0 (grayscale) too [Haihao]
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Fri, 9 May 2014 15:55:05 +0000 (17:55 +0200)]
config: fix vaCreateConfig() to not override user chroma format.
Only validate the user-defined chroma format (VAConfigAttribRTFormat)
attribute, if any. Don't override it. i.e. append a pre-defined value
only if it was not defined by the user beforehand.
Propertly return VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT if the supplied
chroma format is not supported.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Fri, 9 May 2014 16:30:33 +0000 (18:30 +0200)]
config: fix vaGetConfigAttributes() to validate profile/entrypoint.
Factor out code to validate profile/entrypoint per the underlying
hardware capabilities. Also fix vaGetConfigAttributes() to really
validate the profile/entrypoint pair.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Wed, 14 May 2014 11:42:51 +0000 (13:42 +0200)]
surface: factor out release of surface buffer storage.
Introduce a new i965_destroy_surface_storage() helper function to
unreference the underlying GEM buffer object, and any associated
private data, if any.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Wed, 14 May 2014 11:33:07 +0000 (13:33 +0200)]
surface: fix geometry (size, layout) of grayscale surfaces.
Fix size of the allocated buffer used to represent grayscale (Y800)
surfaces. Only the luminance component is needed, thus implying a
single plane.
Likewise, update render routines to only submit the first plane.
The existing render kernels readily only care about that single
plane.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Xiang, Haihao [Fri, 9 May 2014 08:31:54 +0000 (16:31 +0800)]
mpeg2: check frame_pred_frame_dct instead of progressive_frame
Some MPEG-2 videos set progressive_frame to 1 and set
frame_pred_frame_dct to 0, which is not conformed to MPEG-2 spec.
bottom field may be used to form prediction if frame_pred_frame_dct is
0. Previously the bottom field is excluded from the frame store list
https://bugs.freedesktop.org/show_bug.cgi?id=73424
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
b3031d16b1ea9ef2ab95bc09e59f0db5214a1125)
Xiang, Haihao [Fri, 9 May 2014 08:16:05 +0000 (16:16 +0800)]
Limit the minimum pitch for linear surface
pitch must be 64 at least for linear surface for most functions on IVB/HSW/BDW
such VEBOX, Data port media read/write
https://bugs.freedesktop.org/show_bug.cgi?id=72522
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
57db5c2524f4e3cb6ae2301bddfdf1c40cdbb626)
Xiang, Haihao [Thu, 24 Apr 2014 05:39:21 +0000 (13:39 +0800)]
Rename HAS_PP() to HAS_VPP()
Directly check the flag of has_vpp in codec_info
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
1c4d3468229797e787f4b99b0729baf90a115a1d)
Conflicts:
src/gen8_post_processing.c
src/i965_post_processing.c
Xiang, Haihao [Fri, 18 Apr 2014 16:12:41 +0000 (00:12 +0800)]
posst_processing_context_init()/finalize() callback functions for each platform
It is to reduce the usage of IS_GENxxx() as well.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
77b6a72504d917af9335ab94f6ecbefb8b087206)
Xiang, Haihao [Fri, 18 Apr 2014 16:12:40 +0000 (00:12 +0800)]
render_init()/render_terminate() callback functions for each platform
It is to reduce the usage of IS_GENxxx()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
f150fbf444ca63b5e9c3e8f7e17aa3386f7061fa)
Xiang, Haihao [Fri, 18 Apr 2014 16:12:39 +0000 (00:12 +0800)]
Simplify some macros
Now it can directly use the information in intel_device_info instead of
checking the pci id.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
f1b3f83953cd5f6e39900d98b4858a7cb825dee0)
Conflicts:
src/gen8_post_processing.c
src/i965_post_processing.c
src/intel_driver.h
Xiang, Haihao [Fri, 18 Apr 2014 16:12:38 +0000 (00:12 +0800)]
Remove max_wm_threads from render_state
Instead directly use the value stored in intel_device_info
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
6ba787b29e4bcebdceda52906e33cb84f24a63b5)
Xiang, Haihao [Fri, 18 Apr 2014 16:12:37 +0000 (00:12 +0800)]
Remove URB_SIZE()
Instead directly use the value stored in intel_device_info
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
a0fe5a6262f9ff1398a512c83d193556bbd0eae9)
Xiang, Haihao [Fri, 18 Apr 2014 16:12:36 +0000 (00:12 +0800)]
Dump chipset information in the vendor string
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
2518c1e741cb21c5412a4b5252ebe861a52c2900)
Xiang, Haihao [Fri, 18 Apr 2014 16:12:35 +0000 (00:12 +0800)]
Add a new intel_device_info structure
To store statically known device information
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
eb014a09fde988ba3ed2d2be6e8d6f0c650d281e)
Xiang, Haihao [Fri, 18 Apr 2014 16:12:34 +0000 (00:12 +0800)]
Move all of PCIIDs and codec info into separated files
The redundant code will be removed soon.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
d20db5984989626728f62eb3e02b60093d914d01)
Conflicts:
src/i965_drv_video.c
Zhong Li [Mon, 14 Apr 2014 08:17:42 +0000 (02:17 -0600)]
i965_DeriveImage() support JPEG color formats
Signed-off-by: Zhong Li <zhong.li@intel.com>
(cherry picked from commit
9f9c505ed5212ae0704f71f45532b9716ac0bd51)
Xiang, Haihao [Fri, 9 May 2014 04:51:08 +0000 (12:51 +0800)]
1.3.2.pre1 for development
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 9 May 2014 04:45:01 +0000 (12:45 +0800)]
Intel driver 1.3.1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 5 May 2014 07:38:52 +0000 (15:38 +0800)]
Update NEWS
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 5 May 2014 04:48:27 +0000 (12:48 +0800)]
Return error when trying to decoding an interlaced VC-1 video
https://bugs.freedesktop.org/show_bug.cgi?id=77386
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Mon, 5 May 2014 04:39:50 +0000 (12:39 +0800)]
Make it buildable against libva 1.3.0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
qing.zhang [Mon, 28 Apr 2014 21:44:47 +0000 (05:44 +0800)]
Fix over assigned callback "QueryConfigEntrypoints".
Sirisha Muppavarapu [Tue, 25 Mar 2014 22:04:30 +0000 (15:04 -0700)]
VPP: Enable Skin tone detection and enhancement - Added STDE coefficients.
In this commit, I added the optimized STDE coefficients to the vebox state table.
(cherry picked from commit
150f67c67bd92cd201b75a92388fe3a63b00cd8a)
Sirisha Muppavarapu [Tue, 25 Mar 2014 22:04:29 +0000 (15:04 -0700)]
VPP: Enable Skin Tone Detection and Enhancement feature in the driver.
The VPP-STDE feature is enabled in the driver code for gen75 and gen8.
In this commit, I added the filter and made appropriate changes to the
hw_codec_info and the supporting methods.
(cherry picked from commit
691b149b7afe578889a423841a29db3ac56aad83)
Gwenole Beauchesne [Wed, 23 Apr 2014 15:23:21 +0000 (17:23 +0200)]
vp8: fix support for segmentation-enabled streams.
If segmentation is enabled, then the segmentation map shall be live
across frames until the current frame updates the segment ids. This
means that the driver needs to maintain the segmentation map buffer
allocation and enable writes (resp. reads) whenever necessary.
This fixes decoding of 00-comprehensive-010.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Zhao Yakui [Tue, 22 Apr 2014 03:05:18 +0000 (11:05 +0800)]
VPP: Set the alpha channel when doing the conversion from NV12 to RGBA on Ivy/Haswell/BDW
Currently zero is written to alpha channel when doing the conversion
from NV12 to RGBA(BGRA), which affects the following the rendering operation.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
4082c9db1eef45bc117fc151d60a178926ab9f73)
Xiang, Haihao [Tue, 15 Apr 2014 02:20:31 +0000 (20:20 -0600)]
Fix bound checking
Otherwise it might result in buffer overflow.
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
782b8afdda14f000874d8acf51c3e8c490d55773)
Zhao Yakui [Wed, 9 Apr 2014 03:40:16 +0000 (11:40 +0800)]
Rendering/BDW:Follow the hardware spec to update the 3DSTATE_URB_VS command
This is to fix the GPU hang when doing the color-space conversion from
NV12 to RGB on BDW GT3 machine.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
4a3f17ae44bae58daf65dcc706332b28a6d478ac)
Gwenole Beauchesne [Tue, 8 Apr 2014 12:56:03 +0000 (06:56 -0600)]
vp8: fix loop filter for bitexact reconstruction.
Each loop filter delta update value shall be encoded within 7 bits,
including the sign bit and 6-bit magnitude in 2's complement. So,
don't propagate the sign bit while packing the filter level values.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit
36ccd9c3e47766edc70ecbdf82acc89ed67e26c4)
Zhao Yakui [Mon, 24 Mar 2014 02:46:14 +0000 (10:46 +0800)]
BDW: Fix one error in shader binaray for media encoding
The commit
7ac4263ff2dae5c877b92356d04df4ccfe10d7c9 updates
the shader binary more than it required. So it is removed.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
b1319c7f7cb9d20179b20dac2308330bd0e51ffe)
Alex wu [Mon, 24 Mar 2014 02:45:27 +0000 (20:45 -0600)]
V3: Add 422H support.
Changes between V3 to V2:
1. Add 422H support into gen8_post_processing.c, according to
yakui's comments.
changes between V2 and V1:
1. Rebase on staging branch.
2. Add 422H support for pp.
3. Reword the commit title.
Signed-off-by: Alex wu <zhiwen.wu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
347dd731d31dd37b242bbace744125554f2c09e7)
Zhao Yakui [Thu, 20 Mar 2014 04:08:51 +0000 (12:08 +0800)]
Use the VA_FOURCC_ABCD constant to replace the VA_FOURCC(A,B,C,D)
This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
acea969011bceee36a57fe2c0e4ee96c0c5e79c7)
Zhao Yakui [Mon, 24 Mar 2014 01:49:09 +0000 (09:49 +0800)]
VEBOX: Use the VA_FOURCC_ABCD constant to replace the VA_FOURCC(A,B,C,D)
This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
--
src/gen75_vpp_vebox.c | 83 ++++++++++++++++++++++++--------------------------
1 file changed, 41 insertions(+), 42 deletions(-)
(cherry picked from commit
2a31ad7e200cfb5df95b11875ee33795cdc7e343)
Zhao Yakui [Mon, 24 Mar 2014 01:49:06 +0000 (09:49 +0800)]
VPP: Use the VA_FOURCC_ABCD constant to replace the VA_FOURCC(A,B,C,D)
This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
0b9ed6ad9fbe46812d566fa31bf6d60739757a17)
Conflicts:
src/i965_post_processing.c
Zhao Yakui [Mon, 24 Mar 2014 01:48:50 +0000 (09:48 +0800)]
Use the VA_FOURCC_XXXX to replace the VA_FOURCC(X,X,X,X) in i965_drv_video
This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
ab3e02d63fe672e3f81631f2beb5bc2b7ab17af0)
Zhao, Halley [Fri, 21 Mar 2014 07:56:39 +0000 (01:56 -0600)]
Fix for check i965_check_alloc_surface_bo ret
Signed-off-by: Zhao Halley <halley.zhao@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
41da810decbb2d64843b95384fc87f7a29152c88)
Zhao, Halley [Fri, 14 Mar 2014 09:12:41 +0000 (17:12 +0800)]
clean up some assert in i965_drv_video.c
a return value is expected when assert is disabled.
Signed-off-by: Zhao Halley <halley.zhao@intel.com>
(cherry picked from commit
12c81227fd92fe028100af0cb32cc17b7f698b3d)
Zhao, Halley [Fri, 14 Mar 2014 05:43:33 +0000 (13:43 +0800)]
va: User specified tiling and stride support.
It is done by two VASurfaceAttrib:
* one is buffer attribute described by VASurfaceAttribExternalBufferDescriptor.
it covers strides and tiling or not.
* another is buffer type to indicate that the buffer is allocated by va driver.
VASurfaceAttribMemoryType:VA_SURFACE_ATTRIB_MEM_TYPE_VA
Signed-off-by: Zhao Halley <halley.zhao@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
55e63685dc040e3855868b4d7ccb0ac8e1f66690)
Zhao Yakui [Tue, 18 Mar 2014 08:15:15 +0000 (16:15 +0800)]
VPP: Fix the typo error of "VV16"
It should be "YV16" instead of "VV16".
Thank Gwenole for capturing this typo error which is caused by
the commit
2b5fad11a5c12d3c6ffbef15c02449a3b4e90b98.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
abd77ff2014322d152d723a3e8b1cba1e41b0a5f)
Zhao Yakui [Fri, 14 Mar 2014 07:16:26 +0000 (15:16 +0800)]
Add the csc conversion from YV16 to NV12
V1->V2: Follow Zhiwen's comment to handle the scenario of CSC conversion from
YV16 to NV12 when the source is YV16 image instead of YV16 surface.
Reviewed-by: Wind Yuan <feng.yuan@intel.com>
Tested-by: Wind Yuan <feng.yuan@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
2b5fad11a5c12d3c6ffbef15c02449a3b4e90b98)
Zhao Yakui [Fri, 14 Mar 2014 07:16:24 +0000 (15:16 +0800)]
Add the support of derive image from YV16 surface
Reviewed-by: Wind Yuan <feng.yuan@intel.com>
Tested-by: Wind Yuan <feng.yuan@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
7d5172de91336db2e627c0011404231b6b64b211)
Zhao Yakui [Fri, 14 Mar 2014 07:16:20 +0000 (15:16 +0800)]
Export the surface attribute based on YV16 for VPP on Gen7+
Reviewed-by: Wind Yuan <feng.yuan@intel.com>
Tested-by: Wind Yuan <feng.yuan@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
94f415b29ee197f66281370801a9c3bd4240c928)
Zhao Yakui [Fri, 14 Mar 2014 07:16:17 +0000 (15:16 +0800)]
Add the support of create surface based on YV16 format
Reviewed-by: Wind Yuan <feng.yuan@intel.com>
Tested-by: Wind Yuan <feng.yuan@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
12e7421ce1ed2627270dcb281af4d760afeb7209)
Zhao Yakui [Tue, 4 Mar 2014 08:23:08 +0000 (16:23 +0800)]
Add the seperated file for Video post-processing on BDW
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
6e1baecded9d23b32daa8e34828b6a5d32a27c46)
Conflicts:
src/i965_post_processing.c
Zhao Yakui [Tue, 4 Mar 2014 08:23:08 +0000 (16:23 +0800)]
Use the XXX_post_processing as callback function for post-processing
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
b7da102c3d237ac5553f8c8ada1bb155e5b8ea75)
Zhao Yakui [Tue, 4 Mar 2014 08:23:08 +0000 (16:23 +0800)]
Add the seperated file for rendering on BDW
This is to avoid the interference between the new platform and previous
platform.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
fbd6b7ff33ed5beb15f0122ec70668ed0c8479d2)
Zhao Yakui [Tue, 4 Mar 2014 08:23:07 +0000 (16:23 +0800)]
Use the XXX_render_put_surface/put_subpicture as callback function for rendering
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
9db92268b7b7bf6763ae76df0021608effe260ec)
Zhao Yakui [Tue, 4 Mar 2014 08:23:07 +0000 (16:23 +0800)]
Define i965_DestroySurfaces in header file explicitly to avoid multiple declaration
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
af0687252bfc6f81ff5361feedba7ec8989b3555)
Zhao Yakui [Tue, 4 Mar 2014 01:08:43 +0000 (09:08 +0800)]
BDW: Follow the spec to add the MEDIA_STATE_FLUSH before MEDIA_INTERFACE_LOAD
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
a90acbe7f08d66084e70113859198c3975f63b80)
Zhao Yakui [Tue, 4 Mar 2014 01:08:38 +0000 (09:08 +0800)]
bdw: Follow the spec to update the PIPE_CONTROL command
This is the hardware requirement.
Signed-off-by: Zhao Yakui <Yakui.zhao@intel.com>
(cherry picked from commit
fc4d39f3b849366ed04223620fa371d76cf813b0)
Zhao Yakui [Tue, 4 Mar 2014 01:08:34 +0000 (09:08 +0800)]
bdw: Fix the FENCE message in GPU shader for H264 encoding
Use the real register as write_back register instead of NULL register
although the Fence Message doesn't touch it.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
7ac4263ff2dae5c877b92356d04df4ccfe10d7c9)
Xiang, Haihao [Tue, 25 Mar 2014 00:55:14 +0000 (08:55 +0800)]
1.3.1.pre1 for development
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 24 Mar 2014 11:12:07 +0000 (19:12 +0800)]
Intel driver 1.3.0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 24 Mar 2014 08:52:52 +0000 (16:52 +0800)]
Fix the broken package made by 'make dist'
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 18 Mar 2014 00:49:04 +0000 (08:49 +0800)]
Fix broken make dist
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 17 Mar 2014 04:50:08 +0000 (12:50 +0800)]
Bump version to 1.3.0.pre1
To build the code, a new version of VA-API is needed, so
update the dependency on VA-API as well
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 18 Mar 2014 00:40:45 +0000 (08:40 +0800)]
Update NEWS
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 3 Mar 2014 02:34:43 +0000 (19:34 -0700)]
configure.ac: update the dependency on intel-gen4asm
The new version of intel-gen4asm is required to build shaders
for BDW
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Sun, 26 Jan 2014 01:43:52 +0000 (18:43 -0700)]
intel-vaapi: Add more checks for H264 decoding parameter to filter the unsupported clip
Signed-off-by: Yuan Feng <feng.yuan@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Mon, 20 Jan 2014 03:13:11 +0000 (11:13 +0800)]
Remove the redundant if () from gen8_pp_upload_constants
This fixed the issue reported by Klockwork
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 20 Jan 2014 03:04:24 +0000 (11:04 +0800)]
Warning fixes
gen8_mfd.c: In function ‘gen8_mfd_vp8_decode_init’:
gen8_mfd.c:2773:5: warning: implicit declaration of function ‘intel_update_vp8_frame_store_index’ [-Wimplicit-function-declaration]
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 20 Jan 2014 02:59:10 +0000 (10:59 +0800)]
Don't use assert() in case getting wrong parameters from user
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Mon, 20 Jan 2014 01:58:06 +0000 (09:58 +0800)]
Fix the wrong setting in MI_BATCH_BATCH_START command on Snb/Ivy/Haswell
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Fri, 17 Jan 2014 08:51:20 +0000 (16:51 +0800)]
Use the right parameters to initialize bit rate context
Reported-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 17 Jan 2014 08:46:52 +0000 (16:46 +0800)]
Don't advertise CBR for MPEG-2 encoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao, Halley [Wed, 15 Jan 2014 05:21:46 +0000 (13:21 +0800)]
Fix vp8 partition offset set error
Signed-off-by: Zhong Li <zhong.li@intel.com>
Zhong Li [Tue, 14 Jan 2014 02:44:55 +0000 (10:44 +0800)]
Fix vp8 p frame decode error issue.
Signed-off-by: Zhong Li <zhong.li@intel.com>
Zhao, Halley [Fri, 10 Jan 2014 01:53:16 +0000 (09:53 +0800)]
vp8 dec: fix when bool_coder_ctx.count is 0
bool_coder_ctx.count is remaining bits,
hw requires used-bits-count: 8-bool_coder_ctx.count, range [0,7]
update offset and partition_size[0] as well
Signed-off-by: Zhao Halley <halley.zhao@intel.com>
Zhao, Halley [Wed, 8 Jan 2014 19:14:24 +0000 (03:14 +0800)]
vp8 dec: follows va_dec_vp8.h update
key_frame:0 means an intra frame
bool_coder_ctx.count is the remaining bits in bool_coder_ctx.value, range[0,7)
slice_data_offset/macroblock_offset update
Signed-off-by: Zhao Halley <halley.zhao@intel.com>
Zhao Yakui [Mon, 13 Jan 2014 01:42:32 +0000 (09:42 +0800)]
Remove the unnecessary sorting to simplify the DPB buffer management
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Mon, 13 Jan 2014 01:42:28 +0000 (09:42 +0800)]
Complain the warning instead of assert fault when slice picture is not found in DPB for decoder
This is to fix the bug https://bugs.freedesktop.org/show_bug.cgi?id=72660
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Li Xiaowei [Thu, 9 Jan 2014 05:33:44 +0000 (13:33 +0800)]
VPP: Correct return value of vpp gpe functions
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Thu, 9 Jan 2014 01:23:13 +0000 (09:23 +0800)]
Remove the whitespace following trailing backslash in a Makefile.am
src/shaders/post_processing/gen8/Makefile.am:31: whitespace following trailing backslash
src/shaders/post_processing/gen8/Makefile.am:32: whitespace following trailing backslash
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li Xiaowei [Tue, 7 Jan 2014 03:38:09 +0000 (11:38 +0800)]
VPP: Enable sharpening feature on BDW
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li Xiaowei [Tue, 7 Jan 2014 02:45:56 +0000 (10:45 +0800)]
VPP: Refine code for sharpening on Haswell
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Tue, 7 Jan 2014 05:13:25 +0000 (13:13 +0800)]
VEBOX/bdw: set downsample method
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 7 Jan 2014 05:10:58 +0000 (13:10 +0800)]
VEBOX/bdw: DW0-DW8 are used for dndi parameters in VEBOX_DNDI_STATE
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Mon, 30 Dec 2013 04:42:55 +0000 (12:42 +0800)]
Add one environment variable to check the benchmark of decoding/vaPutsurface
The swap_buffer callback will wait for the completion of buffer swap, which
will affect the benchmark test of decoding/vaPutSurface.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Mon, 30 Dec 2013 04:42:51 +0000 (12:42 +0800)]
Render/BDW: Align each offset with 64 bytes
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Mon, 30 Dec 2013 04:42:47 +0000 (12:42 +0800)]
Render/BDW: Initialize the blend_state for rendering
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Mon, 30 Dec 2013 01:39:04 +0000 (09:39 +0800)]
Render/HSW: Fix the bug caused by merging code
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:56:37 +0000 (15:56 +0800)]
Update the MFX_AVC_IMAGE_STATE to follow the spec
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:56:33 +0000 (15:56 +0800)]
Fix the incorrect MV upper bound setting of MFC_IND_OBJ_BASE_ADDRESS_STAE for encoding on gen8
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:16:37 +0000 (15:16 +0800)]
Fix the wrong VPP initialization function for Dn/DI on Ivybridge
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:05:45 +0000 (15:05 +0800)]
Add the VPP shader of conversion between YUY2 and YUY2 on BDW
Signed-off-by: Zhao Yakui <yakui.zhao2intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:05:44 +0000 (15:05 +0800)]
Use the pp_null_initialize function for the unsupported VPP on BDW
The Dn/DI will be implemented by using VEBOX and doesn't use the VPP shader any more.
So the corresponding VPP shader should use the pp_null_initialize hook function.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:05:44 +0000 (15:05 +0800)]
Fix the error for the VPP conversion of NV12->NV12 on BDW
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:05:44 +0000 (15:05 +0800)]
Use the correct sub-context for VPP on BDW to avoid the NULL pointer
The structure of sub-context is updated for VPP in the commit of
4faf6bf47f8e4e2fe587e3bb6a004340edd59c4c. So BDW should update the correct
sub-context.Otherwise the segment fault will be triggered.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:05:44 +0000 (15:05 +0800)]
Add the support of querying the surface attributes on BDW
Otherwise the user-space application doesn't query which surfaceformat is
supported by the libva-vappi driver on BDW.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:05:44 +0000 (15:05 +0800)]
Fix the wrong pitch of surface for Video post-processing on BDW
Now the object surface already contains the pitch after the object surface
structure is reworked in the commit
f886f24eaaacba9544fa5f6405b7382c686f3a1f.
So it is unnecessary to calculate the pitch based on the width.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:05:44 +0000 (15:05 +0800)]
Follow the spec to make the VPP media pipeline work in 48-bit addressing mode
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 27 Dec 2013 07:05:44 +0000 (15:05 +0800)]
Fix the error of offset calculation for encoding on BDW
Currently although the encoding can work well, the offset in the internal
object is calculated incorrectly. So fix it to avoid the potential issue.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Fri, 27 Dec 2013 03:16:48 +0000 (11:16 +0800)]
VPP/bdw: Fix the initialize function used for NV12 to NV12
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhong Li [Wed, 25 Dec 2013 06:23:29 +0000 (14:23 +0800)]
Add the ring supported for bdw vpp filters
Signed-off-by: Zhong Li <zhong.li@intel.com>