[ProfileData] Change std::sort to llvm::sort in response to r327219

Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: bogner, vsk, eraman, ruiu

Reviewed By: ruiu

Subscribers: ruiu, llvm-commits

Differential Revision: https://reviews.llvm.org/D45139

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330057 91177308-0d34-0410-b5e6-96231b3b80d8

[CostModel][X86] Add some specific cpu targets to the cost models

We're mostly testing with generic isa attributes, but PR36550 will require testing of specific target's scheduler models as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330056 91177308-0d34-0410-b5e6-96231b3b80d8

[CostModel][X86] Split fma arith costs tests from other fp tests

Was proving cumbersome to test with/without fma

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330054 91177308-0d34-0410-b5e6-96231b3b80d8

[LTO] Change std::sort to llvm::sort in response to r327219

Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer D44363 for a list of all the required patches.

Reviewers: pcc, mehdi_amini, ruiu

Reviewed By: ruiu

Subscribers: ruiu, inglorion, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D45137

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330053 91177308-0d34-0410-b5e6-96231b3b80d8

[CostModel][X86] Regenerate latency/codesize cost tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330052 91177308-0d34-0410-b5e6-96231b3b80d8

[CostModel][X86] Regenerate cast conversion cost tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330051 91177308-0d34-0410-b5e6-96231b3b80d8

[CostModel][X86] Regenerate masked intrinsic cost tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330050 91177308-0d34-0410-b5e6-96231b3b80d8

Define InitLLVM to do common initialization all at once.

We have a few functions that virtually all command wants to run on
process startup/shutdown. This patch adds InitLLVM class to do that
all at once, so that we don't need to copy-n-paste boilerplate code
to each llvm command's main() function.

Differential Revision: https://reviews.llvm.org/D45602

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330046 91177308-0d34-0410-b5e6-96231b3b80d8

hwasan: add -fsanitize=kernel-hwaddress flag

This patch adds -fsanitize=kernel-hwaddress flag, that essentially enables
-hwasan-kernel=1 -hwasan-recover=1 -hwasan-match-all-tag=0xff.

Differential Revision: https://reviews.llvm.org/D45046

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330044 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine][NFC] masked-merge: commutativity tests: ensure the ordering.

This was intended since initially, but i did not really think
about it, and did not know how to force that. Now that the
xor->or fold is working (patch upcoming), this came up
to improve the test coverage.

A followup for rL330003, rL330007
https://bugs.llvm.org/show_bug.cgi?id=6773

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330039 91177308-0d34-0410-b5e6-96231b3b80d8

Add PPC64_GLINK dynamic tag.

Add support for the PPC64_GLINK dynamic tag which is used in the ElfV2 abi.

Differential Revision: https://reviews.llvm.org/D45574

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330038 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Materialize constants for multiplication

Previously, the MIPS backend would alwyas break down constant multiplications
into a series of shifts, adds, and subs. This patch changes that so the cost of
doing so is estimated.

The cost is estimated against worst case constant materialization and retrieving
the results from the HI/LO registers.

For cases where the value type of the multiplication is not legal, the cost of
legalization is estimated and is accounted for before performing the
optimization of breaking down the constant

This resolves PR36884.

Thanks to npl for reporting the issue!

Reviewers: abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D45316

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330037 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove remaining itinerary support from instructions and target (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330035 91177308-0d34-0410-b5e6-96231b3b80d8

[ARM] FP16 vmaxnm/vminnm scalar instructions

This adds code generation support for the FP16 vmaxnm/vminnm scalar
instructions.

Differential Revision: https://reviews.llvm.org/D44675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330034 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r330027: "[llvm-exegesis] re-enable failing tests after r330026."

The tests are still failing on some bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330033 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-mca] Ensure that instructions with a schedule read-advance are always issued in the right order.

Normally, the Scheduler prioritizes older instructions over younger instructions
during the instruction issue stage. In one particular case where a dependent
instruction had a schedule read-advance associated to one of the input operands,
this rule was not correctly applied.

This patch fixes the issue and adds a test to verify that we don't regress that
particular case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330032 91177308-0d34-0410-b5e6-96231b3b80d8

[ARC] Add LImm support for J/JL

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330031 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Generalize X86FixupLEAs to work with TargetSchedModel

Similar to rL329834, don't rely on itinerary scheduler model to determine latencies for LEA thresholds, use the generic TargetSchedModel::computeInstrLatency call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330030 91177308-0d34-0410-b5e6-96231b3b80d8

[profile] Fix binary format reader error propagation.

Summary:
This was originally part of rL328132, and led to the discovery
of the issues addressed in rL328987. Re-landing.

Reviewers: xur, davidxl, bkramer

Reviewed By: bkramer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45545

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330029 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-exegesis] re-enable failing tests after r330026.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330027 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-exegesis] Fix use after free.

Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D45625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330026 91177308-0d34-0410-b5e6-96231b3b80d8

Remove comment reference to itineraries. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330025 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructions

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45618

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330024 91177308-0d34-0410-b5e6-96231b3b80d8

[X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not WriteFAdd

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330023 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove remaining OpndItins/SizeItins from all instruction defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330022 91177308-0d34-0410-b5e6-96231b3b80d8

Remove comment references to itineraries. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330021 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-exegesis][NFC] Add more logging in case target creation fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330020 91177308-0d34-0410-b5e6-96231b3b80d8

Remove out of data comment. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330019 91177308-0d34-0410-b5e6-96231b3b80d8

[PostRASink]Add register dependency check for implicit operands

Summary:
This change extend the register dependency check for implicit operands in Copy instructions.
Fixes PR36902.

Reviewers: thegameg, sebpop, uweigand, jnspaulsson, gberry, mcrosier, qcolombet, MatzeB

Reviewed By: thegameg

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330018 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine][NFC] Regenerate logical-select.ll test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330017 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-exegesis] Create test files in temporary directory.

Currently the test fails in sandboxed environnements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330015 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.

Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.

This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45432

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330014 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330013 91177308-0d34-0410-b5e6-96231b3b80d8

[NEON] Support intrinsic for scalar and vector versions of the VRINTN instruction

Differential Revision: https://reviews.llvm.org/D45514

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330011 91177308-0d34-0410-b5e6-96231b3b80d8

Partially revert r330008.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330010 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-exegesis] Run unit tests on more platforms.

Summary:
 - Target-independent tests are run all the time.
 - Tests that codegen X86 code are run when X86 is in build targets.
 - Tests that run X86 jitted code are run only on X86 hosts.

Reviewers: gchatelet

Subscribers: mgorny, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D45614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330008 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine][NFC] Add last few tests with constant mask for masked merge folding.

A followup for rL330003
https://bugs.llvm.org/show_bug.cgi?id=6773

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330007 91177308-0d34-0410-b5e6-96231b3b80d8

[NFC] fix trivial typos in comments

"the the" -> "the", "we we" -> "we", etc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330006 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine][NFC] Add tests for masked merge folding.

https://bugs.llvm.org/show_bug.cgi?id=6773

As discussed there, some backends may want to undo this fold
(x86+bmi for scalars, x86+sse for vectors, ...)
https://bugs.llvm.org/show_bug.cgi?id=37104

https://rise4fun.com/Alive/JXt

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330003 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine]: foldSelectICmpAndAnd(): and is commutative

Summary:
The fold added in D45108 did not account for the fact that
the and instruction is commutative, and if the mask is a variable,
the mask variable and the fold variable may be swapped.

I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]]

This extends/generalizes that fold, so it is handled too.

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45539

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330001 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Add support for parsing and printing SVE vector lists.

Summary:
Added Z_(b|h|s|d) vector list RegisterOperands along with support to
add/print the vector lists.

This is patch [5/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: fhahn

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45431

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330000 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Introduce cldemote instruction

Hint to hardware to move the cache line containing the
address to a more distant level of the cache without
writing back to memory.

Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329992 91177308-0d34-0410-b5e6-96231b3b80d8

[Support] Fix building for Windows on ARM

The commit in SVN r310001 that added support for this actually didn't
use the right struct field for the frame pointer - for ARM, there is
no register named Fp in the CONTEXT struct. On Windows, the R11
register is used as frame pointer.

Differential Revision: https://reviews.llvm.org/D45590

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329991 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.

This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics.

We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329990 91177308-0d34-0410-b5e6-96231b3b80d8

Enable debug fission for thinLTO linked via gold-plugin

Summary: This enables debug fission on implicit ThinLTO when linked with gold. It will put the .dwo files in a directory specified by user.

Reviewers: tejohnson, pcc, dblaikie

Reviewed By: pcc

Subscribers: JDevlieghere, mehdi_amini, inglorion

Differential Revision: https://reviews.llvm.org/D44792

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329988 91177308-0d34-0410-b5e6-96231b3b80d8

[CallSiteSplit] Fix comment. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329987 91177308-0d34-0410-b5e6-96231b3b80d8

Fix another bot failure from r329951.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329986 91177308-0d34-0410-b5e6-96231b3b80d8

[AMDGPU] Update relocation record description

Document which relocation records are static and dynamic.

Differential Revision: https://reviews.llvm.org/D45587

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329981 91177308-0d34-0410-b5e6-96231b3b80d8

[lit] Remove duplicate to_string method

There are two versions of to_string used by TestRunner.py. The one defined
in TestRunner.py and the one defined in utils/lit/lit/util.py. The util.py
version is superior to the TestRunner.py version.

This change removes the duplicate to_string in TestRunner.py in favor of
always using the version from util.py. Beside removing duplicate code, this
makes it easier to debug TestRunner.py since only one version of to_string
is used.

Patch by Stella Stamenova!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329972 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove unused MoveLoadStoreItins/ShiftOpndItins schedule class wrappers.

Was being used to move around empty/unused itineraries...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329970 91177308-0d34-0410-b5e6-96231b3b80d8

Free a pointer, fix a bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329969 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove x86 InstrItinClass entries (PR37093)

This removes the last of the x86 schedule itineraries, I'm intending to cleanup the remaining uses of NoItinerary/OpndItins/etc. before resolving PR37093.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329967 91177308-0d34-0410-b5e6-96231b3b80d8

[CachePruning] Clarify the per-directory entry limit on Linux ext4.

Summary:
508   root node entries (root_limit)
510   internal node entries (node_limit)

For a filename with 40 bytes, its sizeof(ext4_dir_entry_2) = 48, a linear directory can contain at most floor(4096/48)=85 of them.
The real per-directory entry limit should be 508*510*85 = 22021800
The limit varies with the average length of filenames.

However, the Linux ext4 code does not try rebalancing the htree, so we will not be able to create filenames in a full leaf node. This is demonstrated with the following example, certain filenames cannot be used while others can:

  % touch d/0000000000000000000000000000000000816a6f
  touch: cannot touch 'd/0000000000000000000000000000000000816a6f': No
  space left on device
  % touch d/0000000000000000000000000000000000816a70
  # succeeded

Reviewers: pcc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45546

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329966 91177308-0d34-0410-b5e6-96231b3b80d8

[DAGCombiner] simplify code; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329964 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] add fsub-fneg test; NFC

This is a test for a transform that was suggested in the post-commit
mailing list thread for rL329821. The target in question is not in
trunk, so PPC gets to stand in for it because it's the only in-tree
target that sets 'isFPExtFree()' to 'true'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329963 91177308-0d34-0410-b5e6-96231b3b80d8

Don't call skipModule for CFI lowering passes.

opt-bisect shouldn't skip these passes; they lower intrinsics which
no other pass can handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329961 91177308-0d34-0410-b5e6-96231b3b80d8

[ProfileSummary] Remove repeated cutoffs; NFCI

I'm told the repeat of "500000, 600000," is accidental, and should be
removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329959 91177308-0d34-0410-b5e6-96231b3b80d8

Let llvm-diff correctly deal with Undef/ConstantAggregateZero/ConstantVector/IndirectBr

Summary:
llvm-diff incorrectly reports that there's a diff when input IR contains undef/zeroinitializer/constantvector/indirectbr.
(This happens even if two identical files are given, e.g. `llvm-diff x.ll x.ll`)

This is fix to the bug report https://bugs.llvm.org/show_bug.cgi?id=33623 .

Reviewers: dexonsmith, rjmccall

Reviewed By: rjmccall

Subscribers: chenwj, mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D34856

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329957 91177308-0d34-0410-b5e6-96231b3b80d8

AArch64: Introduce a DAG combine for folding offsets into addresses.

This is a code size win in code that takes offseted addresses
frequently, such as C++ constructors that typically need to compute
an offseted address of a vtable. This reduces the size of Chromium
for Android's .text section by 108KB.

Differential Revision: https://reviews.llvm.org/D45199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329956 91177308-0d34-0410-b5e6-96231b3b80d8

[DebugInfo] Create merged locations for instructions other than calls

This lifts a restriction on DILocation::getMergedLocation(), allowing it
to create merged locations for instructions other than calls.

Instruction::applyMergedLocation() now defaults to creating merged
locations for all instructions.

The default behavior of getMergedLocation() is unchanged: callers which
invoke it directly are unaffected.

This change will enable a follow-up Mem2Reg fix which improves crash
reporting.

Differential Revision: https://reviews.llvm.org/D45396

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329955 91177308-0d34-0410-b5e6-96231b3b80d8

[ProfileSummary] Move a vector we're about to destroy anyway; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329954 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329953 91177308-0d34-0410-b5e6-96231b3b80d8

[demangler] Add a partial demangling API for LLDB.

This parses a mangled name into an AST (typically an intermediate stage in
itaniumDemangle) and provides some functions to query certain properties or
print certain parts of the demangled name.

Differential revision: https://reviews.llvm.org/D44668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329951 91177308-0d34-0410-b5e6-96231b3b80d8

[demangler] NFC: Some refactoring to support partial demangling.

I'm committing this to libcxxabi too so that the two demanglers remain as
simular as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329950 91177308-0d34-0410-b5e6-96231b3b80d8

[WebAssembly] libObject: Don't include the name the size of custom sections

Differential Revision: https://reviews.llvm.org/D45579

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329947 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove InstrItinClass entries from SSE/AVX instructions defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329945 91177308-0d34-0410-b5e6-96231b3b80d8

[ORC] Use insert rather than emplace.

Hopefully this will fix the build failure at
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/9028

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329944 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify; NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329943 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove explicit SSE/AVX schedule itineraries from defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329940 91177308-0d34-0410-b5e6-96231b3b80d8

[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0

Summary:
GCC compresses the pseudo instruction "mv rd, rs",  which is an alias of
"addi rd, rs, 0", to "c.mv rd, rs".

In LLVM we rely on the canonical MC instruction (MCInst) to do our compression
checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv
rd, rs" we lose this compression opportunity to gcc.

 In this patch we fix that by adding an addi to c.mv compression pattern, the
 instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like
 gcc does.

Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal).

Reviewers: asb, apazos, zzheng, mgrang, shiva0217

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits

Differential Revision: https://reviews.llvm.org/D45583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329939 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove remaining gpr schedule itineraries (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329938 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Introduce LLVM wbinvd intrinsic

A previously missing intrinsic for an old instruction.

Reviewers: craig.topper, echristo

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45312

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329936 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a typo in a comment; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329935 91177308-0d34-0410-b5e6-96231b3b80d8

[ORC] Plumb error notifications through the VSO interface.

This allows materializers to notify the VSO that they were unable to
resolve or finalize symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329934 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove gpr shift/extension schedule itineraries (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329933 91177308-0d34-0410-b5e6-96231b3b80d8

[Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision

Legalize and emit code for:

  * xscvsdqp
  * xscvudqp

Differential Revision: https://reviews.llvm.org/D45230

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329931 91177308-0d34-0410-b5e6-96231b3b80d8

[MCJIT] Remove the anchor from mcjit.

This is a layering violation. LTO shouldn't depend on MCJIT. The right
fix for this is moving the class somewhere else.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329929 91177308-0d34-0410-b5e6-96231b3b80d8

[MIPS GlobalISel] remove superfluous #includes (NFC)

Remove superfluous #includes.
Minor code style change in MipsCallLowering::lowerFormalArguments().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329926 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64] Move AFI->setRedZone(false) to top of emitPrologue

AFI->setRedZone(false) was put in the wrong place before, and so it only fired
on functions that didn't have stack frames. This moves that to the top of
emitPrologue to make sure that every function without a redzone has it set
correctly.

This also adds a function representing one of the early exit cases (GHC calling
convention) to the MachineOutliner noredzone test to ensure that we can outline
from functions like these, where we never use a redzone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329922 91177308-0d34-0410-b5e6-96231b3b80d8

revert r328921 - [DAGCombine] (float)((int) f) --> ftrunc (PR36617)

This change is exposing UB in source code - as was warned/predicted. :)
See D44909 for discussion. Reverting while we figure out how to fix things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329920 91177308-0d34-0410-b5e6-96231b3b80d8

[Pipeliner] Use std::stable_sort when ordering NodeSets

There are cases when individual NodeSets can be equal with respect to
the ordering criteria. Since they are stored in an ordered container,
use stable_sort to preserve the relative order of equal NodeSets.

This should remove non-determinism discovered by shuffling done in
llvm::sort with expensive checks enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329915 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Correct the predicates of the load/store (double)word for coprocessor 3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329913 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedule itineraries (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329912 91177308-0d34-0410-b5e6-96231b3b80d8

Revert "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time."

This reverts commit r329865. Causes stage2/stage3 miscompare.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329910 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][AsmParser] Unify 'addVectorListOperands' functions.

Summary:
Merged 'addVectorList64Operands' and 'addVectorList128Operands' into a
generic 'addVectorListOperands', which can be easily extended to work
for SVE vectors.

This is patch [4/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329909 91177308-0d34-0410-b5e6-96231b3b80d8

[CodeGen] Allow printing MachineMemOperands with less context in SDAGDumper

Don't assume SelectionDAG is non-null as the targets can use it with a
null pointer.

Differential Revision: https://reviews.llvm.org/D44611

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329908 91177308-0d34-0410-b5e6-96231b3b80d8

[IRCE] isKnownNonNegative helper function

Created a helper function to query for non negative SCEVs. Uses the
SGE predicate to catch constants that could be interpreted as
negative.

Differential Revision: https://reviews.llvm.org/D45481

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329907 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove remaining system/special schedule itineraries (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329906 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx.

Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D44436

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329905 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove system/control schedule itineraries (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329903 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine][NFC]: Add tests: foldSelectICmpAndAnd(): and is commutative

Summary:
The fold added in D45108 did not account for the fact that
the and instruction is commutative, and if the mask is a variable,
the mask variable and the fold variable may be swapped.

I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]]

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45538

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329901 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][AsmParser] Make parse function for VectorLists generic to other vector types.

Summary:
Added 'RegisterKind' to the VectorListOp structure, so that this operand
type can be reused for SVE vector lists in a later patch. It also
refactors the 'tryParseVectorList' function so it can be used directly
in the ParserMethod of an operand. The parsing can now parse multiple
kinds of vectors and recover if there is no match.

This is patch [3/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329900 91177308-0d34-0410-b5e6-96231b3b80d8

[RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC

Summary:

According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only
allow 32-bit instruction alignment, but instruction allow to be aligned
to 16-bit boundaries for C-extension.

So we just align to 4 bytes and 2 bytes for C-extension is enough.

Reviewers: asb, apazos

Differential Revision: https://reviews.llvm.org/D45560

Patch by Kito Cheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329899 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove CMOV/SETCC schedule itineraries (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329898 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove MMX/3DNow schedule itineraries (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329896 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-mca] Removed unused argument from cycleEvent. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329895 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove X87 schedule itineraries (PR37093)

First of a number of commits to remove x86 schedule itineraries entirely - approved off-line with @craig.topper

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329893 91177308-0d34-0410-b5e6-96231b3b80d8

[MIPS GlobalISel] minor update to MIR tests added in r329819

Remove 'registers' section, as suggested (D. Sanders) at code review

https://reviews.llvm.org/D44304

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329888 91177308-0d34-0410-b5e6-96231b3b80d8

[SystemZ]  Use ResourceCycles=30 for FPd unit (NFC).

This is better than listing FPd 30 times :-)

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329887 91177308-0d34-0410-b5e6-96231b3b80d8

[SystemZ]  Remove FullInstRWOverlapCheck from SchedMachineModels.

This is NFC, even though it caught just a few cases of overlapping regular
expressions.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329886 91177308-0d34-0410-b5e6-96231b3b80d8