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Oliver Stannard [Thu, 21 Aug 2014 12:50:31 +0000 (12:50 +0000)]
[ARM] Enable DP copy, load and store instructions for FPv4-SP
The FPv4-SP floating-point unit is generally referred to as
single-precision only, but it does have double-precision registers and
load, store and GPR<->DPR move instructions which operate on them.
This patch enables the use of these registers, the main advantage of
which is that we now comply with the AAPCS-VFP calling convention.
This partially reverts r209650, which added some AAPCS-VFP support,
but did not handle return values or alignment of double arguments in
registers.
This patch also adds tests for Thumb2 code generation for
floating-point instructions and intrinsics, which previously only
existed for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216172
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Rafael Espindola [Thu, 21 Aug 2014 12:39:07 +0000 (12:39 +0000)]
Sort declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216171
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Benjamin Kramer [Thu, 21 Aug 2014 11:22:05 +0000 (11:22 +0000)]
Make format_object_base's destructor protected and non-virtual.
It's not meant to be used with operator delete and this avoids emitting virtual
dtors for every derived format object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216170
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Erik Verbruggen [Thu, 21 Aug 2014 10:45:30 +0000 (10:45 +0000)]
Reassociate x + -0.1234 * y into x - 0.1234 * y
This does not require -ffast-math, and it gives CSE/GVN more options to
eliminate duplicate expressions in, e.g.:
return ((x + 0.1234 * y) * (x - 0.1234 * y));
Differential Revision: http://reviews.llvm.org/D4904
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216169
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Benjamin Kramer [Thu, 21 Aug 2014 10:31:37 +0000 (10:31 +0000)]
X86: Turn redundant if into an assertion.
While there remove noop casts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216168
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Robert Khasanov [Thu, 21 Aug 2014 09:43:43 +0000 (09:43 +0000)]
[x86] Added _addcarry_ and _subborrow_ intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216164
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Robert Khasanov [Thu, 21 Aug 2014 09:34:12 +0000 (09:34 +0000)]
[x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216163
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Robert Khasanov [Thu, 21 Aug 2014 09:27:00 +0000 (09:27 +0000)]
[x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216162
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Robert Khasanov [Thu, 21 Aug 2014 09:16:12 +0000 (09:16 +0000)]
[x86] Enable Broadwell target.
Added FeatureSMAP.
Broadwell ISA includes Haswell ISA + ADX + RDSEED + SMAP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216161
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Zinovy Nis [Thu, 21 Aug 2014 08:25:45 +0000 (08:25 +0000)]
[INDVARS] Extend using of widening of induction variables for the cases of "sub nsw" and "mul nsw" instructions.
Currently only "add nsw" are widened. This patch eliminates tons of "sext" instructions for 64 bit code (and the corresponding target code) in cases like:
int N = 100;
float **A;
void foo(int x0, int x1)
{
float * A_cur = &A[0][0];
float * A_next = &A[1][0];
for(int x = x0; x < x1; ++x).
{
// Currently only [x+N] case is widened. Others 2 cases lead to sext.
// This patch fixes it, so all 3 cases do not need sext.
const float div = A_cur[x + N] + A_cur[x - N] + A_cur[x * N];
A_next[x] = div;
}
}
...
> clang++ test.cpp -march=core-avx2 -Ofast -fno-unroll-loops -fno-tree-vectorize -S -o -
Differential Revision: http://reviews.llvm.org/D4695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216160
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Elena Demikhovsky [Thu, 21 Aug 2014 07:01:55 +0000 (07:01 +0000)]
IntelJITEventListener updates to fix breaks by recent changes to EngineBuilder and DIContext.
By Arch Robison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216159
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Craig Topper [Thu, 21 Aug 2014 05:55:13 +0000 (05:55 +0000)]
Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid needing to mention the size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216158
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David Majnemer [Thu, 21 Aug 2014 05:14:48 +0000 (05:14 +0000)]
InstCombine: Fold ((A | B) & C1) ^ (B & C2) -> (A & C1) ^ B if C1^C2=-1
Adapted from a patch by Richard Smith, test-case written by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216157
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Craig Topper [Thu, 21 Aug 2014 04:31:10 +0000 (04:31 +0000)]
Remove custom implementations of max/min in StringRef that was originally added to work an old gcc bug. I believe its been fixed by now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216156
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Eric Fiselier [Thu, 21 Aug 2014 04:27:11 +0000 (04:27 +0000)]
add self to credits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216155
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Jiangning Liu [Thu, 21 Aug 2014 02:12:35 +0000 (02:12 +0000)]
Fix a bug around truncating vector in const prop.
In constant folding stage, "TRUNC" can't handle vector data type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216149
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Jiangning Liu [Thu, 21 Aug 2014 01:59:30 +0000 (01:59 +0000)]
Revert r216066, "Optimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG Builder and type".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216147
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Quentin Colombet [Thu, 21 Aug 2014 00:19:16 +0000 (00:19 +0000)]
[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the
advanced copy optimization.
This is the final step patch toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov.32 d16[0], r0
vmov.32 d16[1], r1
and is able to rewrite the following sequence:
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
into simple generic GPR copies that the coalescer managed to remove.
<rdar://problem/
12702965>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216144
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Quentin Colombet [Thu, 21 Aug 2014 00:10:52 +0000 (00:10 +0000)]
[ARM] Mark VSETLNi32 with the InsertSubreg property and implement the related
target hook.
This patch teaches the compiler that:
dX = VSETLNi32 dY, rZ, imm
is the same as:
dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(imm)
<rdar://problem/
12702965>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216143
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James Molloy [Thu, 21 Aug 2014 00:02:51 +0000 (00:02 +0000)]
[LoopVectorize] Up the maximum unroll factor to 4 for AArch64
Only for Cortex-A57 and Cyclone for now, where it has shown wins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216141
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James Molloy [Wed, 20 Aug 2014 23:53:52 +0000 (23:53 +0000)]
[LoopVectorizer] Limit unroll factor in the presence of nested reductions.
If we have a scalar reduction, we can increase the critical path length if the loop we're unrolling is inside another loop. Limit, by default to 2, so the critical path only gets increased by one reduction operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216140
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Quentin Colombet [Wed, 20 Aug 2014 23:49:36 +0000 (23:49 +0000)]
Add isInsertSubreg property.
This patch adds a new property: isInsertSubreg and the related target hooks:
TargetIntrInfo::getInsertSubregInputs and
TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific
instruction is a (kind of) INSERT_SUBREG.
The approach is similar to r215394.
<rdar://problem/
12702965>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216139
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Jonathan Roelofs [Wed, 20 Aug 2014 23:38:50 +0000 (23:38 +0000)]
Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence
On pre-v6 hardware, 'MOV lo, lo' gives undefined results, so such copies need to
be avoided. This patch trades simplicity for implementation time at the expense
of performance... As they say: correctness first, then performance.
See http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075998.html for a few
ideas on how to make this better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216138
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Quentin Colombet [Wed, 20 Aug 2014 23:25:28 +0000 (23:25 +0000)]
Mention the right target hook in the comment on isExtractSubreg property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216137
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Quentin Colombet [Wed, 20 Aug 2014 23:13:02 +0000 (23:13 +0000)]
[PeepholeOptimizer] Take advantage of the isExtractSubreg property in the
advanced copy optimization.
This patch is a step toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov r0, r1, d16
but it does not understand yet
vmov.32 d16[0], r0
vmov.32 d16[1], r1
Comming patches will fix that and update the related test case.
<rdar://problem/
12702965>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216136
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Yi Jiang [Wed, 20 Aug 2014 22:55:40 +0000 (22:55 +0000)]
New InstCombine pattern: (icmp ult/ule (A + C1), C3) | (icmp ult/ule (A + C2), C3) to (icmp ult/ule ((A & ~(C1 ^ C2)) + max(C1, C2)), C3) under certain condition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216135
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Alexey Samsonov [Wed, 20 Aug 2014 22:46:38 +0000 (22:46 +0000)]
Don't allow MCStreamer::EmitIntValue to output 0-byte integers.
It makes no sense and can hide bugs. In particular, it lead
to left shift by 64 bits, which is an undefined behavior,
properly reported by UBSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216134
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Quentin Colombet [Wed, 20 Aug 2014 22:16:19 +0000 (22:16 +0000)]
[ARM] Mark VMOVRRD with the ExtractSubreg property and implement the related
target hook.
This patch teaches the compiler that:
rX, rY = VMOVRRD dZ
is the same as:
rX = EXTRACT_SUBREG dZ, ssub_0
rY = EXTRACT_SUBREG dZ, ssub_1
<rdar://problem/
12702965>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216132
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Alexey Samsonov [Wed, 20 Aug 2014 21:56:43 +0000 (21:56 +0000)]
Fix undefined behavior (left shift of negative value) in SystemZ backend.
This bug is reported by UBSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216131
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Quentin Colombet [Wed, 20 Aug 2014 21:51:26 +0000 (21:51 +0000)]
Add isExtractSubreg property.
This patch adds a new property: isExtractSubreg and the related target hooks:
TargetIntrInfo::getExtractSubregInputs and
TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific
instruction is a (kind of) EXTRACT_SUBREG.
The approach is similar to r215394.
<rdar://problem/
12702965>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216130
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Alexey Samsonov [Wed, 20 Aug 2014 21:40:15 +0000 (21:40 +0000)]
Fix null reference creation in SelectionDAG constructor.
Store TargetSelectionDAGInfo as a pointer instead of a reference:
getSelectionDAGInfo() may not be implemented for certain backends
(e.g. it's not currently implemented for R600).
This bug is reported by UBSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216129
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Alexey Samsonov [Wed, 20 Aug 2014 21:22:03 +0000 (21:22 +0000)]
Fix undefined behavior (left shift of negative value) in Hexagon backend.
This bug is reported by UBSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216125
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Alexey Samsonov [Wed, 20 Aug 2014 20:57:26 +0000 (20:57 +0000)]
Cleanup: Delete seemingly unused reference to MachineDominatorTree from ScheduleDAGInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216124
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Sanjay Patel [Wed, 20 Aug 2014 20:34:56 +0000 (20:34 +0000)]
Don't prevent a vselect of constants from becoming a single load (PR20648).
Fix for PR20648 - http://llvm.org/bugs/show_bug.cgi?id=20648
This patch checks the operands of a vselect to see if all values are constants.
If yes, bail out of any further attempts to create a blend or shuffle because
SelectionDAGLegalize knows how to turn this kind of vselect into a single load.
This already happens for machines without SSE4.1, so the added checks just send
more targets down that path.
Differential Revision: http://reviews.llvm.org/D4934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216121
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Duncan P. N. Exon Smith [Wed, 20 Aug 2014 19:58:59 +0000 (19:58 +0000)]
X86: Add missing triples from r216119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216120
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Duncan P. N. Exon Smith [Wed, 20 Aug 2014 19:40:59 +0000 (19:40 +0000)]
X86: Align the stack on word boundaries in LowerFormalArguments()
The goal of the patch is to implement section 3.2.3 of the AMD64 ABI
correctly. The controlling sentence is, "The size of each argument gets
rounded up to eightbytes. Therefore the stack will always be eightbyte
aligned." The equivalent sentence in the i386 ABI page 37 says, "At all
times, the stack pointer should point to a word-aligned area." For both
architectures, the stack pointer is not being rounded up to the nearest
eightbyte or word between the last normal argument and the first
variadic argument.
Patch by Thomas Jablin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216119
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Alexey Samsonov [Wed, 20 Aug 2014 19:36:05 +0000 (19:36 +0000)]
Fix null reference creation in ScheduleDAGInstrs constructor call.
Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI
constructor call. It is undefined behavior to take references to these values.
This bug is reported by UBSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216118
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Keno Fischer [Wed, 20 Aug 2014 19:00:37 +0000 (19:00 +0000)]
Do not insert a tail call when returning multiple values on X86
Summary: This fixes http://llvm.org/bugs/show_bug.cgi?id=19530.
The problem is that X86ISelLowering erroneously thought the third call
was eligible for tail call elimination.
It would have been if it's return value was actually the one returned
by the calling function, but here that is not the case and
additional values are being returned.
Test Plan: Test case from the original bug report is included.
Reviewers: rafael
Reviewed By: rafael
Subscribers: rafael, llvm-commits
Differential Revision: http://reviews.llvm.org/D4968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216117
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Alexey Samsonov [Wed, 20 Aug 2014 18:30:07 +0000 (18:30 +0000)]
Fix undefined behavior (left shift by 64 bits) in ScaledNumber::toString().
This bug is reported by UBSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216116
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Sanjay Patel [Wed, 20 Aug 2014 18:03:00 +0000 (18:03 +0000)]
critical-anti-dependency breaker: don't use reg def info from kill insts (PR20308)
In PR20308 ( http://llvm.org/bugs/show_bug.cgi?id=20308 ), the critical-anti-dependency breaker
caused a miscompile because it broke a WAR hazard using a register that it thinks is available
based on info from a kill inst. Until PR18663 is solved, we shouldn't use any def/use info from
a kill because they are really just nops.
This patch adds guard checks for kills around calls to ScanInstruction() where the DefIndices
array is set. For good measure, add an assert in ScanInstruction() so we don't hit this bug again.
The test case is a reduced version of the code from the bug report.
Differential Revision: http://reviews.llvm.org/D4977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216114
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Quentin Colombet [Wed, 20 Aug 2014 17:41:48 +0000 (17:41 +0000)]
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/
12702965>.
Review: http://reviews.llvm.org/D4874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216088
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Andrew Trick [Wed, 20 Aug 2014 17:38:12 +0000 (17:38 +0000)]
Tweak CFGPrinter to wrap very long names.
I added wrapping to the CFGPrinter a while back so the -view-cfg
output is actually viewable. I've since enountered very long mangled
names with the same problem, so I'm slightly tweaking this code to
work in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216087
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Rafael Espindola [Wed, 20 Aug 2014 17:33:44 +0000 (17:33 +0000)]
Remove unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216086
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Juergen Ributzka [Wed, 20 Aug 2014 16:34:15 +0000 (16:34 +0000)]
[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.
This fixes a bug I introduced in a previous commit (r216033). Sign-/Zero-
extension from i1 cannot be folded into the ADDS/SUBS instructions. Instead both
operands have to be sign-/zero-extended with separate instructions.
Related to <rdar://problem/
17913111>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216073
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Rafael Espindola [Wed, 20 Aug 2014 15:19:37 +0000 (15:19 +0000)]
Quick fix for an use after free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216071
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Dan Liew [Wed, 20 Aug 2014 15:06:30 +0000 (15:06 +0000)]
Add note to LangRef about how function arguments can be unnamed and
how this affects the numbering of unnamed temporaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216070
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Aaron Ballman [Wed, 20 Aug 2014 12:54:13 +0000 (12:54 +0000)]
Silencing a -Wcast-qual warning. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216068
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Aaron Ballman [Wed, 20 Aug 2014 12:14:35 +0000 (12:14 +0000)]
Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)). NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216067
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Jiangning Liu [Wed, 20 Aug 2014 12:05:15 +0000 (12:05 +0000)]
Optimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG Builder and type
legalization stage. With those two optimizations, fewer signed/zero extension
instructions can be inserted, and then we can expose more opportunities to
Machine CSE pass in back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216066
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Pavel Chupin [Wed, 20 Aug 2014 11:59:22 +0000 (11:59 +0000)]
[x32] Fix FrameIndex check in SelectLEA64_32Addr
Summary:
Fixes http://llvm.org/bugs/show_bug.cgi?id=20016 reproducible on new
lea-5.ll case.
Also use RSP/RBP for x32 lea to save 1 byte used for 0x67 prefix in
ESP/EBP case.
Test Plan: lea tests modified to include x32/nacl and new test added
Reviewers: nadav, dschuff, t.p.northover
Subscribers: llvm-commits, zinovy.nis
Differential Revision: http://reviews.llvm.org/D4929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216065
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Yi Kong [Wed, 20 Aug 2014 10:40:20 +0000 (10:40 +0000)]
ARM: Fix codegen for rbit intrinsic
LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic.
According to ARM ARM, rbit only takes register as argument, not immediate.
The correct instruction should be rbit <Rd>, <Rm>.
The bug was originally introduced in r211057.
Differential Revision: http://reviews.llvm.org/D4980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216064
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Bill Wendling [Wed, 20 Aug 2014 07:32:09 +0000 (07:32 +0000)]
Update projects lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216048
91177308-0d34-0410-b5e6-
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Bill Wendling [Wed, 20 Aug 2014 07:30:08 +0000 (07:30 +0000)]
Add libcxxabi to the projects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216047
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David Majnemer [Wed, 20 Aug 2014 07:17:31 +0000 (07:17 +0000)]
InstCombine: Annotate sub with nuw when we prove it's safe
We can prove that a 'sub' can be a 'sub nuw' if the left-hand side is
negative and the right-hand side is non-negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216045
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 20 Aug 2014 04:41:36 +0000 (04:41 +0000)]
Fix an off by 1 bug that prevented SmallPtrSet from using all of its 'small' capacity. Then fix the early return in the move constructor that prevented 'small' moves from clearing the NumElements in the moved from object. The directed test missed this because it was always testing large moves due to the off by 1 bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216044
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NAKAMURA Takumi [Wed, 20 Aug 2014 04:22:47 +0000 (04:22 +0000)]
Constants.h: Fix possible typo in r216015. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216043
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Peter Collingbourne [Wed, 20 Aug 2014 01:40:23 +0000 (01:40 +0000)]
[dfsan] Treat vararg custom functions like unimplemented functions.
Because declarations of these functions can appear in places like autoconf
checks, they have to be handled somehow, even though we do not support
vararg custom functions. We do so by printing a warning and calling the
uninstrumented function, as we do for unimplemented functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216042
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Juergen Ributzka [Wed, 20 Aug 2014 01:10:36 +0000 (01:10 +0000)]
[FastISel][AArch64] Use the proper FMOV instruction to materialize a +0.0.
Use FMOVWSr/FMOVXDr instead of FMOVSr/FMOVDr, which have the proper register
class to be used with the zero register. This makes the MachineInstruction
verifier happy again.
This is related to <rdar://problem/
18027157>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216040
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David Majnemer [Tue, 19 Aug 2014 23:36:30 +0000 (23:36 +0000)]
InstCombine: Annotate sub with nsw when we prove it's safe
We can prove that a 'sub' can be a 'sub nsw' under certain conditions:
- The sign bits of the operands is the same.
- Both operands have more than 1 sign bit.
The subtraction cannot be a signed overflow in either case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216037
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Hans Wennborg [Tue, 19 Aug 2014 23:35:33 +0000 (23:35 +0000)]
BumpPtrAllocator: don't accept 0 for the alignment parameter
It seems unnecessary to have to use an extra branch to check for this special case.
http://reviews.llvm.org/D4945
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216036
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Juergen Ributzka [Tue, 19 Aug 2014 22:29:55 +0000 (22:29 +0000)]
[FastISel][AArch64] Factor out ADDS/SUBS instruction emission and add support for extensions and shift folding.
Factor out the ADDS/SUBS instruction emission code into helper functions and
make the helper functions more clever to support most of the different ADDS/SUBS
instructions the architecture support. This includes better immedediate support,
shift folding, and sign-/zero-extend folding.
This fixes <rdar://problem/
17913111>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216033
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Rafael Espindola [Tue, 19 Aug 2014 22:05:47 +0000 (22:05 +0000)]
Split parseAssembly into parseAssembly and parseAssemblyInto.
This should restore the functionality of parsing new code into an existing
module without the confusing interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216031
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Alexey Samsonov [Tue, 19 Aug 2014 21:51:08 +0000 (21:51 +0000)]
Delete unused argument in AArch64MCInstLower constructor: it doesn't
use Mangler, and Mangler is in fact not even created when AArch64MCInstLower
is constructed.
This bug is reported by UBSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216030
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 21:48:04 +0000 (21:48 +0000)]
LangRef: Move example of function-scope uselistorder to a function
Should make the example added in r216025 a little more clear.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216027
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 21:30:15 +0000 (21:30 +0000)]
IR: Implement uselistorder assembly directives
Implement `uselistorder` and `uselistorder_bb` assembly directives,
which allow the use-list order to be recovered when round-tripping to
assembly.
This is the bulk of PR20515.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216025
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Lang Hames [Tue, 19 Aug 2014 21:26:36 +0000 (21:26 +0000)]
[MCJIT] Add an i386 RuntimeDyldMachO test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216024
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 21:18:21 +0000 (21:18 +0000)]
IR: Fix a missed case when threading OnlyIfReduced through ConstantExpr
In r216015 I missed propagating `OnlyIfReduced` through the inline
versions of `getGetElementPtr()` (I was relying on compile failures on
mismatches between the header and source signatures to get them all).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216023
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 21:08:27 +0000 (21:08 +0000)]
verify-uselistorder: Force -preserve-bc-use-list-order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216022
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Juergen Ributzka [Tue, 19 Aug 2014 20:35:07 +0000 (20:35 +0000)]
[FastISel][AArch64] Extend floating-point materialization test.
This adds the missing test that I promised for r215753 to test the
materialization of the floating-point value +0.0.
Related to <rdar://problem/
18027157>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216019
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Rafael Espindola [Tue, 19 Aug 2014 20:06:25 +0000 (20:06 +0000)]
fix the gcc build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216018
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Lang Hames [Tue, 19 Aug 2014 20:04:45 +0000 (20:04 +0000)]
[MCJIT] Allow '$' characters in symbol names in RuntimeDyldChecker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216017
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 20:03:35 +0000 (20:03 +0000)]
IR: Fix ConstantExpr::replaceUsesOfWithOnConstant()
Change `ConstantExpr` to follow the model the other constants are using:
only malloc a replacement if it's going to be used. This fixes a subtle
bug where if an API user had used `ConstantExpr::get()` already to
create the replacement but hadn't given it any users, we'd delete the
replacement.
This relies on r216015 to thread `OnlyIfReduced` through
`ConstantExpr::getWithOperands()`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216016
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 19:45:37 +0000 (19:45 +0000)]
IR: Thread OnlyIfReduced through ConstantExpr::getWithOperands()
In order to change `ConstantExpr::replaceUsesOfWithOnConstant()` to work
like other constants (e.g., using `ConstantArray::getImpl()`), thread
`OnlyIfReduced` through as necessary. When `OnlyIfReduced` is false,
there's no functionality change. When it's true, if there's no constant
folding or type changes `nullptr` is returned instead of the new
constant.
`ConstantExpr::replaceUsesOfWithOnConstant()` will be updated to use the
"true" version in a follow-up commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216015
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Rafael Espindola [Tue, 19 Aug 2014 19:45:15 +0000 (19:45 +0000)]
Fix the MSVC build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216014
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Juergen Ributzka [Tue, 19 Aug 2014 19:44:17 +0000 (19:44 +0000)]
Reapply [FastISel][AArch64] Add support for more addressing modes (r215597).
Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.
Original commit message:
FastISel didn't take much advantage of the different addressing modes available
to it on AArch64. This commit allows the ComputeAddress method to recognize more
addressing modes that allows shifts and sign-/zero-extensions to be folded into
the memory operation itself.
For Example:
lsl x1, x1, #3 --> ldr x0, [x0, x1, lsl #3]
ldr x0, [x0, x1]
sxtw x1, w1
lsl x1, x1, #3 --> ldr x0, [x0, x1, sxtw #3]
ldr x0, [x0, x1]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216013
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Juergen Ributzka [Tue, 19 Aug 2014 19:44:13 +0000 (19:44 +0000)]
Reapply [FastISel][X86] Add large code model support for materializing floating-point constants (r215595).
Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.
Original commit message:
In the large code model for X86 floating-point constants are placed in the
constant pool and materialized by loading from it. Since the constant pool
could be far away, a PC relative load might not work. Therefore we first
materialize the address of the constant pool with a movabsq and then load
from there the floating-point value.
Fixes <rdar://problem/
17674628>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216012
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Juergen Ributzka [Tue, 19 Aug 2014 19:44:10 +0000 (19:44 +0000)]
Reapply [FastISel][X86] Use XOR to materialize the "0" value (r215594).
Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216011
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Juergen Ributzka [Tue, 19 Aug 2014 19:44:06 +0000 (19:44 +0000)]
Reapply [FastISel][X86] Emit more efficient instructions for integer constant materialization (r215593).
Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.
Original commit message:
This mostly affects the i64 value type, which always resulted in an 15byte
mobavsq instruction to materialize any constant. The custom code checks the
value of the immediate and tries to use a different and smaller mov
instruction when possible.
This fixes <rdar://problem/
17420988>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216010
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Juergen Ributzka [Tue, 19 Aug 2014 19:44:02 +0000 (19:44 +0000)]
Reapply [FastISel][AArch64] Make use of the zero register when possible (r215591).
Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.
Original commit message:
This change materializes now the value "0" from the zero register.
The zero register can be folded by several instruction, so no
materialization is need at all.
Fixes <rdar://problem/
17924413>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216009
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 19:18:46 +0000 (19:18 +0000)]
ADT: Unit test for ArrayRef::equals change in r215986
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216008
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 19:13:30 +0000 (19:13 +0000)]
IR: De-duplicate code for replacing operands in place
This is non-trivial and sits in three places. Move it to
ConstantUniqueMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216007
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Juergen Ributzka [Tue, 19 Aug 2014 19:05:24 +0000 (19:05 +0000)]
Reapply [FastISel] Let the target decide first if it wants to materialize a constant (215588).
Note: This was originally reverted to track down a buildbot error. This commit
exposed a latent bug that was fixed in r215753. Therefore it is reapplied
without any modifications.
I run it through SPEC2k and SPEC2k6 for AArch64 and it didn't introduce any new
regeressions.
Original commit message:
This changes the order in which FastISel tries to materialize a constant.
Originally it would try to use a simple target-independent approach, which
can lead to the generation of inefficient code.
On X86 this would result in the use of movabsq to materialize any 64bit
integer constant - even for simple and small values such as 0 and 1. Also
some very funny floating-point materialization could be observed too.
On AArch64 it would materialize the constant 0 in a register even the
architecture has an actual "zero" register.
On ARM it would generate unnecessary mov instructions or not use mvn.
This change simply changes the order and always asks the target first if it
likes to materialize the constant. This doesn't fix all the issues
mentioned above, but it enables the targets to implement such
optimizations.
Related to <rdar://problem/
17420988>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216006
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Rafael Espindola [Tue, 19 Aug 2014 18:59:14 +0000 (18:59 +0000)]
Fix a pair of use after free. Should bring the bots back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216005
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Rafael Espindola [Tue, 19 Aug 2014 18:44:46 +0000 (18:44 +0000)]
Don't own the buffer in object::Binary.
Owning the buffer is somewhat inflexible. Some Binaries have sub Binaries
(like Archive) and we had to create dummy buffers just to handle that. It is
also a bad fit for IRObjectFile where the Module wants to own the buffer too.
Keeping this ownership would make supporting IR inside native objects
particularly painful.
This patch focuses in lib/Object. If something elsewhere used to own an Binary,
now it also owns a MemoryBuffer.
This patch introduces a few new types.
* MemoryBufferRef. This is just a pair of StringRefs for the data and name.
This is to MemoryBuffer as StringRef is to std::string.
* OwningBinary. A combination of Binary and a MemoryBuffer. This is needed
for convenience functions that take a filename and return both the
buffer and the Binary using that buffer.
The C api now uses OwningBinary to avoid any change in semantics. I will start
a new thread to see if we want to change it and how.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216002
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Alexey Samsonov [Tue, 19 Aug 2014 18:40:39 +0000 (18:40 +0000)]
Hide two different AlignMode enums in anonymous namespaces. This bug is reported by UBSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216001
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Renato Golin [Tue, 19 Aug 2014 18:08:50 +0000 (18:08 +0000)]
Revert "Small refactor on VectorizerHint for deduplication"
This reverts commit r215994 because MSVC 2012 can't cope with its C++11 goodness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215999
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Juergen Ributzka [Tue, 19 Aug 2014 17:41:53 +0000 (17:41 +0000)]
[FastISel][AArch64] Fix a few BuildMI callsites where the result register was added as an operand register.
This fixes a few BuildMI callsites where the result register was added by
using addReg, which is per default a use and therefore an operand register.
Also use the zero register as result register when emitting a compare
instruction (SUBS with unused result register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215997
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Renato Golin [Tue, 19 Aug 2014 17:30:43 +0000 (17:30 +0000)]
Small refactor on VectorizerHint for deduplication
Previously, the hint mechanism relied on clean up passes to remove redundant
metadata, which still showed up if running opt at low levels of optimization.
That also has shown that multiple nodes of the same type, but with different
values could still coexist, even if temporary, and cause confusion if the
next pass got the wrong value.
This patch makes sure that, if metadata already exists in a loop, the hint
mechanism will never append a new node, but always replace the existing one.
It also enhances the algorithm to cope with more metadata types in the future
by just adding a new type, not a lot of code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215994
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Alex Lorenz [Tue, 19 Aug 2014 17:05:58 +0000 (17:05 +0000)]
Docs: add documentation for the coverage mapping format.
Differential Revision: http://reviews.llvm.org/D4729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215990
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Rafael Espindola [Tue, 19 Aug 2014 16:58:54 +0000 (16:58 +0000)]
Modernize the .ll parsing interface.
* Use StringRef instead of std::string&
* Return a std::unique_ptr<Module> instead of taking an optional module to write
to (was not really used).
* Use current comment style.
* Use current naming convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215989
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 16:49:40 +0000 (16:49 +0000)]
CodingStandards: Document std::equal misbehaviour
I should have included this as part of r215986, which worked around this
corner by changing ArrayRef::equals() not to use std::equal. Alas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215988
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 16:39:58 +0000 (16:39 +0000)]
Reapply r215966, r215965, r215964, r215963, r215960, r215959, r215958, and r215957
This reverts commit r215981, which reverted the above commits because
MSVC std::equal asserts on nullptr iterators, and thes commits
introduced an `ArrayRef::equals()` on empty ArrayRefs.
ArrayRef was changed not to use std::equal in r215986.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215987
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Duncan P. N. Exon Smith [Tue, 19 Aug 2014 16:36:21 +0000 (16:36 +0000)]
ADT: Avoid using std::equal in ArrayRef::equals
MSVC's STL has a bug in `std::equal()`: it asserts on nullptr iterators,
causing a block revert in r215981. This works around that by re-writing
`ArrayRef::equals()` to do the work itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215986
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Aaron Ballman [Tue, 19 Aug 2014 14:59:02 +0000 (14:59 +0000)]
Reverting r215966, r215965, r215964, r215963, r215960, r215959, r215958, and r215957 (these commits all rely on previous commits) due to build breakage. These commits cause failed assertions when testing Clang using MSVC 2013. The asserts are triggered from the std::equal call within ArrayRef::equals due to being passed invalid input (ArrayRef.begin() is returning a nullptr which is problematic).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215981
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Toma Tabacu [Tue, 19 Aug 2014 14:22:52 +0000 (14:22 +0000)]
[mips] Add assembler support for .set arch=x directive.
Summary:
This directive is similar to ".set mipsX".
It is used to change the CPU target of the assembler, enabling it to accept instructions for a specific CPU.
This patch only implements the r4000 CPU (which is treated internally as generic mips3) and the generic ISAs.
Contains work done by Matheus Almeida.
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D4884
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215978
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Mayur Pandey [Tue, 19 Aug 2014 08:19:19 +0000 (08:19 +0000)]
InstCombine: ((A & ~B) ^ (~A & B)) to A ^ B
Proof using CVC3 follows:
$ cat t.cvc
A, B : BITVECTOR(32);
QUERY BVXOR((A & ~B),(~A & B)) = BVXOR(A,B);
$ cvc3 t.cvc
Valid.
Differential Revision: http://reviews.llvm.org/D4898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215974
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Craig Topper [Tue, 19 Aug 2014 07:44:27 +0000 (07:44 +0000)]
Const-correct and prevent a copy of a SmallPtrSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215973
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 19 Aug 2014 06:57:14 +0000 (06:57 +0000)]
Prevent use of the implicit copy constructor on SmallPtrSetImpl. An accidental copy caused my SmallPtrSet->SmallPtrSetImpl conversion commit to fail the other day.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215971
91177308-0d34-0410-b5e6-
96231b3b80d8
Mayur Pandey [Tue, 19 Aug 2014 06:41:55 +0000 (06:41 +0000)]
test commit (spelling correction)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215970
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Tue, 19 Aug 2014 04:04:25 +0000 (04:04 +0000)]
Make it explicit that ExecutionEngine takes ownership of the modules.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215967
91177308-0d34-0410-b5e6-
96231b3b80d8