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Martin Storsjo [Tue, 8 May 2018 08:47:37 +0000 (08:47 +0000)]
[llvm-rc] Don't strictly require quotes around external file names
Regardless of what docs may say, existing resource files in the
wild can use this syntax.
Rename a file used in an existing test, to make it usable for unquoted
paths.
Differential Revision: https://reviews.llvm.org/D46511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331747
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Hans Wennborg [Tue, 8 May 2018 08:22:58 +0000 (08:22 +0000)]
Object: Find terminator correctly when reading long filenames in GNU archives (PR37244)
The code was previously relying on there being a null terminator
somewhere in (or after) the string table, something made less likely by
r330786.
Differential Revision: https://reviews.llvm.org/D46527
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331746
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Gabor Buella [Tue, 8 May 2018 07:11:05 +0000 (07:11 +0000)]
[x86] Introduce the enclv instruction
Summary:
and use the -msgx flag as a requirement
for the SGX instructions.
Reviewers: craig.topper, zvi
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D46436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331742
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Bjorn Pettersson [Tue, 8 May 2018 06:59:47 +0000 (06:59 +0000)]
[LCSSA] Do not remove used PHI nodes in formLCSSAForInstructions
Summary:
In formLCSSAForInstructions we speculatively add new PHI
nodes, that sometimes ends up without having any uses. It
has been discovered that sometimes an added PHI node can
appear as being unused in one iteration of the Worklist,
although it can end up being used by a PHI node added in
a later iteration. We now check, a second time, that the
PHI node still is unused before we remove it. This avoids
an assert about "Trying to remove a phi with uses." for the
added test case.
Reviewers: davide, mzolotukhin, mattd, dberlin
Reviewed By: mzolotukhin, dberlin
Subscribers: dberlin, mzolotukhin, davide, bjope, uabelho, llvm-commits
Differential Revision: https://reviews.llvm.org/D46422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331741
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Gabor Buella [Tue, 8 May 2018 06:47:36 +0000 (06:47 +0000)]
[x86] Introduce the pconfig instruction
Reviewers: craig.topper, zvi
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D46430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331739
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Fangrui Song [Tue, 8 May 2018 06:21:12 +0000 (06:21 +0000)]
[DebugInfo] Accept `S` in augmentation strings in CIE.
glibc libc.a(sigaction.o) compiled from sysdeps/unix/sysv/linux/x86_64/sigaction.c uses "zRS".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331738
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Roman Tereshin [Tue, 8 May 2018 02:48:15 +0000 (02:48 +0000)]
[MachineVerifier][GlobalISel] Verifying generic extends and truncates
Making sure we don't truncate / extend pointers, don't try to change
vector topology or bitcast vectors to scalars or back, and most
importantly, don't extend to a smaller type or truncate to a large
one.
Reviewers: qcolombet t.p.northover aditya_nandakumar
Reviewed By: qcolombet
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D46490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331718
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Roman Tereshin [Tue, 8 May 2018 02:02:50 +0000 (02:02 +0000)]
[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)
MIParser wasn't able to parse LLTs like `<4 x p0>`, fixing that.
Reviewers: qcolombet t.p.northover aditya_nandakumar
Reviewed By: qcolombet
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D46490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331712
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Teresa Johnson [Tue, 8 May 2018 01:45:46 +0000 (01:45 +0000)]
[NewPM] Emit inliner NoDefinition missed optimization remark
Summary: Makes this consistent with the old PM.
Reviewers: eraman
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D46526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331709
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Sam Clegg [Tue, 8 May 2018 00:08:21 +0000 (00:08 +0000)]
[WebAssembly] MC: Use existing MCSymbol.Index field rather than inventing extra mapping
MCSymbol has getIndex/setIndex which are implementation defined
and on other platforms are used to store the symbol table
index. It makes sense to use this rather than invent a new
mapping.
Differential Revision: https://reviews.llvm.org/D46555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331705
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Sam Clegg [Mon, 7 May 2018 23:52:17 +0000 (23:52 +0000)]
[MC] ELFObjectWriter: Removing unneeded variable and cast
Differential Revision: https://reviews.llvm.org/D46289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331704
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Chandler Carruth [Mon, 7 May 2018 23:41:48 +0000 (23:41 +0000)]
Revert r330742: Let TableGen write output only if it changed, instead of doing so in cmake.
This change causes us to re-run tablegen for every single target on
every single build. This is much, much worse than the problem being
fixed AFAICT.
On my system, it makes a clean rebuild of `llc` with nothing changed go
from .5s to over 8s. On systems with less parallelism, slower file
systems, or high process startup overhead this will be even more
extreme.
The only way I see this could be a win is in clean builds where we churn
the filesystem. But I think incremental rebuild is more important, and
so if we want to re-instate this, it needs to be done in a way that
doesn't trigger constant re-runs of tablegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331702
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Roman Tereshin [Mon, 7 May 2018 23:14:00 +0000 (23:14 +0000)]
Follow Up on [MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring visitMachineInstrBefore
Fixing accidentally broken CodeGen/X86/verifier-generic-types-1.mir test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331695
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Roman Tereshin [Mon, 7 May 2018 22:31:47 +0000 (22:31 +0000)]
[MachineVerifier][GlobalISel] Checking that generic instrs have LLTs on all vregs
Every generic machine instruction must have generic virtual registers
only, that is, have a low-level type attached to each operand.
Previously MachineVerifier would catch a type missing on an operand
only if the previous operand for the the same type index exists and
have a type attached to it and it will report it as a type mismatch.
This is incosistent behaviour and a misleading error message.
This commit makes sure MachineVerifier explicitly checks that the
types are there for every operand and if not provides a
straightforward error message.
Reviewers: qcolombet t.p.northover bogner ab
Reviewed By: qcolombet
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D46455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331694
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Roman Tereshin [Mon, 7 May 2018 22:31:12 +0000 (22:31 +0000)]
[MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring visitMachineInstrBefore
This is an NFC pre-commit for the following "Checking that generic
instrs have LLTs on all vregs" commit.
This overloads MachineOperand::print to make it possible to print LLTs
with standalone machine operands.
This also overloads MachineVerifier::print(...MachineOperand...) with
an optional LLT using the newly introduced MachineOperand::print
variant; no actual calls added.
This also refactors MachineVerifier::visitMachineInstrBefore in the
parts dealing with all generic instructions (checking Selected
property, LLTs, and phys regs).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331693
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Tom Stellard [Mon, 7 May 2018 22:17:54 +0000 (22:17 +0000)]
AMDGPU/GlobalISel: Don't try to lower hull shaders
Summary: The AMDGPU_HS calling convention is not supported yet.
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331691
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Alexander Shaposhnikov [Mon, 7 May 2018 22:00:59 +0000 (22:00 +0000)]
[tools] Add missing test dependency
Caught by the build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331687
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Roman Lebedev [Mon, 7 May 2018 21:52:22 +0000 (21:52 +0000)]
[DAGCombiner] Masked merge: enhance handling of 'andn' with immediates
Summary:
Split off from D46031.
The previous patch, D46493, completely disabled unfolding in case of immediates.
But we can do better:
{
F6120274} {
F6120277}
https://rise4fun.com/Alive/xJS
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: andreadb, llvm-commits
Differential Revision: https://reviews.llvm.org/D46494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331685
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Roman Lebedev [Mon, 7 May 2018 21:52:11 +0000 (21:52 +0000)]
[DagCombiner] Not all 'andn''s work with immediates.
Summary:
Split off from D46031.
In masked merge case, this degrades IPC by decreasing instruction count.
{
F6108777}
The next patch should be able to recover and improve this.
This also affects the transform @spatel have added in D27489 / rL289738,
and the test coverage for X86 was missing.
But after i have added it, and looked at the changes in MCA, i'm somewhat confused.
{
F6093591} {
F6093592} {
F6093593}
I'd say this regression is an improvement, since `IPC` increased in that case?
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: andreadb, llvm-commits, spatel
Differential Revision: https://reviews.llvm.org/D46493
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331684
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Dmitry Mikulin [Mon, 7 May 2018 21:30:15 +0000 (21:30 +0000)]
Remove explicit setting of the CFI jumptable section name, it does not appear
to be needed: jump table sections are created with .cfi.jumptable suffix. With
this change each jump table is placed in a separate section, which allows the
linker to re-order them.
Differential Revision: https://reviews.llvm.org/D46537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331680
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Simon Pilgrim [Mon, 7 May 2018 21:10:48 +0000 (21:10 +0000)]
[llvm-mca][x86] Remove addsubpd from SSE2 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331678
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Alexander Shaposhnikov [Mon, 7 May 2018 21:07:01 +0000 (21:07 +0000)]
[tools] Adjust the lit config for llvm-strip
Caught by the build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331676
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Roman Lebedev [Mon, 7 May 2018 21:06:53 +0000 (21:06 +0000)]
[llvm-rc] Fix build: missing 'override'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331675
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Simon Pilgrim [Mon, 7 May 2018 20:52:53 +0000 (20:52 +0000)]
[X86] Split WriteFAdd/WriteFCmp/WriteFMul schedule classes
Split to support single/double for scalar, XMM and YMM/ZMM instructions - removing InstrRW overrides for these instructions.
Fixes Atom ADDSUBPD instruction and reclassifies VFPCLASS as WriteFCmp which is closer in behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331672
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Martin Storsjo [Mon, 7 May 2018 20:27:37 +0000 (20:27 +0000)]
[llvm-rc] Implement the BITMAP resource type
Differential Revision: https://reviews.llvm.org/D46509
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331670
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Martin Storsjo [Mon, 7 May 2018 20:27:28 +0000 (20:27 +0000)]
[llvm-rc] Allow optional commas between the string table index and value
This form is even used in one of the examples at
https://msdn.microsoft.com/en-us/library/windows/desktop/
aa381050(v=vs.85).aspx.
Differential Revision: https://reviews.llvm.org/D46508
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331669
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Martin Storsjo [Mon, 7 May 2018 20:27:23 +0000 (20:27 +0000)]
[llvm-rc] Exclude padding from sizes in versioninfo resources
Normally when writing something that requires padding, we first
measure the length of the written payload data, then write
padding if necessary.
For a recursive structure like versioninfo, this means that the
padding is excluded from the size of the inner element, but
included in the size of the enclosing block.
Rc.exe excludes the final padding (but not the padding of earlier
children) from all levels of the hierarchy.
To achieve this, don't pad after each block or value, but only
before starting the next one. We still pad after completing the
toplevel versioninfo resource, so this won't affect other resource
types.
Differential Revision: https://reviews.llvm.org/D46510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331668
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Martin Storsjo [Mon, 7 May 2018 20:27:15 +0000 (20:27 +0000)]
[llvm-rc] Fix alphabetical order of cases. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331667
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Aaron Smith [Mon, 7 May 2018 20:15:50 +0000 (20:15 +0000)]
[SelectionDAG] Transfer DbgValues when casts are optimized in SelectionDAG::getNode
Summary:
getNode optimizes (ext (trunc x)) to x and the dbgvalue node on trunc is lost. The fix calls transferDbgValues to add the dbgvalue to x.
Add DebugInfo/AArch64/dbg-value-i16.ll
Patch by Sejong Oh!
Reviewers: aprantl, javed.absar, llvm-commits, vsk
Reviewed By: aprantl, vsk
Subscribers: kristof.beyls, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D46348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331665
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Sam Clegg [Mon, 7 May 2018 19:40:50 +0000 (19:40 +0000)]
[WebAssembly] Ensure all .debug_XXX section has proper symbol names
Updated wasm section symbols names to match section name, and ensure all
referenced sections will have a symbol (per DWARF spec v3, Figure 43)
Patch by Yury Delendik!
Differential Revision: https://reviews.llvm.org/D46543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331664
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Alexander Shaposhnikov [Mon, 7 May 2018 19:32:09 +0000 (19:32 +0000)]
[tools] Introduce llvm-strip
llvm-strip is supposed to be a drop-in replacement for binutils strip.
To start the ball rolling this diff adds the initial bits for llvm-strip,
more features will be added incrementally over time.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D46407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331663
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Matt Davis [Mon, 7 May 2018 18:29:15 +0000 (18:29 +0000)]
[llvm-mca] Avoid exposing index values in the MCA interfaces.
Summary:
This patch eliminates many places where we originally needed to pass index
values to represent an instruction. The index is still used as a key, in various parts of
MCA. I'm not comfortable eliminating the index just yet. By burying the index in
the instruction, we can avoid exposing that value in many places.
Eventually, we should consider removing the Instructions list in the Backend
all together, it's only used to hold and reclaim the memory for the allocated
Instruction instances. Instead we could pass around a smart pointer. But that's
a separate discussion/patch.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb
Subscribers: javed.absar, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331660
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Simon Pilgrim [Mon, 7 May 2018 18:25:19 +0000 (18:25 +0000)]
[X86][AVX2] Tag VPMOVSX/VPMOVZX ymm instructions as WriteShuffle256
These are more like cross-lane shuffles than regular shuffles - we already do this for AVX512 equivalents.
Differential Revision: https://reviews.llvm.org/D46229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331659
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Krzysztof Parzyszek [Mon, 7 May 2018 17:34:23 +0000 (17:34 +0000)]
[Hexagon] Move clamping of extended operands directly to MC code emitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331653
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Roman Lebedev [Mon, 7 May 2018 16:42:47 +0000 (16:42 +0000)]
[DAGCombine][NFC] Masked merge unfolding: comment: some tests are non-canonical
As requested in https://reviews.llvm.org/D46494#inline-407282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331650
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Simon Pilgrim [Mon, 7 May 2018 16:34:26 +0000 (16:34 +0000)]
[X86][Znver1] Remove WriteFMul/WriteFRcp InstRW overrides/aliases.
Fixes x87 schedules to more closely match Agner - AMD doesn't tend to "special case" x87 instructions as much as Intel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331645
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Simon Pilgrim [Mon, 7 May 2018 16:15:46 +0000 (16:15 +0000)]
[X86] Split WriteFDiv schedule classes to support single/double scalar, XMM and YMM/ZMM instructions.
This removes all InstrRW overrides for these instructions - some x87 overrides remain but most use default (and realistic) values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331643
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Mark Searles [Mon, 7 May 2018 14:43:28 +0000 (14:43 +0000)]
[AMDGPU][Waitcnt] Remove the old waitcnt pass
Remove the old waitcnt pass ( si-insert-waits ), which is no longer maintained
and getting crufty
Differential Revision: https://reviews.llvm.org/D46448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331641
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Petar Jovanovic [Mon, 7 May 2018 14:09:33 +0000 (14:09 +0000)]
Add option -verify-cfiinstrs to run verifier in CFIInstrInserter
Instead of enabling it for non NDEBUG builds, use -verify-cfiinstrs to
run verifier in CFIInstrInserter. It defaults to false.
Differential Revision: https://reviews.llvm.org/D46444
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331635
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Clement Courbet [Mon, 7 May 2018 13:26:47 +0000 (13:26 +0000)]
[NFC] Fix typo in variable name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331634
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Tim Renouf [Mon, 7 May 2018 13:21:26 +0000 (13:21 +0000)]
[AMDGPU] Don't force WQM for DS op
Summary:
Previously, all DS ops forced WQM in a pixel shader. That was a hack to
allow for graphics frontends using ds_swizzle to implement explicit
derivatives, on SI/CI at least where DPP is not available. But it forced
WQM for _any_ DS op.
With this commit, DS ops no longer force WQM. Both graphics frontends
(Mesa and LLPC) need to change to issue an explicit llvm.amdgcn.wqm
intrinsic call when calculating explicit derivatives.
The required Mesa change is: "amd/common: use llvm.amdgcn.wqm for
explicit derivatives".
Subscribers: qcolombet, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46051
Change-Id: I9b745b626fa91bbd66456e6cf41ee07eeea42f81
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331633
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Simon Pilgrim [Mon, 7 May 2018 11:50:44 +0000 (11:50 +0000)]
[X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classes
WriteFRcp/WriteFRsqrt are split to support scalar, XMM and YMM/ZMM instructions.
WriteFSqrt is split into single/double/long-double sizes and scalar, XMM, YMM and ZMM instructions.
This removes all InstrRW overrides for these instructions.
NOTE: There were a couple of typos in the Znver1 model - notably a 1cy throughput for SQRT that is highly unlikely and doesn't tally with Agner.
NOTE: I had to add Agner's numbers for several targets for WriteFSqrt80.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331629
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Petar Jovanovic [Mon, 7 May 2018 11:47:48 +0000 (11:47 +0000)]
Skip unreachable blocks for CFIInstrInserter verify
Iterate only through reachable blocks. This finetunes r330706 and
it resolves build issue reported by Craig Topper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331628
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Jonas Paulsson [Mon, 7 May 2018 10:48:43 +0000 (10:48 +0000)]
[SystemZ] Bugfix for MVCLoop CC clobbering.
MVCLoop clobbers CC (since it emits a compare/branch), but this was not
modelled.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331627
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Roman Lebedev [Mon, 7 May 2018 09:42:45 +0000 (09:42 +0000)]
[InstCombine][NFC] Add tests for one more masked merge pattern.
This pattern came up in D46494.
I'm pretty sure we want to canonicalize it from
(x | ~m) & (y & m)
to
(x & m) | (y & ~m)
https://rise4fun.com/Alive/TEM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331625
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Clement Courbet [Mon, 7 May 2018 09:09:48 +0000 (09:09 +0000)]
Re-land r331622 "[llvm-exegesis] Add a library to cluster benchmark results."
Add missing move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331624
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Clement Courbet [Mon, 7 May 2018 08:30:18 +0000 (08:30 +0000)]
Revert r331622 "[llvm-exegesis] Add a library to cluster benchmark results."
Breaks build over llvm::Error copy construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331623
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Clement Courbet [Mon, 7 May 2018 08:20:00 +0000 (08:20 +0000)]
[llvm-exegesis] Add a library to cluster benchmark results.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D46432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331622
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Fangrui Song [Mon, 7 May 2018 05:21:20 +0000 (05:21 +0000)]
Fix comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331615
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Amaury Sechet [Mon, 7 May 2018 01:43:42 +0000 (01:43 +0000)]
[ARM] Select result 1 from ConvertBooleanCarryToCarryFlag's result automatically. NFC
The old behavior return the value 0, which is error prone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331614
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Craig Topper [Mon, 7 May 2018 01:32:18 +0000 (01:32 +0000)]
[TargetLowering] Use StringRef::split instead of SplitString. NFC
SplitString splits based on a list of delimeters, but we're only using one delimeter so we should use the simpler split.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331613
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Craig Topper [Mon, 7 May 2018 00:47:02 +0000 (00:47 +0000)]
[X86] Fix copy/paste mistake in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331611
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Fangrui Song [Sun, 6 May 2018 23:08:29 +0000 (23:08 +0000)]
[llvm-dwp] Define InitLLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331610
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Roman Lebedev [Sun, 6 May 2018 20:02:22 +0000 (20:02 +0000)]
[NFC][DAGCombine] unfoldMaskedMerge(): rename two variables
The current names can be confused with the A and B sides
of the canonical masked merge pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331609
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Craig Topper [Sun, 6 May 2018 17:48:21 +0000 (17:48 +0000)]
[X86] Enable reciprocal estimates for v16f32 vectors by using VRCP14PS/VRSQRT14PS
Summary:
The legacy VRCPPS/VRSQRTPS instructions aren't available in 512-bit versions. The new increased precision versions are. So we can use those to implement v16f32 reciprocal estimates.
For KNL CPUs we can probably use VRCP28PS/VRSQRT28PS and avoid the NR step altogether, but I leave that for a future patch.
Reviewers: spatel
Reviewed By: spatel
Subscribers: RKSimon, llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D46498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331606
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Craig Topper [Sun, 6 May 2018 17:45:40 +0000 (17:45 +0000)]
[X86] Add test cases for reciprocal estimation for v16f32 vectors with AVX512F.
We should be able to use the vrsqrt14ps and vrcp14ps instructions for these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331605
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Amaury Sechet [Sun, 6 May 2018 16:00:23 +0000 (16:00 +0000)]
Add test cases for large integer legalization of add and sub. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331604
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Daniel Sanders [Sat, 5 May 2018 21:19:59 +0000 (21:19 +0000)]
[globalisel] Remove redundant -global-isel option from tests that use -run-pass. NFC
As Roman Tereshin pointed out in https://reviews.llvm.org/D45541, the
-global-isel option is redundant when -run-pass is given. -global-isel sets up
the GlobalISel passes in the pass manager but -run-pass skips that entirely and
configures it's own pipeline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331603
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Fangrui Song [Sat, 5 May 2018 20:54:03 +0000 (20:54 +0000)]
[MC] Remove unused MCOI::GenericOperandType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331602
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Daniel Sanders [Sat, 5 May 2018 20:53:24 +0000 (20:53 +0000)]
[globalisel] Update GlobalISel emitter to match new representation of extending loads
Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
improve optimization of extends and truncates, this legality requirement
would spread without considerable care w.r.t when certain combines were
permitted.
* The SelectionDAG importer required some ugly and fragile pattern
rewriting to translate patterns into this style.
This patch changes the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.
Each extending load can be lowered by the legalizer into separate extends
and loads, however a target that supports s1 will need the any-extending
load to extend to at least s8 since LLVM does not represent memory accesses
smaller than 8 bit. The legalizer can widenScalar G_LOAD into an
any-extending load but sign/zero-extending loads need help from something
else like a combiner pass. A follow-up patch that adds combiner helpers for
for this will follow.
The new representation requires that the MMO correctly reflect the memory
access so this has been corrected in a couple tests. I've also moved the
extending loads to their own tests since they are (mostly) separate opcodes
now. Additionally, the re-write appears to have invalidated two tests from
select-with-no-legality-check.mir since the matcher table no longer contains
loads that result in s1's and they aren't legal in AArch64 anymore.
Depends on D45540
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar
Reviewed By: rtereshin
Subscribers: javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331601
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Heejin Ahn [Sat, 5 May 2018 20:53:23 +0000 (20:53 +0000)]
[MIRPraser] Improve error checking for typed immediate operands
Summary:
This improves error checks for typed immediate operands introduced in
D45948 (rL331586), and removes a code block copied by mistake.
Reviewers: rtereshin
Subscribers: dschuff, sbc100, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D46491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331600
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Fangrui Song [Sat, 5 May 2018 20:14:38 +0000 (20:14 +0000)]
Simplify LLVM_ATTRIBUTE_USED call sites.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331599
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Roman Lebedev [Sat, 5 May 2018 15:45:40 +0000 (15:45 +0000)]
[DAGCombiner] Masked merge: don't touch "not" xor's.
Summary:
Split off form D46031.
It seems we don't want to transform the pattern if the `xor`'s are actually `not`'s.
In vector case, this breaks `andnpd` / `vandnps` patterns.
That being said, we may want to re-visit this `not` handling, maybe in D46073.
Reviewers: spatel, craig.topper, javed.absar
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46492
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331595
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Andrea Di Biagio [Sat, 5 May 2018 15:36:47 +0000 (15:36 +0000)]
[llvm-mca] removes flag -instruction-tables from the "View Options" category.
This patch also improves the description of a couple of flags in the view
options. With this change, the -help now specifies which views are enabled by
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331594
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Teresa Johnson [Sat, 5 May 2018 14:37:20 +0000 (14:37 +0000)]
[LTO] Handle Task=-1 passed to addSaveTemps
Summary:
This change is necessary for D46464, which will pass -1 as the Task
ID for distributed backends, so that the save temps files don't end
up with "
4294967295" in their path. For distributed back ends, when -1
is passed, don't append any Task ID.
An existing test (tools/clang/test/CodeGen/thinlto_backend.ll) will
fail without this change after D46464.
Reviewers: pcc
Subscribers: mehdi_amini, inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D46488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331591
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Andrea Di Biagio [Sat, 5 May 2018 12:21:54 +0000 (12:21 +0000)]
[llvm-mca] minor tweak to the resource pressure printing functionality. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331590
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Roman Lebedev [Sat, 5 May 2018 10:39:54 +0000 (10:39 +0000)]
[NFC][DagCombiner] unfoldMaskedMerge(): improve readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331588
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Piotr Padlewski [Sat, 5 May 2018 10:23:27 +0000 (10:23 +0000)]
[CaptureTracking] Handle capturing of launder.invariant.group
Summary:
launder.invariant.group has the same rules of capturing as
bitcast, gep, etc - the original value is not captured
if the returned pointer is not captured.
With this patch, we mark 40% more functions as noalias when compiling with -fstrict-vtable-pointers;
1078 vs 1778 (39.37%)
Reviewers: sanjoy, davide, nlewycky, majnemer, mehdi_amini
Subscribers: JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D32673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331587
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Heejin Ahn [Sat, 5 May 2018 07:05:51 +0000 (07:05 +0000)]
[MIRParser] Allow register class names in the form of integer/scalar
Summary:
The current code cannot handle register class names like 'i32', which is
a valid register class name in WebAssembly. This patch removes special
handling for integer/scalar/pointer type parsing and treats them as
normal identifiers.
Reviewers: thegameg
Subscribers: jfb, dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D45948
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331586
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Fangrui Song [Sat, 5 May 2018 06:05:31 +0000 (06:05 +0000)]
[Option] Remove an unnecessary conversion function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331585
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George Burgess IV [Sat, 5 May 2018 04:52:26 +0000 (04:52 +0000)]
Range-ify for loop; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331582
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Tom Stellard [Sat, 5 May 2018 02:52:41 +0000 (02:52 +0000)]
GlobalISel/InstructionSelector: Implement GIR_CopyFConstantAsFPImm
Summary: AMDGPU will need this to enable the TableGen'd GlobalISel selector.
Reviewers: dsanders, aditya_nandakumar
Reviewed By: dsanders
Subscribers: rovka, kristof.beyls, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D45990
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331579
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Craig Topper [Sat, 5 May 2018 01:57:00 +0000 (01:57 +0000)]
Fix a bunch of places where operator-> was used directly on the return from dyn_cast.
Inspired by r331508, I did a grep and found these.
Mostly just change from dyn_cast to cast. Some cases also showed a dyn_cast result being converted to bool, so those I changed to isa.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331577
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Peter Collingbourne [Sat, 5 May 2018 00:51:55 +0000 (00:51 +0000)]
LowerTypeTests: Fix non-determinism in code that handles icall branch funnels.
This was exposed by enabling expensive checks, which causes llvm::sort
to sort randomly.
Differential Revision: https://reviews.llvm.org/D45901
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331573
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Teresa Johnson [Fri, 4 May 2018 23:59:34 +0000 (23:59 +0000)]
[LTO] Allow pass remarks with hotness to be set when emitting to stderr
Summary:
Set setDiagnosticsHotnessRequested before the early exit check for a
diagnostic output file, so that pass remarks with hotness works when
emitting pass remarks to stderr (e.g. via -pass-remarks=.).
Also fix the llvm-lto2 diagnistic handler so that it only calls exit(1)
when the diagnistic is an error type. Otherwise the new test invocation
of llvm-lto2 with -pass-remarks causes it to fail. The new code is
consistent with the diagnostic handler elsewhere (e.g. on the
LLVMContext).
Reviewers: pcc, davide
Subscribers: fhahn, mehdi_amini, llvm-commits, inglorion
Differential Revision: https://reviews.llvm.org/D46387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331569
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Davide Italiano [Fri, 4 May 2018 23:41:25 +0000 (23:41 +0000)]
[llvm-mc-assemble-fuzzer] Catch up with API changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331568
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Michael Berg [Fri, 4 May 2018 23:41:15 +0000 (23:41 +0000)]
Mapping SDNode flags to MachineInstr flags
Summary: Providing the glue to map SDNode fast math sub flags to MachineInstr fast math sub flags.
Reviewers: spatel, arsenm, wristow
Reviewed By: spatel
Subscribers: wdng
Differential Revision: https://reviews.llvm.org/D46447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331567
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Konstantin Zhuravlyov [Fri, 4 May 2018 22:53:55 +0000 (22:53 +0000)]
AMDGPU/NFC: Update D16PreservesUnusedBits description based Tony Tye's comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331564
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Philip Reames [Fri, 4 May 2018 21:35:00 +0000 (21:35 +0000)]
[LICM] Compute a must execute property for the prefix of the header as we go
Computing this property within the existing walk ensures that the cost is linear with the size of the block. If we did this from within isGuaranteedToExecute, it would be quadratic without some very fancy caching.
This allows us to reliably catch a hoistable instruction within a header which may throw at some point *after* our hoistable instruction. It doesn't do anything for non-header cases, but given how common single block loops are, this seems very worthwhile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331557
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Konstantin Zhuravlyov [Fri, 4 May 2018 20:21:31 +0000 (20:21 +0000)]
AMDGPU/NFC: Fix formatting for 900, 902 ISA Version features
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331553
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Konstantin Zhuravlyov [Fri, 4 May 2018 20:06:57 +0000 (20:06 +0000)]
AMDGPU: Add D16 instructions preserve unused bits feature
- Predicate D16 patterns on this new feature
- Added this new feature to gfx900/2/4
Differential Revision: https://reviews.llvm.org/D46366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331551
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Geoff Berry [Fri, 4 May 2018 19:25:09 +0000 (19:25 +0000)]
[MachineLICM] Debug intrinsics shouldn't affect hoist decisions
Summary:
When checking if an instruction stores to a given frame index, check
that the instruction can write to memory before looking at the memory
operands list to avoid e.g. DBG_VALUE instructions that reference a
frame index preventing a load from that index from being hoisted.
Reviewers: dblaikie, MatzeB, qcolombet, reames, javed.absar
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D46284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331549
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Shoaib Meenai [Fri, 4 May 2018 19:03:11 +0000 (19:03 +0000)]
[ObjCARC] Account for catchswitch in bitcast insertion
A catchswitch is both a pad and a terminator, meaning it must be the
only non-phi instruction in its basic block. When we're inserting a
bitcast in the incoming basic block for a phi, if that incoming block is
a catchswitch, we should go up the dominator tree to find a valid
insertion point rather than attempting to insert before the catchswitch
(which would result in invalid IR).
Differential Revision: https://reviews.llvm.org/D46412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331548
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Michael Berg [Fri, 4 May 2018 18:48:20 +0000 (18:48 +0000)]
Fast Math Flag mapping into SDNode
Summary: Adding support for Fast flags in the SDNode to leverage fast math sub flag usage.
Reviewers: spatel, arsenm, jbhateja, hfinkel, escha, qcolombet, echristo, wristow, javed.absar
Reviewed By: spatel
Subscribers: llvm-commits, rampitec, nhaehnle, tstellar, FarhanaAleen, nemanjai, javed.absar, jbhateja, hfinkel, wdng
Differential Revision: https://reviews.llvm.org/D45710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331547
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Simon Pilgrim [Fri, 4 May 2018 18:16:13 +0000 (18:16 +0000)]
[X86] Add WriteEMMS scheduler class
Filled in the missing values from Btver2 SoG or Agner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331546
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Simon Pilgrim [Fri, 4 May 2018 17:47:46 +0000 (17:47 +0000)]
[X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331543
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Craig Topper [Fri, 4 May 2018 17:39:08 +0000 (17:39 +0000)]
[LoopIdiomRecognize] Don't create an IRBuilder just to call getTrue/getFalse.
We can call the methods in ConstantInt directly. We just need a context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331542
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Adhemerval Zanella [Fri, 4 May 2018 17:21:26 +0000 (17:21 +0000)]
[AArch64] Add missing testcase for r331522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331541
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Matt Davis [Fri, 4 May 2018 17:19:40 +0000 (17:19 +0000)]
[llvm-mca] Add descriptive names for the TimelineView report characters. NFC.
Summary:
This change makes the TimelineView source simpler to read and easier to modify in the future.
This patch introduces a class of static chars used as the display values in the TimelineView report, this change just eliminates a few magic characters.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb
Subscribers: tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331540
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Peter Collingbourne [Fri, 4 May 2018 16:45:57 +0000 (16:45 +0000)]
Object: The default alignment of a section without alignment flags is 16.
Differential Revision: https://reviews.llvm.org/D46420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331538
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Peter Collingbourne [Fri, 4 May 2018 16:28:41 +0000 (16:28 +0000)]
obj2yaml: Correctly round-trip default alignment.
Previously we were emitting the "cooked" alignment, which made it hard
to distinguish between that and the default alignment.
Differential Revision: https://reviews.llvm.org/D46418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331537
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Adrian Prantl [Fri, 4 May 2018 16:10:43 +0000 (16:10 +0000)]
DwarfCompileUnit: Fix another assertion failure on malformed input
that is not rejected by the Verifier.
Thanks to Björn Pettersson for providing a reproducer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331535
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Clement Courbet [Fri, 4 May 2018 15:26:12 +0000 (15:26 +0000)]
[llvm-exegesis] Fix pfm counter names for BDW.
Summary: They are not consistent with other microarchitectures.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D46434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331532
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Simon Pilgrim [Fri, 4 May 2018 15:20:18 +0000 (15:20 +0000)]
[X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.
Rename scalar and XMM versions, this is to match/simplify an upcoming change to split MUL/DIV/SQRT scalar/xmm/ymm/zmm classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331531
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David Bolvansky [Fri, 4 May 2018 15:14:00 +0000 (15:14 +0000)]
[bindings/go] Add Go bindings for volatile loads/stores
Reviewers: whitequark
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331530
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Krzysztof Parzyszek [Fri, 4 May 2018 15:07:30 +0000 (15:07 +0000)]
[Hexagon] Remove leftover debugging code after r331527
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331528
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Krzysztof Parzyszek [Fri, 4 May 2018 15:04:48 +0000 (15:04 +0000)]
[Hexagon] Handle non-immediate constants in HexagonSplitDouble
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331527
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Simon Dardis [Fri, 4 May 2018 15:00:54 +0000 (15:00 +0000)]
[mips] Correct the predicates of sign extension instructions
And eliminatw the duplication of those instructions for microMIPS32r6.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D46117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331526
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Simon Pilgrim [Fri, 4 May 2018 14:54:33 +0000 (14:54 +0000)]
[X86] Add WriteVecMOVMSKY scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331525
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Adhemerval Zanella [Fri, 4 May 2018 14:33:55 +0000 (14:33 +0000)]
[AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32
This patch adds a custom lowering for ISD::MULH{S,U} used on divide by
constant optimization (DAGCombiner::BuildSDIV and DAGCombiner::BuildUDIV).
New patterns for smull and umull are added, so AArch64ISD::{S,U}MULL
can be correctly lowered to smull2 and umull2.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331522
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