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Kenneth Graunke [Wed, 10 Feb 2016 00:16:00 +0000 (16:16 -0800)]
i965: Make brw_clear_cache flag all the bits on both pipelines.
Setting brw->ctx.NewDriverState and brw->ctx.NewGLState affects
the dirty bits for the current pipeline. But, we need to flag
everything dirty on *both* pipelines, so that when we switch
back, we'll realize our programs are stale and re-upload them.
To accomplish this, flag the saved state for both pipelines.
Only one of them should matter, but this way we don't have to
check which we need to set. It's harmless to set the other.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Iglesias Gonsálvez [Thu, 11 Feb 2016 06:15:50 +0000 (07:15 +0100)]
glsl: Allow invariant qualifer in block members in desktop OpenGL.
Feedback from Khronos is that 'invariant' should be allowed on block
members for desktop OpenGL. Fix piglit regression added by
fe1e89a0:
invariant-qualifier-in-out-block-01.vert
v2:
- Allow it for in/out blocks in OpenGL ES too, so when OES_shader_io_blocks
is supported we don't need to do any change (Timothy)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89330
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Wed, 10 Feb 2016 00:11:55 +0000 (16:11 -0800)]
i965: Consider tessellation in get_pipeline_state_l3_weights.
I think this was just missed; Curro and I were probably writing
code simultaneously and forgot to combine them at the end.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Wed, 10 Feb 2016 00:08:18 +0000 (16:08 -0800)]
i965: Split brw_upload_texture_surfaces into compute/render atoms.
When uploading state for the compute pipeline, we don't want to
look at VS/TCS/TES/GS/FS programs, as they might be stale, and
aren't relevant anyway. Likewise, the render pipeline shouldn't
look at CS.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Marek Olšák [Thu, 11 Feb 2016 16:49:39 +0000 (17:49 +0100)]
radeonsi: fix build with LLVM 3.6
Broken by this cleanup:
3dc1cb0cc7605a2f3128311f5a6052f740fc7b0d
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jason Ekstrand [Thu, 11 Feb 2016 05:57:52 +0000 (21:57 -0800)]
i965/gs: Pass VerticesIn though prog_data
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 11 Feb 2016 05:27:57 +0000 (21:27 -0800)]
i965/fs: Pass usage of depth, W, and sample mask through prog_data
We really need to stop pulling information directly out of shaders for
state setup. For one thing, if we want any sort of an on-disk shader
cache, having all of this metadata in one place is going to be crucial.
Also, passing it all through prog_data cleans up the compiler <-> state
setup API substantially.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 11 Feb 2016 05:20:01 +0000 (21:20 -0800)]
i965/fs: Refactor setup_payload_gen6 to assume FS
It's extremely FS specific so the fact that we have a stage check in the
middle of it is rather bogus. While were here, we rename
setup_payload_gen4 and setup_payload_gen6 to make it obvious that they are
both FS specific.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Pitoiset [Thu, 11 Feb 2016 22:05:04 +0000 (23:05 +0100)]
nv50,nvc0: remove unused parameter in nvXX_state_validate()
This 'words' parameter is there since 2011 but it has never been used.
While we are at it, get rid of the extern declaration.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Timothy Arceri [Thu, 11 Feb 2016 04:14:21 +0000 (15:14 +1100)]
glsl: don't validate interface blocks twice
We already check for opaque types so don't recheck for atomics
and images.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Timothy Arceri [Thu, 11 Feb 2016 04:45:05 +0000 (15:45 +1100)]
glsl: remove duplicate embedded struct validation
Commit
c98deb18d5836f in 2010 disallowed embedded struct definitions
in ES. Then in 2013
d9bb8b7b56ce65b disallowed it for everything but
GLSL 1.10.
Commit
c98deb18d5836f seemed the cleanest way to do the check so its
been extended to cover GL and the other version has been removed.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jose Fonseca [Thu, 11 Feb 2016 11:36:17 +0000 (11:36 +0000)]
include,gallium: Remove pre-MSVC 2013 compatibility.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Thu, 11 Feb 2016 11:07:49 +0000 (11:07 +0000)]
scons: Eliminate MSVC2008 compatibility.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Thu, 11 Feb 2016 11:07:33 +0000 (11:07 +0000)]
configure: Eliminate MSVC2008 compatibility.
We no longer need to build any part of Mesa with Windows SDK 7.0.7600 or
MSVC 2008. MSVC 2013 will be the oldest we support.
In practice this means people are now free to declare variables in the
middle of blocks, on the whole Mesa tree.
Care should still be taken with variable length arrays and void pointer
arithmetic.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Hella-acked-by: Ian Romanick <ian.d.romanick@intel.com>
Chris Forbes [Thu, 11 Feb 2016 06:03:56 +0000 (19:03 +1300)]
i965: ir: dump floats as %-g rather than %f, so we can see denormals
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Jordan Justen [Wed, 10 Feb 2016 17:56:23 +0000 (09:56 -0800)]
i965/gen7: Require kernel cmd_parser 5 for ARB_compute_shader
The indirect dispatch registers were whitelisted in command parser
version 5. (Version 5 is available as of Linux 4.4)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Mon, 5 Oct 2015 21:18:18 +0000 (23:18 +0200)]
st/mesa: release GLSL IR in LinkShader after it's not needed
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Mon, 5 Oct 2015 21:15:59 +0000 (23:15 +0200)]
mesa: call build_program_resource_list inside Driver.LinkShader
to allow LinkShader to free the GLSL IR.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Thu, 11 Feb 2016 15:40:54 +0000 (16:40 +0100)]
st/mesa: use correct pipe functions to create tess shaders
Broken by one of my cleanups. Spotted by luck.
Radeonsi doesn't care, because all shader create callbacks go to the same
function.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 10 Feb 2016 20:48:59 +0000 (21:48 +0100)]
gallium/radeon: drop support for LLVM 3.5
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
v2: adjust the comment in the amdgpu winsys
Marek Olšák [Wed, 10 Feb 2016 20:27:55 +0000 (21:27 +0100)]
radeonsi: obtain commonly used LLVM types only once
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 10 Feb 2016 19:31:26 +0000 (20:31 +0100)]
radeonsi: cleanup shader codegen
si_shader_ctx -> ctx
type * ptr -> type *ptr
si_shader_context *shader -> si_shader_context *ctx
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Feb 2016 14:49:51 +0000 (15:49 +0100)]
radeonsi: fix a crash when binding a sampler buffer
Buffers don't contain r600_texture.
Broken by
7aedbbacae6d3ec3d06735fff2eb66:
"radeonsi: put image, fmask, and sampler descriptors into one array"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94091
Emil Velikov [Thu, 11 Feb 2016 01:47:07 +0000 (01:47 +0000)]
docs: add news item and link release notes for 11.1.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 11 Feb 2016 01:21:31 +0000 (01:21 +0000)]
docs: add sha256 checksums for 11.1.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
e49dd21bcbabdb330620d48f5915828cfd5eb983)
Emil Velikov [Thu, 11 Feb 2016 00:03:22 +0000 (00:03 +0000)]
docs: add release notes for 11.1.2
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
7bcd827806b0816d61122ba3d37dd40178d96d98)
Jason Ekstrand [Tue, 9 Feb 2016 22:51:28 +0000 (14:51 -0800)]
nir: Remove the const_offset from nir_tex_instr
When NIR was originally drafted, there was no easy way to determine if
something was constant or not. The result was that we had lots of
special-casing for constant values such as this. Now that load_const
instructions are SSA-only, it's really easy to find constants and this
isn't really needed anymore.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rob Clark <robclark@gmail.com>
Jason Ekstrand [Wed, 10 Feb 2016 20:07:49 +0000 (12:07 -0800)]
nir/lower_vec_to_movs: Better report channels handled by insert_mov
This fixes two issues. First, we had a use-after-free in the case where
the instruction got deleted and we tried to return mov->dest.write_mask.
Second, in the case where we are doing a self-mov of a register, we delete
those channels that are moved to themselves from the write-mask. This
means that those channels aren't reported as being handled even though they
are. We now stash off the write-mask before remove unneeded channels so
that they still get reported as handled.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94073
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Marek Olšák [Sun, 24 Jan 2016 00:06:07 +0000 (01:06 +0100)]
radeonsi: don't emit unnecessary NULL exports for unbound targets (v3)
v2: remove semantic index == 0 checks
add the else statement to remove shadowing of args
v3: fix fbo-alphatest-nocolor regression
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v2)
Ben Widawsky [Sun, 7 Feb 2016 02:11:21 +0000 (18:11 -0800)]
i965: Make sure we blit a full compressed block
This fixes an assertion failure in [at least] one of the Unreal Engine Linux
demo/games that uses DXT1 compression. Specifically, the "Vehicle Game".
At some point, the game ends up trying to blit mip level whose size is 2x2,
which is smaller than a DXT1 block. As a result, the assertion in the blit path
is triggered. It should be safe to simply make sure we align the width and
height, which is sadly an example of compression being less efficient.
NOTE: The demo seems to work fine without the assert, and therefore release
builds of mesa wouldn't stumble over this. Perhaps there is some unnoticeable
corruption, but I had trouble spotting it.
Thanks to Jason for looking at my backtrace and figuring out what was going on.
v2: Use NPOT alignment to make sure ASTC is handled properly (Ilia)
Remove comment about how this doesn't fix other bugs, because it does.
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93358
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Tested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Marek Olšák [Wed, 10 Feb 2016 19:15:07 +0000 (20:15 +0100)]
radeon/uvd: silence a warning
Marek Olšák [Wed, 10 Feb 2016 19:14:53 +0000 (20:14 +0100)]
r300g: silence warnings
Ian Romanick [Thu, 12 Nov 2015 17:37:27 +0000 (09:37 -0800)]
meta/decompress: Don't pollute the renderbuffer namespace
tl;dr: For many types of GL object, we can *NEVER* use the Gen function.
In OpenGL ES (all versions!) and OpenGL compatibility profile,
applications don't have to call Gen functions. The GL spec is very
clear about how you can mix-and-match generated names and non-generated
names: you can use any name you want for a particular object type until
you call the Gen function for that object type.
Here's the problem scenario:
- Application calls a meta function that generates a name. The first
Gen will probably return 1.
- Application decides to use the same name for an object of the same
type without calling Gen. Many demo programs use names 1, 2, 3,
etc. without calling Gen.
- Application calls the meta function again, and the meta function
replaces the data. The application's data is lost, and the app
fails. Have fun debugging that.
Fixes piglit 'object-namespace-pollution glGetTexImage-compressed
renderbuffer' test.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92363
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Thu, 12 Nov 2015 17:29:34 +0000 (09:29 -0800)]
meta: Use internal functions for renderbuffer access
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Thu, 12 Nov 2015 17:26:41 +0000 (09:26 -0800)]
meta/decompress: Track renderbuffer using gl_renderbuffer instead of GL API object handle
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Thu, 12 Nov 2015 02:05:09 +0000 (18:05 -0800)]
i965/meta: Don't pollute the renderbuffer namespace
tl;dr: For many types of GL object, we can *NEVER* use the Gen function.
In OpenGL ES (all versions!) and OpenGL compatibility profile,
applications don't have to call Gen functions. The GL spec is very
clear about how you can mix-and-match generated names and non-generated
names: you can use any name you want for a particular object type until
you call the Gen function for that object type.
Here's the problem scenario:
- Application calls a meta function that generates a name. The first
Gen will probably return 1.
- Application decides to use the same name for an object of the same
type without calling Gen. Many demo programs use names 1, 2, 3,
etc. without calling Gen.
- Application calls the meta function again, and the meta function
replaces the data. The application's data is lost, and the app
fails. Have fun debugging that.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92363
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Thu, 12 Nov 2015 00:35:05 +0000 (16:35 -0800)]
i965/meta: Use internal functions for renderbuffer access
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Wed, 11 Nov 2015 23:57:25 +0000 (15:57 -0800)]
i965/meta: Return struct gl_renderbuffer* from brw_get_rb_for_slice instead of GL API handle
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Wed, 11 Nov 2015 22:34:11 +0000 (14:34 -0800)]
meta: Don't save or restore the renderbuffer binding
Nothing left in meta does anything with the RBO binding, so we don't
need to save or restore it. The FBO binding is still modified.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Wed, 11 Nov 2015 22:33:30 +0000 (14:33 -0800)]
meta: Use _mesa_CreateRenderbuffers instead of _mesa_GenRenderbuffers and _mesa_BindRenderbuffer
This has the advantage that it does not pollute the global binding
state. It also enables later patches that will stop calling
_mesa_GenRenderbuffers / _mesa_CreateRenderbuffers which pollute the
renderbuffer namespace.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Wed, 11 Nov 2015 22:29:18 +0000 (14:29 -0800)]
i965/meta: Use _mesa_CreateRenderbuffers instead of _mesa_GenRenderbuffers and _mesa_BindRenderbuffer
This has the advantage that it does not pollute the global binding
state. It also enables later patches that will stop calling
_mesa_GenRenderbuffers / _mesa_CreateRenderbuffers which pollute the
renderbuffer namespace.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Thu, 12 Nov 2015 17:11:20 +0000 (09:11 -0800)]
mesa: Refactor renderbuffer_storage to make _mesa_renderbuffer_storage
Pulls the parts of renderbuffer_storage that aren't just parameter
validation out into a function that can be called from other parts of
Mesa (e.g., meta).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Thu, 12 Nov 2015 00:30:41 +0000 (16:30 -0800)]
mesa: Refactor _mesa_framebuffer_renderbuffer
This function previously was only used in fbobject.c and contained a
bunch of API validation. Split the function into
framebuffer_renderbuffer that is static and contains the validation, and
_mesa_framebuffer_renderbuffer that is suitable for calling from
elsewhere in Mesa (e.g., meta).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Marek Olšák [Sat, 6 Feb 2016 21:09:45 +0000 (22:09 +0100)]
radeonsi: put image, fmask, and sampler descriptors into one array
The texture slot is expanded to 16 dwords containing 2 descriptors.
Those can be:
- Image and fmask, or
- Image and sampler state
By carefully choosing the locations, we can put all three into one slot,
with the fmask and sampler state being mutually exclusive.
This improves shaders in 2 ways:
- 2 user SGPRs are unused, shaders can use them as temporary registers now
- each pair of descriptors is always on the same cache line
v2: cosmetic changes: add back v8i32, don't load a sampler state & fmask
at the same time
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 10 Feb 2016 18:41:37 +0000 (19:41 +0100)]
winsys/radeon: fix the num_tile_pipes comment to silence warnings
Alexandre Demers [Wed, 10 Feb 2016 14:45:46 +0000 (09:45 -0500)]
winsys/radeon: better explain the num_tile_pipes fixup for TAHITI (v2)
v2: Clarify the relation between num_tiles_pipes and GB_TILE_MODE and the fix
needed for Tahiti as suggested by Marek.
Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Tue, 9 Feb 2016 10:40:08 +0000 (11:40 +0100)]
st/mesa: check ureg_create() retval in create_pbo_upload_vs()
This avoids a possible NULL dereference because ureg_create() might
return a NULL pointer.
Spotted by coverity.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Bernhard Rosenkränzer [Wed, 10 Feb 2016 16:19:46 +0000 (17:19 +0100)]
freedreno/ir3: Get rid of nested functions
This allows building Freedreno with clang
Signed-off-by: Bernhard Rosenkränzer <bero@linaro.org>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Chris Forbes [Tue, 18 Nov 2014 08:49:53 +0000 (21:49 +1300)]
i965/blorp: Fix hiz ops on MSAA surfaces
Two things were broken here:
- The depth/stencil surface dimensions were broken for MSAA.
- Sample count was programmed incorrectly.
Result was the depth resolve didn't work correctly on MSAA surfaces, and
so sampling the surface later produced garbage.
Fixes the new piglit test arb_texture_multisample-sample-depth, and
various artifacts in 'tesseract' with msaa=4 glineardepth=0.
Fixes freedesktop bug #76396.
Not observed any piglit regressions on Haswell.
v2: Just set brw_hiz_op_params::dst.num_samples rather than adding a
helper function (Ken).
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
v3: moved the alignment needed for hiz+msaa to brw_blorp.cpp, as
suggested by Chad Versace (Alejandro Piñeiro on behalf of Chris
Forbes)
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Topi Pohjolainen [Sun, 3 Jan 2016 13:06:09 +0000 (15:06 +0200)]
i965/gen8: Remove dead assertion
The assertion is inside a condition mandating num_samples > 1 and
therefore the first half of the constraint is always met. The
second half in turn would only be applicable for single sampled
case and moreover it is trying to falsely check against surface
type instead of format.
Subsequent patches will introduce proper support for the lossless
compression and dropping this here makes the patches a little
simpler.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Topi Pohjolainen [Mon, 7 Dec 2015 19:58:33 +0000 (21:58 +0200)]
i965: Use constant pointer when checking for compression
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Brian Paul [Wed, 10 Feb 2016 03:09:26 +0000 (20:09 -0700)]
mesa: fix trivial comment typo in dlist.c
Kenneth Graunke [Thu, 14 Jan 2016 04:33:17 +0000 (20:33 -0800)]
i965/vec4: Drop support for ATTR as an instruction destination.
This is no longer necessary...and it doesn't make much sense to
have inputs as destinations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Thu, 14 Jan 2016 04:33:16 +0000 (20:33 -0800)]
i965/vec4/gs: Stop munging the ATTR containing gl_PointSize.
gl_PointSize is delivered in the .w component of the VUE header, while
the language expects it to be a float (and thus in the .x component).
Previously, we emitted MOVs to copy it over to the .x component.
But this is silly - we can just use a .wwww swizzle and access it
without copying anything or clobbering the value stored at .x
(which admittedly is useless).
Removes the last use of ATTR destinations.
v2: Use BRW_SWIZZLE_WWWW, not SWIZZLE_WWWW (caught by GCC).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Thu, 14 Jan 2016 04:33:15 +0000 (20:33 -0800)]
i965: Apply VS attribute workarounds in NIR.
This patch re-implements the pre-Haswell VS attribute workarounds.
Instead of emitting shader code in the vec4 backend, we now simply
call a NIR pass to emit the necessary code.
This simplifies the vec4 backend. Beyond deleting code, it removes
the primary use of ATTR as a destination. It also eliminates the
requirement that the vec4 VS backend express the ATTR file in terms
of VERT_ATTRIB_* locations, giving us a bit more flexibility.
This approach is a little different: rather than munging the attributes
at the top, we emit code to fix them up when they're accessed. However,
we run the optimizer afterwards, so CSE should eliminate the redundant
math. It may even be able to fuse it with other calculations based on
the input value.
shader-db does not handle non-default NOS settings, so I have no
statistics about this patch.
Note that the scalar backend does not implement VS attribute
workarounds, as they are unnecessary on hardware which allows SIMD8 VS.
v2: Do one multiply for FIXED rescaling and select components from
either the original or scaled copy, rather than multiplying each
component separately (suggested by Matt Turner).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Brian Paul [Tue, 9 Feb 2016 21:44:54 +0000 (14:44 -0700)]
st/mesa: clarify some texture target code in st_cb_drawpix.c
Use st->internal_target instead of PIPE_TEXTURE_2D when choosing the
texture format. Probably no real difference, but let's be consistent.
Simplify a test when determining whether we need normalized texcoords.
Add a new assertion.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 9 Feb 2016 21:35:31 +0000 (14:35 -0700)]
st/mesa: fix bitmap texture target code and simplify tex sampler state
Bitmaps may be drawn with a PIPE_TEXTURE_2D or PIPE_TEXTURE_RECT resource
as determined at context creation by checking if PIPE_CAP_NPOT_TEXTURES is
supported. But many places in the bitmap code were hard-coded to use
PIPE_TEXTURE_2D. Use st->internal_target instead.
I think an older NV chip is the only case where a gallium driver does not
support NPOT textures. Bitmap drawing was probably broken for that GPU.
Also, we only need one sampler state with texcoord normalization set up
according to st->internal_target.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 9 Feb 2016 21:20:41 +0000 (14:20 -0700)]
st/mesa: use MAX3() macro, as we do for sampler view code below
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 9 Feb 2016 21:19:25 +0000 (14:19 -0700)]
st/mesa: move some st_cb_drawpixels.c code, add comments
Nanley Chery [Sat, 6 Feb 2016 00:25:28 +0000 (16:25 -0800)]
mesa/readpix: Dedent former _mesa_readpixels() if block
Formatting patch split out for easy reviewing.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Nanley Chery [Sat, 6 Feb 2016 00:25:01 +0000 (16:25 -0800)]
mesa/readpix: Don't clip in _mesa_readpixels()
The clipping is performed higher up in the call-chain.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Nanley Chery [Sat, 6 Feb 2016 00:21:33 +0000 (16:21 -0800)]
mesa/readpix: Clip ReadPixels() area to the ReadBuffer's
The fast path for Intel's ReadPixels() unintentionally omits clipping
the specified area to a valid one. Rather than clip in various
corner-cases, perform this operation in the API validation stage.
The bug in intel_readpixels_tiled_memcpy() showed itself when the winsys
ReadBuffer's height was smaller than the one specified by ReadPixels().
yoffset became negative, which was an invalid input for tiled_to_linear().
v2: Move clipping to validation stage (Jason)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92193
Reported-by: Marta Löfstedt <marta.lofstedt@intel.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Nanley Chery [Sat, 6 Feb 2016 00:20:01 +0000 (16:20 -0800)]
mesa/image: Make _mesa_clip_readpixels() work with renderbuffers
v2: Use gl_renderbuffer::{Width,Height} (Jason)
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Jason Ekstrand [Tue, 3 Nov 2015 02:39:17 +0000 (18:39 -0800)]
i965/vec4: Plumb separate surfaces and samplers through from NIR
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 3 Nov 2015 02:28:49 +0000 (18:28 -0800)]
i965/vec4: Separate the sampler from the surface in generate_tex
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Sat, 6 Feb 2016 02:24:02 +0000 (18:24 -0800)]
i965/fs: Plumb separate surfaces and samplers through from NIR
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Mon, 2 Nov 2015 23:24:05 +0000 (15:24 -0800)]
i965/fs: Separate the sampler from the surface in generate_tex
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Sat, 6 Feb 2016 02:39:13 +0000 (18:39 -0800)]
i965/fs: Add an enum for keeping track of texture instruciton sources
These logical texture instructions can have a *lot* of sources. It's much
safer if we have symbolic names for them.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 3 Nov 2015 01:58:29 +0000 (17:58 -0800)]
nir: Separate texture from sampler in nir_tex_instr
This commit adds the capability to NIR to support separate textures and
samplers. As it currently stands, glsl_to_nir only sets the texture deref
and leaves the sampler deref alone as it did before and nir_lower_samplers
assumes this. Backends can still assume that they are combined and only
look at only at the texture index. Or, if they wish, they can assume that
they are separate because nir_lower_samplers, tgsi_to_nir, and prog_to_nir
all set both texture and sampler index whenever a sampler is required (the
two indices are the same in this case).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Sat, 6 Feb 2016 17:05:10 +0000 (09:05 -0800)]
nir/tex_instr: Rename sampler to texture
We're about to separate the two concepts. When we do, the sampler will
become optional. Doing a rename first makes the separation a bit more
safe because drivers that depend on GLSL or TGSI behaviour will be fine to
just use the texture index all the time.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 9 Feb 2016 18:48:42 +0000 (10:48 -0800)]
nir: Add some braces around loops and ifs
Kenneth Graunke [Tue, 5 Jan 2016 09:53:57 +0000 (01:53 -0800)]
i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT.
Bit 0 of the Patch Header is "TR DS Cache Disable". Setting that bit
disables the DS Cache for tessellator-output topologies resulting in
stitch-transition regions (but leaves it enabled for other cases).
We probably shouldn't leave this to chance - the URB could contain
garbage - which could result in the cache randomly being turned on
or off.
This patch makes the final EOT write 0 to the first DWord (which
only contains this one bit). This ensures the cache is always on.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Rob Clark [Thu, 21 Jan 2016 20:15:56 +0000 (15:15 -0500)]
freedreno/ir3: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 21 Jan 2016 19:12:58 +0000 (14:12 -0500)]
nir: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Thu, 21 Jan 2016 18:49:07 +0000 (13:49 -0500)]
ptn: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Thu, 21 Jan 2016 18:36:37 +0000 (13:36 -0500)]
ttn: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Thu, 21 Jan 2016 18:32:37 +0000 (13:32 -0500)]
ttn: small logic cleanup
The only case where dim!=NULL is where op==load_ubo. But using
op==load_ubo is less confusing.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 21 Jan 2016 18:32:09 +0000 (13:32 -0500)]
gtn: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Wed, 13 Jan 2016 23:43:14 +0000 (18:43 -0500)]
nir: const_index helpers
Direct access to intr->const_index[n], where different slots have
different meanings, is somewhat confusing.
Instead, let's put some extra info in nir_intrinsic_infos[] about which
slots map to what, and add some get/set helpers. The helpers validate
that the field being accessed (base/writemask/etc) is applicable for the
intrinsic opc, for some extra safety. And nir_print can use this to
dump out decoded const_index fields.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 9 Feb 2016 10:12:07 +0000 (02:12 -0800)]
glsl: Disallow transform feedback varyings with compute shaders.
If the only stage is MESA_SHADER_COMPUTE, we should complain that
there's nothing coming out of the geometry shader stage just as
we would if the first stage were MESA_SHADER_FRAGMENT.
Also, it's valid for tessellation shaders to be the stage producing
transform feedback varyings, so mention those in the compiler error.
Found by inspection.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Marek Olšák [Fri, 5 Feb 2016 21:49:12 +0000 (22:49 +0100)]
radeonsi: enable denorms for 64-bit and 16-bit floats
This fixes FP16 conversion instructions for VI, which has 16-bit floats,
but not SI & CI, which can't disable denorms for those instructions.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 6 Feb 2016 16:13:07 +0000 (17:13 +0100)]
gallium: pass the robust buffer access context flag to drivers
radeonsi will not do bounds checking for loads if this is not set.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 6 Jan 2016 20:21:07 +0000 (21:21 +0100)]
gallium/radeon: add a function for adding llvm function attributes
This will be used for setting the new InitialPSInputAddr attribute.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Jan 2016 01:26:59 +0000 (02:26 +0100)]
radeonsi: compile geometry shaders immediately
they have only 1 variant
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Jan 2016 00:29:25 +0000 (01:29 +0100)]
radeonsi: split out code for deleting si_shader
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 16:07:29 +0000 (17:07 +0100)]
radeonsi: move code writing tess factors into a separate function
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 22:32:23 +0000 (23:32 +0100)]
radeonsi: make LLVM IR dumping less messy
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 21:39:24 +0000 (22:39 +0100)]
radeonsi: move a few r600_can_dump_shader calls to where they're needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 16:27:54 +0000 (17:27 +0100)]
radeonsi: remove useless code that handles dx10_clamp_mode
"enable-no-nans-fp-math" is a wrong string and there was a disagreement
about fixing it.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 21:16:55 +0000 (22:16 +0100)]
radeonsi: dump SPI_PS_INPUT values along with shader stats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 6 Jan 2016 15:03:38 +0000 (16:03 +0100)]
radeonsi: read SPI_PS_INPUT_ADDR from LLVM if it returns it
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 9 Jan 2016 13:33:38 +0000 (14:33 +0100)]
radeonsi: don't force gl_SampleMaskIn to 1 for smoothing
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jan 2016 23:41:43 +0000 (00:41 +0100)]
radeonsi: split PS input interpolation code into its own function
This will be used by the fragment shader prolog.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 3 Jan 2016 18:00:29 +0000 (19:00 +0100)]
radeonsi: implement forcing per-sample_interpolation using the shader key only
It was partly a state and partly emulated by shader code, but since we want
to do this in a fragment shader prolog, we need to put it into the shader
key, which will be used to generate the prolog.
This also removes the spi_ps_input states and moves the registers
to the PS state.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 2 Jan 2016 02:18:03 +0000 (03:18 +0100)]
radeonsi: remove si_shader::ps_input_interpolate
tgsi_shader_info has this too.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 2 Jan 2016 01:54:29 +0000 (02:54 +0100)]
radeonsi: move BCOLOR PS input locations after all other inputs
BCOLOR inputs were immediately after COLOR inputs. Thus, all following inputs
were offset by 1 if color_two_side was enabled, and not offset if it was not
enabled, which is a variation that's problematic if we want to have 1 variant
per shader and the variant doesn't care about color_two_side (that should be
handled by other bytecode attached at the beginning).
Instead, move BCOLOR inputs after all other inputs, so BCOLOR0 is at location
"num_inputs" if it's present. BCOLOR1 is next.
This also allows removing si_shader::nparam and
si_shader::ps_input_param_offset, which are useless now.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 2 Jan 2016 01:25:51 +0000 (02:25 +0100)]
radeonsi: move SPI_PS_INPUT_CNTL value computation to a separate function
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jan 2016 18:44:16 +0000 (19:44 +0100)]
radeonsi: generate a color_two_side variant only if the shader reads colors
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 27 Dec 2015 19:10:33 +0000 (20:10 +0100)]
radeonsi: move si_shader_context initialization into a separate function
This will be re-used later.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 30 Jan 2016 15:43:53 +0000 (16:43 +0100)]
st/mesa: remove st_is_program_native
The default scenario sets GL_TRUE too.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>