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Sanjay Patel [Tue, 21 Aug 2018 14:45:13 +0000 (14:45 +0000)]
[InstSimplify] use isKnownNeverNaN to fold more fcmp ord/uno
Remove duplicate tests from InstCombine that were added with
D50582. I left negative tests there to verify that nothing
in InstCombine tries to go overboard. If isKnownNeverNaN is
improved to handle the FP binops or other cases, we should
have coverage under InstSimplify, so we could remove more
duplicate tests from InstCombine at that time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340279
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Anna Thomas [Tue, 21 Aug 2018 14:40:27 +0000 (14:40 +0000)]
[LV] Vectorize loops where non-phi instructions used outside loop
Summary:
Follow up change to rL339703, where we now vectorize loops with non-phi
instructions used outside the loop. Note that the cyclic dependency
identification occurs when identifying reduction/induction vars.
We also need to identify that we do not allow users where the PSCEV information
within and outside the loop are different. This was the fix added in rL307837
for PR33706.
Reviewers: Ayal, mkuper, fhahn
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D50778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340278
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Sanjay Patel [Tue, 21 Aug 2018 13:33:13 +0000 (13:33 +0000)]
[InstSimplify] add tests for FP uno/ord with nnan; NFC
This is a slight modification of the tests from D50582;
change half of the predicates to 'uno' so we have coverage
for that side too. All of the positive tests can fold to a
constant (true/false), so that should happen in instsimplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340276
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Anna Thomas [Tue, 21 Aug 2018 13:02:09 +0000 (13:02 +0000)]
NFC: Add loop vectorizer tests showing various control flow within loop that skip iterations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340275
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Andrea Di Biagio [Tue, 21 Aug 2018 13:00:44 +0000 (13:00 +0000)]
[llvm-mca] Replace use of llvm::any_of with std::any_of.
This should unbreak the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340274
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Andrea Di Biagio [Tue, 21 Aug 2018 12:40:15 +0000 (12:40 +0000)]
[llvm-mca] Add method cycleEvent() to class Scheduler. NFCI
The goal of this patch is to simplify the Scheduler's interface in preparation
for D50929.
Some methods in the Scheduler's interface should not be exposed to external
users, since their presence makes it hard to both understand, and extend the
Scheduler's interface.
This patch removes the following two methods from the public Scheduler's API:
- reclaimSimulatedResources()
- updatePendingQueue()
Their logic has been migrated to a new method named 'cycleEvent()'.
Methods 'updateIssuedSet()' and 'promoteToReadySet()' still exist. However,
they are now private members of class Scheduler.
This simplifies the interaction with the Scheduler from the ExecuteStage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340273
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Tim Renouf [Tue, 21 Aug 2018 11:08:12 +0000 (11:08 +0000)]
[AMDGPU] Allow int types for MUBUF vdata
Summary:
Previously the new llvm.amdgcn.raw/struct.buffer.load/store intrinsics
only allowed float types for the data to be loaded or stored, which
sometimes meant the frontend needed to generate a bitcast. In this, the
new intrinsics copied the old buffer intrinsics.
This commit extends the new intrinsics to allow int types as well.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D50315
Change-Id: I8202af2d036455553681dcbb3d7d32ae273f8f85
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340270
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Tim Renouf [Tue, 21 Aug 2018 11:07:10 +0000 (11:07 +0000)]
[AMDGPU] New buffer intrinsics
Summary:
This commit adds new intrinsics
llvm.amdgcn.raw.buffer.load
llvm.amdgcn.raw.buffer.load.format
llvm.amdgcn.raw.buffer.load.format.d16
llvm.amdgcn.struct.buffer.load
llvm.amdgcn.struct.buffer.load.format
llvm.amdgcn.struct.buffer.load.format.d16
llvm.amdgcn.raw.buffer.store
llvm.amdgcn.raw.buffer.store.format
llvm.amdgcn.raw.buffer.store.format.d16
llvm.amdgcn.struct.buffer.store
llvm.amdgcn.struct.buffer.store.format
llvm.amdgcn.struct.buffer.store.format.d16
llvm.amdgcn.raw.buffer.atomic.*
llvm.amdgcn.struct.buffer.atomic.*
with the following changes from the llvm.amdgcn.buffer.*
intrinsics:
* there are separate raw and struct versions: raw does not have an
index arg and sets idxen=0 in the instruction, and struct always sets
idxen=1 in the instruction even if the index is 0, to allow for the
fact that gfx9 does bounds checking differently depending on whether
idxen is set;
* there is a combined cachepolicy arg (glc+slc)
* there are now only two offset args: one for the offset that is
included in bounds checking and swizzling, to be split between the
instruction's voffset and immoffset fields, and one for the offset
that is excluded from bounds checking and swizzling, to go into the
instruction's soffset field.
The AMDISD::BUFFER_* SD nodes always have an index operand, all three
offset operands, combined cachepolicy operand, and an extra idxen
operand.
The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D50306
Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340269
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Tim Renouf [Tue, 21 Aug 2018 11:06:05 +0000 (11:06 +0000)]
[AMDGPU] New tbuffer intrinsics
Summary:
This commit adds new intrinsics
llvm.amdgcn.raw.tbuffer.load
llvm.amdgcn.struct.tbuffer.load
llvm.amdgcn.raw.tbuffer.store
llvm.amdgcn.struct.tbuffer.store
with the following changes from the llvm.amdgcn.tbuffer.* intrinsics:
* there are separate raw and struct versions: raw does not have an index
arg and sets idxen=0 in the instruction, and struct always sets
idxen=1 in the instruction even if the index is 0, to allow for the
fact that gfx9 does bounds checking differently depending on whether
idxen is set;
* there is a combined format arg (dfmt+nfmt)
* there is a combined cachepolicy arg (glc+slc)
* there are now only two offset args: one for the offset that is
included in bounds checking and swizzling, to be split between the
instruction's voffset and immoffset fields, and one for the offset
that is excluded from bounds checking and swizzling, to go into the
instruction's soffset field.
The AMDISD::TBUFFER_* SD nodes always have an index operand, all three
offset operands, combined format operand, combined cachepolicy operand,
and an extra idxen operand.
The tbuffer pseudo- and real instructions now also have a combined
format operand.
The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store
intrinsics continue to work.
V2: Separate raw and struct intrinsics.
V3: Moved extract_glc and extract_slc defs to a more sensible place.
V4: Rebased on D49995.
V5: Only two separate offset args instead of three.
V6: Pseudo- and real instructions have joint format operand.
V7: Restored optionality of dfmt and nfmt in assembler.
V8: Addressed minor review comments.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D49026
Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340268
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Bjorn Pettersson [Tue, 21 Aug 2018 10:59:50 +0000 (10:59 +0000)]
Change how finalizeBundle selects debug location for the BUNDLE instruction
Summary:
Previously a BUNDLE instruction inherited the DebugLoc from the
first instruction in the bundle, even if that DebugLoc had no
DILocation. With this commit this is changed into selecting the
first DebugLoc that has a DILocation, by searching among the
bundled instructions.
The idea is to reduce amount of bundles that are lacking
debug locations.
Reviewers: #debug-info, JDevlieghere
Reviewed By: JDevlieghere
Subscribers: JDevlieghere, mattd, llvm-commits
Differential Revision: https://reviews.llvm.org/D50639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340267
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Simon Pilgrim [Tue, 21 Aug 2018 10:44:06 +0000 (10:44 +0000)]
[X86] Add SSE2 sdiv combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340264
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Sam Parker [Tue, 21 Aug 2018 10:26:59 +0000 (10:26 +0000)]
[DAGCombiner] Reduce load widths of shifted masks
During combining, ReduceLoadWdith is used to combine AND nodes that
mask loads into narrow loads. This patch allows the mask to be a
shifted constant. This results in a narrow load which is then left
shifted to compensate for the new offset.
Differential Revision: https://reviews.llvm.org/D50432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340261
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Simon Pilgrim [Tue, 21 Aug 2018 10:20:36 +0000 (10:20 +0000)]
[TargetLowering] Add BuildSDiv support for division by one or negone.
This reduces most of the sdiv stages (the MULHS, shifts etc.) to just zero/identity values and use the numerator scale factor to multiply by +1/-1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340260
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Petar Jovanovic [Tue, 21 Aug 2018 08:15:56 +0000 (08:15 +0000)]
[MIPS GlobalISel] Select bitwise instructions
Select bitwise instructions for i32.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D50183
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340258
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Max Kazantsev [Tue, 21 Aug 2018 08:11:31 +0000 (08:11 +0000)]
[LICM] Hoist guards with invariant conditions
This patch teaches LICM to hoist guards from the loop if they are guaranteed to execute and
if there are no side effects that could prevent that.
Differential Revision: https://reviews.llvm.org/D50501
Reviewed By: reames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340256
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Bjorn Pettersson [Tue, 21 Aug 2018 07:49:05 +0000 (07:49 +0000)]
[RegisterCoalescer] Do not assert when trying to remat dead values
Summary:
RegisterCoalescer::reMaterializeTrivialDef used to assert that
the input register was live in. But as shown by the new
coalesce-dead-lanes.mir test case that seems to be a valid
scenario. We now return false instead of the assert, simply
avoiding to remat the dead def.
Normally a COPY of an undef value is eliminated by
eliminateUndefCopy(). Although we only do that when the
destination isn't a physical register. So the situation
above should be limited to the case when we copy an undef
value to a physical register.
Reviewers: kparzysz, wmi, tpr
Reviewed By: kparzysz
Subscribers: MatzeB, qcolombet, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D50842
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340255
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Max Kazantsev [Tue, 21 Aug 2018 07:37:02 +0000 (07:37 +0000)]
[NFC] Add some LICM tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340254
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Kirill Bobyrev [Tue, 21 Aug 2018 07:23:45 +0000 (07:23 +0000)]
[llvm] NFC: Fix assert condition and suppress warning
As mentioned by andreadb, assert condition is wrong and causes
GCC warning.
Related Revision: https://reviews.llvm.org/D50839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340252
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Max Kazantsev [Tue, 21 Aug 2018 07:15:06 +0000 (07:15 +0000)]
[NFC] Factor out predecessors collection into a separate method
It may be reused in a different piece of logic.
Differential Revision: https://reviews.llvm.org/D50890
Reviewed By: reames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340250
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Serguei Katkov [Tue, 21 Aug 2018 04:27:07 +0000 (04:27 +0000)]
[IR Verifier] Do not allow bitcast of pointer to vector of pointers and vice versa.
LangRef for BitCast requires that
"The bit sizes of value and the destination type, ty2, must be identical".
Currently verifier allows BitCast of pointer to vector of pointers so that
the sizes are different.
This change fixes that.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: llvm-commits, wdng
Differential Revision: https://reviews.llvm.org/D50886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340249
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Alex Langford [Tue, 21 Aug 2018 01:43:03 +0000 (01:43 +0000)]
[docs] Fix a small typo in a debug info example
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340246
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Philip Reames [Tue, 21 Aug 2018 00:55:35 +0000 (00:55 +0000)]
[AST] Mark invariant.starts as being readonly
These intrinsics are modelled as writing for control flow purposes, but they don't actually write to any location. Marking these - as we did for guards - allows LICM to hoist loads out of loops containing invariant.starts.
Differential Revision: https://reviews.llvm.org/D50861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340245
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Philip Reames [Tue, 21 Aug 2018 00:42:07 +0000 (00:42 +0000)]
[LICM] Add tests from D50786 [NFC]
Exercise more use of volatiles to illustrate that nothing changes as we tweak how we detect them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340244
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Philip Reames [Tue, 21 Aug 2018 00:37:09 +0000 (00:37 +0000)]
[LICM][NFC] Add tests from D50730
Landing tests so corresponding change can show effects clearly. see
D50730 [AST] Generalize argument specific aliasing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340243
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Philip Reames [Tue, 21 Aug 2018 00:14:14 +0000 (00:14 +0000)]
[LICM] More tests for D50925 [NFC]
This time, the corresponding cases where we can hoist (store-like) calls out of loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340242
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Fangrui Song [Tue, 21 Aug 2018 00:13:52 +0000 (00:13 +0000)]
[llvm-objcopy] Simplify find(X,Y) != X.end() with is_contained()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340241
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Reid Kleckner [Tue, 21 Aug 2018 00:03:21 +0000 (00:03 +0000)]
Fix global_metadata_external_comdat.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340240
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Zachary Turner [Mon, 20 Aug 2018 23:59:21 +0000 (23:59 +0000)]
[MS Demangler] Demangle special operator 'dynamic initializer'.
This is encoded as __E and should print something like
"dynamic initializer for 'Foo'(void)"
This also adds support for dynamic atexit destructor, which is
basically identical but encoded as __F with slightly different
description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340239
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Zachary Turner [Mon, 20 Aug 2018 23:58:58 +0000 (23:58 +0000)]
[MS Demangler] Anonymous namespace hashes can be backreferenced.
Previously we were not remembering the key values of anonymous
namespaces, but we need to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340238
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Zachary Turner [Mon, 20 Aug 2018 23:58:35 +0000 (23:58 +0000)]
[MS Demangler] Properly demangle anonymous namespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340237
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Heejin Ahn [Mon, 20 Aug 2018 23:49:29 +0000 (23:49 +0000)]
[WebAssembly] Revert type of wake count in atomic.wake to i32
Summary:
We decided to revert this from i64 to i32 in Nov 28 CG meeting. Fixes
PR38632.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D51010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340234
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Philip Reames [Mon, 20 Aug 2018 23:37:59 +0000 (23:37 +0000)]
[LICM][Tests] Add tests for store hoisting [NFC]
https://reviews.llvm.org/D50925 will be rebased on top of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340233
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Reid Kleckner [Mon, 20 Aug 2018 23:35:45 +0000 (23:35 +0000)]
Re-land r334313 "[asan] Instrument comdat globals on COFF targets"
If we can use comdats, then we can make it so that the global metadata
is thrown away if the prevailing definition of the global was
uninstrumented. I have only tested this on COFF targets, but in theory,
there is no reason that we cannot also do this for ELF.
This will allow us to re-enable string merging with ASan on Windows,
reducing the binary size cost of ASan on Windows.
I tested this change with ASan+PGO, and I fixed an issue with the
__llvm_profile_raw_version symbol. With the old version of my patch, we
would attempt to instrument that symbol on ELF because it had a comdat
with external linkage. If we had been using the linker GC-friendly
metadata scheme, everything would have worked, but clang does not enable
it by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340232
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Craig Topper [Mon, 20 Aug 2018 23:04:25 +0000 (23:04 +0000)]
[InstCombine] Add splat vector constant support to foldICmpAddOpConst.
Differential Revision: https://reviews.llvm.org/D50946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340231
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Heejin Ahn [Mon, 20 Aug 2018 23:02:15 +0000 (23:02 +0000)]
[WebAssembly] Remove an unused argument from writeSPToMemory (NFC)
Reviewers: dschuff
Subscribers: dschuff, sbc100, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D50933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340230
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Fangrui Song [Mon, 20 Aug 2018 23:01:57 +0000 (23:01 +0000)]
[llvm-strip] Allow only one input
Summary: Before, llvm-strip accepted a second argument but it would just be ignored.
Reviewers: alexshap, jhenderson, paulsemel
Reviewed By: alexshap
Subscribers: jakehehrlich, rupprecht, llvm-commits
Differential Revision: https://reviews.llvm.org/D51004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340229
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Matt Davis [Mon, 20 Aug 2018 22:41:27 +0000 (22:41 +0000)]
[llvm-mca] Remove unused formal parameter. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340227
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Michael Berg [Mon, 20 Aug 2018 22:26:58 +0000 (22:26 +0000)]
extend binop folds for selects to include true and false binops flag intersection
Summary: This change address bug 38641
Reviewers: spatel, wristow
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D50996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340222
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Zachary Turner [Mon, 20 Aug 2018 22:18:21 +0000 (22:18 +0000)]
[llvm-objdump] Add ability to demangle COFF symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340221
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Craig Topper [Mon, 20 Aug 2018 21:51:35 +0000 (21:51 +0000)]
[X86] Add test command line to expose PR38649.
Bypass slow division and constant hoisting are conspiring to break div+rem of large constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340217
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Craig Topper [Mon, 20 Aug 2018 21:08:35 +0000 (21:08 +0000)]
[X86] Prevent lowerVectorShuffleByMerging128BitLanes from creating cycles
Due to some splat handling code in getVectorShuffle, its possible for NewV1/NewV2 to have their mask modified from what is requested. This can lead to cycles being created in the DAG.
This patch examines the returned mask and makes sure its different. Long term we may need to look closer at that splat code in getVectorShuffle, or add more splat awareness to getVectorShuffle.
Fixes PR38639
Differential Revision: https://reviews.llvm.org/D50981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340214
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Craig Topper [Mon, 20 Aug 2018 20:57:35 +0000 (20:57 +0000)]
[X86] Teach combineTruncatedArithmetic to handle some cases of ISD::SUB
We can safely avoid interfering with the subus combine if both inputs are freely truncatable. Either both extends, or an extend and a constant vector.
Differential Revision: https://reviews.llvm.org/D50878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340212
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Craig Topper [Mon, 20 Aug 2018 20:57:32 +0000 (20:57 +0000)]
[X86] Pre-commit test cases for D50878.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340211
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Craig Topper [Mon, 20 Aug 2018 20:57:30 +0000 (20:57 +0000)]
[LegacyPassManager] Remove analysis P from AnUsageMap before deleting it in schedulePass.
If we deem the analysis pass useless and delete it, we need to make sure we remove it from AnUsageMap. Otherwise we might allocate another pass in the freed memory. This will cause us to reuse the AnalysisUsage from the original pass instead of the new one.
Fixes PR38511
Differential Revision: https://reviews.llvm.org/D50573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340210
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Krzysztof Parzyszek [Mon, 20 Aug 2018 20:37:57 +0000 (20:37 +0000)]
Consistently use MemoryLocation::UnknownSize to indicate unknown access size
1. Change the software pipeliner to use unknown size instead of dropping
memory operands. It used to do it before, but MachineInstr::mayAlias
did not handle it correctly.
2. Recognize UnknownSize in MachineInstr::mayAlias.
3. Print and parse UnknownSize in MIR.
Differential Revision: https://reviews.llvm.org/D50339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340208
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David Blaikie [Mon, 20 Aug 2018 20:02:29 +0000 (20:02 +0000)]
Add missing include (<functional> for std::ref)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340205
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Richard Smith [Mon, 20 Aug 2018 19:44:01 +0000 (19:44 +0000)]
Move Itanium demangler implementation into a header file and add visitation support.
Summary:
This transforms the Itanium demangler into a generic reusable library that can
be used to build, traverse, and transform Itanium mangled name trees.
This is in preparation for adding a canonicalizing demangler, which
cannot live in the Demangle library for layering reasons. In order to
keep the diffs simpler, this patch moves more code to the new header
than is strictly necessary: in particular, all of the printLeft /
printRight implementations can be moved to the implementation file.
(And indeed we could make them non-virtual now if we wished, and remove
the vptr from Node.)
All nodes are now included in the Kind enumeration, rather than omitting
some of the Expr nodes, and the three different floating-point literal
node types now have distinct Kind values.
As a proof of concept for the visitation / matching mechanism, this
patch implements a Node dumping facility on top of it, replacing the
prior mechanism that produced the pretty-printed output rather than a
tree dump. Sample dump output:
FunctionEncoding(
NameType("int"),
NameWithTemplateArgs(
NestedName(
NameWithTemplateArgs(
NameType("A"),
TemplateArgs(
{NameType("B")})),
NameType("f")),
TemplateArgs(
{NameType("int")})),
{},
<null>,
QualConst, FunctionRefQual::FrefQualLValue)
As a next step, it would make sense to move the LLVM high-level interface to
the demangler (the itaniumDemangler function and ItaniumPartialDemangler class)
into the Support library, and implement them in terms of the Demangle library.
This would allow the libc++abi demangler implementation to be an identical copy
of the llvm Demangle library, and would allow the LLVM implementation to reuse
LLVM components such as llvm::BumpPtrAllocator, but we'll need to decide how to
coordinate that with the MS ABI demangler, so I'm not doing that in this patch.
No functionality change intended other than the behavior of dump().
Reviewers: erik.pilkington, zturner, chandlerc, dlj
Subscribers: aheejin, llvm-commits
Differential Revision: https://reviews.llvm.org/D50930
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340203
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Vitaly Buka [Mon, 20 Aug 2018 19:31:03 +0000 (19:31 +0000)]
Revert "AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space"
As it introduces out of bound access.
This reverts commit r340172 and r340171
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340202
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Cameron McInally [Mon, 20 Aug 2018 19:28:56 +0000 (19:28 +0000)]
[FPEnv] Support constrained FREM intrinsic
Differential Revision: https://reviews.llvm.org/D50975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340201
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Marcello Maggioni [Mon, 20 Aug 2018 19:23:45 +0000 (19:23 +0000)]
[PSV] Update API to be able to use TargetCustom without UB.
getTargetCustom() requires values for "Kind" in the constructor
that are not in the PSVKind enum. Passing a value that is not inside
an enum as an argument to a constructor of the type of the enum is
UB. Changing to the underlying type of the enum would solve the UB
Differential Revision: https://reviews.llvm.org/D50909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340200
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Zachary Turner [Mon, 20 Aug 2018 19:15:35 +0000 (19:15 +0000)]
[MS Demangler] Demangle member pointer template parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340199
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Aditya Nandakumar [Mon, 20 Aug 2018 18:43:19 +0000 (18:43 +0000)]
Revert "Revert r339977: [GISel]: Add Opcodes for a few LLVM Intrinsics"
This reverts commit
7debc334e6421bb5251ef8f18e97166dfc7dd787.
I missed updating legalizer-info-validation.mir as I had assertions
turned off in my build and that specific test requires asserts. Fixed it
now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340197
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Simon Pilgrim [Mon, 20 Aug 2018 18:23:54 +0000 (18:23 +0000)]
[TargetLowering] Disable BuildSDiv division by one or negone.
Fuzz tests have detected an issue, currently working on a fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340195
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Sanjay Patel [Mon, 20 Aug 2018 18:19:02 +0000 (18:19 +0000)]
[ConstantFolding] improve folding of binops with vector undef operand
A non-undef operand may still have undef constant elements,
so we should always propagate the vector results per-lane.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340194
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Alina Sbirlea [Mon, 20 Aug 2018 18:15:02 +0000 (18:15 +0000)]
[MemorySSA] Update comment to better describe cfg change (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340192
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Sanjay Patel [Mon, 20 Aug 2018 17:31:34 +0000 (17:31 +0000)]
[ConstantFolding] add tests for binops on vectors with undef elements; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340190
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Matt Arsenault [Mon, 20 Aug 2018 16:51:00 +0000 (16:51 +0000)]
ValueTracking: Handle more instructions in isKnownNeverNaN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340187
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Reid Kleckner [Mon, 20 Aug 2018 16:50:19 +0000 (16:50 +0000)]
Revert rr340111 "[GISel]: Add Legalization/lowering code for bit counting operations"
It causes LegalizerHelperTest.LowerBitCountingCTTZ1 to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340186
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Reid Kleckner [Mon, 20 Aug 2018 16:49:54 +0000 (16:49 +0000)]
Add cmake option to disable minidumps, default it to off
Since crash dumping landed in r268519, May 2016, I have not once seen
anyone use an uploaded minidump to debug a compiler crash. Therefore,
I'm turning this off by default. The dumps clutter up user and buildbot
temp directories. Each file is only about 56KB, but it adds up.
In the context of clang, the extra line about the minidump confuses
users, when what we really want from them is the pre-processed source
code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340185
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Sanjay Patel [Mon, 20 Aug 2018 16:49:08 +0000 (16:49 +0000)]
[InstCombine] add tests for insertelement+binop; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340184
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Andrea Di Biagio [Mon, 20 Aug 2018 14:41:36 +0000 (14:41 +0000)]
[llvm-mca] Make the LSUnit a HardwareUnit, and allow derived classes to implement a different memory consistency model.
The LSUnit is now a HardwareUnit, and it is owned by the mca::Context.
Derived classes can now implement a different consistency model by overriding
method `LSUnit::isReady()`.
This patch also slightly refactors the Scheduler interface in the attempt to
simplifying the interaction between ExecuteStage and the underlying Scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340176
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Simon Pilgrim [Mon, 20 Aug 2018 13:44:03 +0000 (13:44 +0000)]
[SelectionDAG] Reuse the Op's VT. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340173
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Samuel Pitoiset [Mon, 20 Aug 2018 13:31:41 +0000 (13:31 +0000)]
AMDGPU: fix compilation errors since r340171
Some buildbot slaves reports compilation errors, but it
compiled fine on my side, sorry for the breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340172
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Samuel Pitoiset [Mon, 20 Aug 2018 13:18:59 +0000 (13:18 +0000)]
AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space
32-bit constant address space is declared as 6, so the
maximum number of address spaces is 6, not 5.
Fixes "LLVM ERROR: Pointer address space out of range".
v3: use static_assert()
v2: add a very simple test for 32-bit addr space
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106630
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340171
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Haojian Wu [Mon, 20 Aug 2018 13:12:54 +0000 (13:12 +0000)]
Fix an undefined behavior when storing an empty StringRef.
Summary: Passing a nullptr to memcpy is UB.
Reviewers: ioeric
Subscribers: llvm-commits, cfe-commits
Differential Revision: https://reviews.llvm.org/D50966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340170
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Simon Pilgrim [Mon, 20 Aug 2018 13:05:48 +0000 (13:05 +0000)]
[SelectionDAG] Add partial sign-bit support to ComputeNumSignBits for BITCAST nodes
Only adds support to the existing 'large element' scalar/vector to 'small element' vector bitcasts.
Handle the case where the sign bit extends to only part of the small elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340169
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Simon Pilgrim [Mon, 20 Aug 2018 11:47:15 +0000 (11:47 +0000)]
[X86][SSE] Fix PACKSS bitcast test from rL340166
We need the signbits to extends to lower 16-bits of the even elements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340167
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Simon Pilgrim [Mon, 20 Aug 2018 11:10:12 +0000 (11:10 +0000)]
[X86][SSE] Add PACKSS test showing ComputeNumSignBits failure to handle a partial sign bits extension through a bitcast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340166
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Simon Pilgrim [Mon, 20 Aug 2018 11:01:51 +0000 (11:01 +0000)]
[X86] Drop unnecessary exact qualifier from packss test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340165
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Victor Leschuk [Mon, 20 Aug 2018 09:59:08 +0000 (09:59 +0000)]
[DWARF] Refactor DWARF classes to use unified error reporting. NFC.
DWARF-related classes in lib/DebugInfo/DWARF contained
duplicating code for creating StringError instances, like:
template <typename... Ts>
static Error createError(char const *Fmt, const Ts &... Vals) {
std::string Buffer;
raw_string_ostream Stream(Buffer);
Stream << format(Fmt, Vals...);
return make_error<StringError>(Stream.str(), inconvertibleErrorCode());
}
Similar function was placed in Support lib in https://reviews.llvm.org/D49824
This revision makes DWARF classes use this function
instead of their local implementation of it.
Reviewers: aprantl, dblaikie, probinson, wolfgangp, JDevlieghere, jhenderson
Reviewed By: JDevlieghere, jhenderson
Differential Revision: https://reviews.llvm.org/D49964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340163
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Simon Pilgrim [Mon, 20 Aug 2018 09:49:20 +0000 (09:49 +0000)]
Use LLVM_BUILTIN_TRAP not __builtin_trap to appease windows builds. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340162
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Sander de Smalen [Mon, 20 Aug 2018 09:16:59 +0000 (09:16 +0000)]
[AArch64][SVE] Asm: Add SVE System registers
This patch adds system registers for controlling aspects of SVE:
- ZCR_EL1 (r/w) visible at EL1 and EL0.
- ZCR_EL2 (r/w) visible at EL2 and Non-secure EL1 and EL0.
- ZCR_EL3 (r/w) visible at all exception levels.
and a system register identifying SVE:
- ID_AA64ZFR0_EL1 (r) SVE Feature identifier.
Reviewers: SjoerdMeijer, samparker, pbarrio, fhahn, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D50885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340158
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Kirill Bobyrev [Mon, 20 Aug 2018 07:00:36 +0000 (07:00 +0000)]
[llvm] Make YAML serialization up to 2.5 times faster
This patch significantly improves performance of the YAML serializer by
optimizing `YAML::isNumeric` function. This function is called on the
most strings and is highly inefficient for two reasons:
* It uses `Regex`, which is parsed and compiled each time this
function is called
* It uses multiple passes which are not necessary
This patch introduces stateful ad hoc YAML number parser which does not
rely on `Regex`. It also fixes YAML number format inconsistency: current
implementation supports C-stile octal number format (`
01234567`) which
was present in YAML 1.0 specialization (http://yaml.org/spec/1.0/),
[Section 2.4. Tags, Example 2.19] but was deprecated and is no longer
present in latest YAML 1.2 specification
(http://yaml.org/spec/1.2/spec.html), see [Section 10.3.2. Tag
Resolution]. Since the rest of the rest of the implementation does not
support other deprecated YAML 1.0 numeric features such as sexagecimal
numbers, commas as delimiters it is treated as inconsistency and not
longer supported. This patch also adds unit tests to ensure the validity
of proposed implementation.
This performance bottleneck was identified while profiling Clangd's
global-symbol-builder tool with my colleague @ilya-biryukov. The
substantial part of the runtime was spent during a single-thread Reduce
phase, which concludes with YAML serialization of collected symbol
collection. Regex matching was accountable for approximately 45% of the
whole runtime (which involves sharded Map phase), now it is reduced to
18% (which is spent in `clang::clangd::CanonicalIncludes` and can be
also optimized because all used regexes are in fact either suffix
matches or exact matches).
`llvm-yaml-numeric-parser-fuzzer` was used to ensure the validity of the
proposed regex replacement. Fuzzing for ~60 hours using 10 threads did
not expose any bugs.
Benchmarking `global-symbol-builder` (using `hyperfine --warmup 2
--min-runs 5 'command 1' 'command 2'`) tool by processing a reasonable
amount of code (26 source files matched by
`clang-tools-extra/clangd/*.cpp` with all transitive includes) confirmed
our understanding of the performance bottleneck nature as it speeds up
the command by the factor of 1.6x:
| Command | Mean [s] | Min…Max [s] |
| this patch (D50839) | 84.7 ± 0.6 | 83.3…84.7 |
| master (rL339849) | 133.1 ± 0.8 | 132.4…134.6 |
Using smaller samples (e.g. by collecting symbols from
`clang-tools-extra/clangd/AST.cpp` only) yields even better performance
improvement, which is expected because Map phase takes less time
compared to Reduce and is 2.05x faster and therefore would significantly
improve the performance of standalone YAML serializations.
| Command | Mean [ms] | Min…Max [ms] |
| this patch (D50839) | 3702.2 ± 48.7 | 3635.1…3752.3 |
| master (rL339849) | 7607.6 ± 109.5 | 7533.3…7796.4 |
Reviewed by: zturner, ilya-biryukov
Differential revision: https://reviews.llvm.org/D50839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340154
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Justin Bogner [Mon, 20 Aug 2018 06:37:11 +0000 (06:37 +0000)]
[SimplifyCFG] Replace some uses of bitwise or with logical or
It's clearer to use logical or for boolean values. Thanks to Steven
Zhang for noticing!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340153
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Craig Topper [Mon, 20 Aug 2018 05:35:12 +0000 (05:35 +0000)]
[InstCombine] Move some variable declarations into a more appropriate scope. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340150
91177308-0d34-0410-b5e6-
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QingShan Zhang [Mon, 20 Aug 2018 02:52:55 +0000 (02:52 +0000)]
[PowerPC] Add a peephole post RA to transform the inst that fed by add
If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e.
y = add imm, reg
LFDX. 0, y
-->
LFD imm(reg)
Reviewers: Nemanjai
Differential Revision: https://reviews.llvm.org/D49007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340149
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whitequark [Sun, 19 Aug 2018 23:40:05 +0000 (23:40 +0000)]
[bindings/go] Add coroutine passes
Add Go bindings for CoroEarly, CoroSplit, CoroElide and CoroCleanup.
Differential Revision: https://reviews.llvm.org/D50951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340148
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whitequark [Sun, 19 Aug 2018 23:39:57 +0000 (23:39 +0000)]
[LLVM-C] Add coroutine passes
Differential Revision: https://reviews.llvm.org/D50950
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340147
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whitequark [Sun, 19 Aug 2018 23:39:47 +0000 (23:39 +0000)]
[C-API][DIBuilder] Added DIFlags in LLVMDIBuilderCreateBasicType
Added DIFlags in LLVMDIBuilderCreateBasicType to add optional DWARF
attributes, such as DW_AT_endianity.
Patch by Chirag Patel.
Differential Revision: https://reviews.llvm.org/D50832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340146
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Craig Topper [Sun, 19 Aug 2018 18:03:34 +0000 (18:03 +0000)]
[InstCombine] Add test cases for an icmp combine that is missing support for splat vector constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340144
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 19 Aug 2018 17:47:50 +0000 (17:47 +0000)]
[SelectionDAG] Add basic demanded elements support to ComputeNumSignBits for BITCAST nodes
Only adds support to the existing 'large element' scalar/vector to 'small element' vector bitcasts.
The next step would be to support cases where the large elements aren't all sign bits, and determine the small element equivalent based on the demanded elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340143
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 19 Aug 2018 16:01:47 +0000 (16:01 +0000)]
[X86][SSE] Add PACKSS test showing ComputeNumSignBits failure to handle demanded elts through a bitcast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340139
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 19 Aug 2018 04:26:31 +0000 (04:26 +0000)]
[X86] Fix an issue in the matching for ADDUS.
We were basically assuming only one operand of the compare could be an ADD node and using that to swap operands. But we can have a normal add followed by a saturing add.
This rewrites the canonicalization to just be based on the condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340134
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 19 Aug 2018 04:26:29 +0000 (04:26 +0000)]
[X86] Add a test case showing an issue in our addusw pattern matching.
We are unable to handle a normal add followed by a saturing add with certain operand orders on the icmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340133
91177308-0d34-0410-b5e6-
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Aditya Kumar [Sat, 18 Aug 2018 20:17:19 +0000 (20:17 +0000)]
Updating MergeFunctions.rst
Improving readability, removing redundant contents.
Reviewers: hiraditya
Differential Revision: https://reviews.llvm.org/D50686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340131
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 18 Aug 2018 19:16:56 +0000 (19:16 +0000)]
[X86] Use SDValue::operator== instead of DAG.isEqualTo in strictly integer matching.
isEqualTo is more useful for floating point. operator== is sufficient for integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340130
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 18 Aug 2018 18:51:04 +0000 (18:51 +0000)]
[X86] Simplify the PADDUS legality check in combineSelect to match PSUBUS. NFC
While there remove some trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340129
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 18 Aug 2018 18:51:03 +0000 (18:51 +0000)]
[X86] Add support for using 512-bit PSUBUS to combineSelect.
The code already support 128 and 256 and even knows to split 256 for AVX1. So we really just needed to stop looking for specific VTs and subtarget features and just look for legal VTs with i8/i16 elements.
While there, add some curly braces around outer if statement bodies that contain only another if. It makes all the closing curly braces look more regular.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340128
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 18 Aug 2018 18:50:59 +0000 (18:50 +0000)]
[X86] Add test cases to show missed opportunities to use 512-bit PSUBUS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340127
91177308-0d34-0410-b5e6-
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Zachary Turner [Sat, 18 Aug 2018 18:49:48 +0000 (18:49 +0000)]
[MS Demangler] Resolve backreferences eagerly, not lazily.
A while back I submitted a patch to resolve backreferences
lazily, thinking this that it was not always possible to know
in advance what type you were looking at until you had completed
a full pass over the input, and therefore it would be impossible
to resolve backreferences eagerly.
This was mistaken though, and turned out to be an unrelated
problem. In fact, the reverse is true. You *must* resolve
backreferences eagerly. This is because certain types of nested
mangled symbols do not share a backreference context with their
parent symbol, and as such, if you try to resolve them lazily
their backreference context will have been lost by the time you
finish demangling the entire input. On the other hand, resolving
them eagerly appears to always work, and enables us to port
many more tests over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340126
91177308-0d34-0410-b5e6-
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Lang Hames [Sat, 18 Aug 2018 18:38:37 +0000 (18:38 +0000)]
[RuntimeDyld] Fix a bug in RuntimeDyld::loadObjectImpl that was over-allocating
space for common symbols.
Patch by Dmitry Sidorov. Thanks Dmitry!
Differential revision: https://reviews.llvm.org/D50240
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340125
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Simon Pilgrim [Sat, 18 Aug 2018 18:04:29 +0000 (18:04 +0000)]
[X86] Replace all single match schedule class instregexs with instrs entries
Helps reduce cost of instrw collection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340124
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Simon Pilgrim [Sat, 18 Aug 2018 15:58:19 +0000 (15:58 +0000)]
[X86] Merge shift/rotate schedule class instregexs
Helps reduce cost of instrw collection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340123
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Hsiangkai Wang [Sat, 18 Aug 2018 14:55:34 +0000 (14:55 +0000)]
[DebugInfo] In FastISel, convert llvm.dbg.label to DBG_LABEL MI.
Convert llvm.dbg.label(!label_metadata) to DBG_LABEL !label_metadata.
Differential Revision: https://reviews.llvm.org/D50622
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340122
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Craig Topper [Sat, 18 Aug 2018 06:00:16 +0000 (06:00 +0000)]
[X86] Add a signed test case for PR38622. Use nounwind to reduce the output on the unsigned test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340121
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Craig Topper [Sat, 18 Aug 2018 05:52:42 +0000 (05:52 +0000)]
[DAGCombiner] Allow divide by constant optimization on opaque constants.
Summary:
I believe this restores the behavior we had before r339147.
Fixes PR38622.
Reviewers: RKSimon, chandlerc, spatel
Reviewed By: chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D50936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340120
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Zachary Turner [Sat, 18 Aug 2018 03:54:16 +0000 (03:54 +0000)]
Add the extended XMM registers mappings for AVX-512.
After this we should have the entire AVX-512 register set
mapping in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340118
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Lang Hames [Sat, 18 Aug 2018 02:48:02 +0000 (02:48 +0000)]
[ORC] Fix some parameter names. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340116
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Lang Hames [Sat, 18 Aug 2018 02:06:18 +0000 (02:06 +0000)]
[ORC] Rename 'finalize' to 'emit' to avoid potential confusion.
An emitted symbol has had its contents written and its memory protections
applied, but it is not automatically ready to execute.
Prior to ORC supporting concurrent compilation, the term "finalized" could be
interpreted two different (but effectively equivalent) ways: (1) The finalized
symbol's contents have been written and its memory protections applied, and (2)
the symbol is ready to run. Now that ORC supports concurrent compilation, sense
(1) no longer implies sense (2). We have already introduced a new term, 'ready',
to capture sense (2), so rename sense (1) to 'emitted' to avoid any lingering
confusion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340115
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Peter Collingbourne [Sat, 18 Aug 2018 00:54:46 +0000 (00:54 +0000)]
MC: Remove dead code from WinCOFFObjectWriter.cpp. NFCI.
Remove code for writing auxiliary symbols of type function definition
and begin function. These types of symbols are associated with
pre-CodeView debug info and we never emit them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340113
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