OSDN Git Service
Mandeep Singh Grang [Sat, 7 Apr 2018 01:29:45 +0000 (01:29 +0000)]
[unittests] Change std::sort to llvm::sort in response to r327219
r327219 added wrappers to std::sort which randomly shuffle the container before
sorting. This will help in uncovering non-determinism caused due to undefined
sorting order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of
std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to
llvm::sort. Refer the comments section in D44363 for a list of all the
required patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329475
91177308-0d34-0410-b5e6-
96231b3b80d8
Graydon Hoare [Sat, 7 Apr 2018 00:44:02 +0000 (00:44 +0000)]
[Support] Make line-number cache robust against access patterns.
Summary:
The LLVM SourceMgr class (which is used indirectly by Swift, though not Clang)
has a routine for looking up line numbers of SMLocs. This routine uses a
shared, special-purpose cache that handles exactly one access pattern
efficiently: looking up the line number of an SMLoc that points into the same
buffer as the last query made to the SourceMgr, at a location in the buffer at
or ahead of the last query.
When this works it's fine, but when it fails it's catastrophic for performancer:
one recent out-of-order access from a Swift utility routine ran for tens of
seconds, spending 99% of its time repeatedly scanning buffers for '\n'.
This change removes the shared cache from the SourceMgr and installs a new
cache in each SrcBuffer. The per-SrcBuffer caches are also "full", in the sense
that rather than caching a single last-query pointer, they cache _all_ the
line-ending offsets, in a binary-searchable array, such that once it's
populated (on first access), all subsequent access patterns run at the same
speed.
Performance measurements I've done show this is actually a little bit faster on
real codebases (though only a couple fractions of a percent). Memory usage is
up by a few tens to hundreds of bytes per SrcBuffer that has a line lookup done
on it; I've attempted to minimize this by using dynamic selection of integer
sized when storing offset arrays. But the main motive here is to
make-impossible the cases we don't always see, that show up by surprise when
there is an out-of-order access pattern.
Reviewers: jordan_rose
Reviewed By: jordan_rose
Subscribers: probinson, llvm-commits
Differential Revision: https://reviews.llvm.org/D45003
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329470
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Smith [Sat, 7 Apr 2018 00:32:59 +0000 (00:32 +0000)]
Windows needs the current codepage instead of utf8 sometimes
Llvm-mc (and tools that use Path.inc on Windows) assume that strings are utf-8
encoded, however, this is not always the case. On Windows the default codepage
is not utf-8, so most of the time the strings are not utf-8 encoded.
The lld test 'format-binary-non-ascii' uses llvm-mc with a file with non-ascii
characters in the name which is how this bug was found. The test fails when run
using Python 3 because it uses properly encoded unicode strings (Python 2 actually
ends up using a byte string which is not utf-8 encoded, so the test passes, but
that's separate issue).
Patch by Stella Stamenova!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329468
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Smith [Sat, 7 Apr 2018 00:21:28 +0000 (00:21 +0000)]
[lit] Fix several Python 2/3 compatibility issues and tests
- In Python 2.x, basestring is the base string type, but in
Python 3.x basestring is not defined and instead str includes
unicode strings.
- When Python is in a path that includes spaces, it needs to
be specified with quotes in the test files for it to run.
- The cache.ll test relies on files of a specific size being
created by Python, but on some versions of Windows the
files that are created by the current code are one byte
larger than expected. To fix the test, update file creation
to always make files of the expected size.
Patch by Stella Stamenova!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329466
91177308-0d34-0410-b5e6-
96231b3b80d8
Artem Belevich [Fri, 6 Apr 2018 22:25:08 +0000 (22:25 +0000)]
[NVPTX] add support for initializing fp16 arrays.
Previously HalfTy was not handled which would either trigger an assertion,
or result in array initialized with garbage.
Differential Revision: https://reviews.llvm.org/D45391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329463
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Fri, 6 Apr 2018 21:41:17 +0000 (21:41 +0000)]
Fix warning by cl::opt<int> -> cl::opt<unsigned>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329461
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Fri, 6 Apr 2018 21:32:36 +0000 (21:32 +0000)]
Runtime flag to control branch funnel threshold
Reviewers: pcc
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D45193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329459
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Fri, 6 Apr 2018 21:14:33 +0000 (21:14 +0000)]
Revert r324557, "gold-plugin: Do not set codegen opt level based on LTO opt level."
It was reported that this change measurably regressed -plugin-opt=O3
performance.
There is an ongoing discussion on llvm-dev about the correct way to
set the CG opt level, see thread "[llvm-dev] [RFC] Adding function
attributes to represent codegen optimization level".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329458
91177308-0d34-0410-b5e6-
96231b3b80d8
Manoj Gupta [Fri, 6 Apr 2018 21:11:09 +0000 (21:11 +0000)]
[Release Notes] Add release note for "-fmerge-all-constants"
Summary:
Add note that "-fmerge-all-constants" is not applied as default
anymore.
Reviewers: rjmccall, rsmith, chandlerc
Subscribers: llvm-commits, thakis
Differential Revision: https://reviews.llvm.org/D45388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329457
91177308-0d34-0410-b5e6-
96231b3b80d8
Artem Belevich [Fri, 6 Apr 2018 21:10:24 +0000 (21:10 +0000)]
[NVPTX] Fixed vectorized LDG for f16.
v2f16 is a special case in NVPTX. v4f16 may be loaded as a pair of v2f16
and that was not previously handled correctly by tryLDGLDU()
Differential Revision: https://reviews.llvm.org/D45339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329456
91177308-0d34-0410-b5e6-
96231b3b80d8
Sameer AbuAsal [Fri, 6 Apr 2018 21:07:05 +0000 (21:07 +0000)]
[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329455
91177308-0d34-0410-b5e6-
96231b3b80d8
Mandeep Singh Grang [Fri, 6 Apr 2018 20:18:05 +0000 (20:18 +0000)]
[TableGen] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: stoklund, kparzysz, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329451
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Davis [Fri, 6 Apr 2018 20:14:13 +0000 (20:14 +0000)]
[StackProtector] Ignore certain intrinsics when calculating sspstrong heuristic.
Summary:
The 'strong' StackProtector heuristic takes into consideration call instructions.
Certain intrinsics, such as lifetime.start, can cause the
StackProtector to protect functions that do not need to be protected.
Specifically, a volatile variable, (not optimized away), but belonging to a stack
allocation will encourage a llvm.lifetime.start to be inserted during
compilation. Because that intrinsic is a 'call' the strong StackProtector
will see that the alloca'd variable is being passed to a call instruction, and
insert a stack protector. In this case the intrinsic isn't really lowered to a
call. This can cause unnecessary stack checking, at the cost of additional
(wasted) CPU cycles.
In the future we should rely on TargetTransformInfo::isLoweredToCall, but as of
now that routine considers all intrinsics as not being lowerable. That needs
to be corrected, and such a change is on my list of things to get moving on.
As a side note, the updated stack-protector-dbginfo.ll test always seems to
pass. I never see the dbg.declare/dbg.value reaching the
StackProtector::HasAddressTaken, but I don't see any code excluding dbg
intrinsic calls either, so I think it's the safest thing to do.
Reviewers: void, timshen
Reviewed By: timshen
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329450
91177308-0d34-0410-b5e6-
96231b3b80d8
Geoff Berry [Fri, 6 Apr 2018 18:47:33 +0000 (18:47 +0000)]
[EarlyCSE] Add debug counter for debugging mis-optimizations. NFC.
Reviewers: reames, spatel, davide, dberlin
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D45162
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329443
91177308-0d34-0410-b5e6-
96231b3b80d8
Sameer AbuAsal [Fri, 6 Apr 2018 18:27:45 +0000 (18:27 +0000)]
[RISCV] Update MC compression tests
Summary:
This patch updates MC tests related to compression in RISCV to
insure they work correctly with automatic compression and relaxation
enabled. This is the first part of a series of patches to implement
automatic compression for RISCV.
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: shiva0217, efriedma, llvm-commits, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng
Differential Revision: https://reviews.llvm.org/D43328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329441
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Preobrazhensky [Fri, 6 Apr 2018 18:24:49 +0000 (18:24 +0000)]
[AMDGPU][MC][GFX9] Added s_call_b64
See bug 36843: https://bugs.llvm.org/show_bug.cgi?id=36843
Differential Revision: https://reviews.llvm.org/D45268
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329440
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 6 Apr 2018 18:19:22 +0000 (18:19 +0000)]
[Hexagon] Fix assert with packetizing IMPLICIT_DEF instructions
The compiler is generating packet with the following instructions,
which causes an undefined register assert in the verifier.
$r0 = IMPLICIT_DEF
$r1 = IMPLICIT_DEF
S2_storerd_io killed $r29, 0, killed %d0
The problem is that the packetizer is not saving the IMPLICIT_DEF
instructions, which are needed when checking if it is legal to
add the store instruction. The fix is to add the IMPLICIT_DEF
instructions to the CurrentPacketMIs structure.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329439
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 6 Apr 2018 18:13:11 +0000 (18:13 +0000)]
[Hexagon] Prevent a stall across zero-latency instructions in a packet
Packetizer keeps two zero-latency bound instrctions in the same packet ignoring
the stalls on the later instruction. This should not be the case if there is no
data dependence.
Patch by Sumanth Gundapaneni.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329437
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 6 Apr 2018 18:10:13 +0000 (18:10 +0000)]
[Hexagon] Remove duplicated code, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329436
91177308-0d34-0410-b5e6-
96231b3b80d8
Mandeep Singh Grang [Fri, 6 Apr 2018 18:08:42 +0000 (18:08 +0000)]
[CodeGen] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: bogner, rnk, MatzeB, RKSimon
Reviewed By: rnk
Subscribers: JDevlieghere, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D45133
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329435
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 6 Apr 2018 17:51:57 +0000 (17:51 +0000)]
[Hexagon] Handle subregisters when calculating iteration count in HW loops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329434
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 17:25:06 +0000 (17:25 +0000)]
Cleanup Reduction helpers by using ArrayRef(NoneType) constructor. NFCI.
Pointed out by @abataev on D45366.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329431
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Preobrazhensky [Fri, 6 Apr 2018 17:25:00 +0000 (17:25 +0000)]
[AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_done
See bug 36844: https://bugs.llvm.org/show_bug.cgi?id=36844
Differential Revision: https://reviews.llvm.org/D45313
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329430
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 6 Apr 2018 17:24:08 +0000 (17:24 +0000)]
[InstCombine] limit nsz: -(X - Y) --> Y - X to hasOneUse()
As noted in the post-commit discussion for r329350, we shouldn't
generally assume that fsub is the same cost as fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329429
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 17:18:44 +0000 (17:18 +0000)]
Add additional tests from D45336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329427
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 17:15:56 +0000 (17:15 +0000)]
Add additional tests from D45366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329425
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 6 Apr 2018 17:12:18 +0000 (17:12 +0000)]
[X686] Add appropriate ReadAfterLd for the register input to memory forms of ADC/SBB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329424
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 17:01:54 +0000 (17:01 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329421
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Preobrazhensky [Fri, 6 Apr 2018 16:35:11 +0000 (16:35 +0000)]
[AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*
See bug 36840: https://bugs.llvm.org/show_bug.cgi?id=36840
Differential Revision: https://reviews.llvm.org/D45250
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329419
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 6 Apr 2018 16:30:52 +0000 (16:30 +0000)]
[InstCombine] add test for fsub+fneg with extra use; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329418
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 6 Apr 2018 16:29:31 +0000 (16:29 +0000)]
[X86] Remove InstRWs for basic arithmetic instructions from Sandy Bridge scheduler model.
We can get this right through WriteALU and friends now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329417
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 6 Apr 2018 16:16:48 +0000 (16:16 +0000)]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs
Summary:
This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency.
Apparently we were inconsistent about whether the store has latency or not thus the test changes.
I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5.
Reviewers: RKSimon, andreadb
Reviewed By: andreadb
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45351
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329416
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 6 Apr 2018 16:16:46 +0000 (16:16 +0000)]
[X86] Add an extra store address cycle to WriteRMW in the Sandy Bridge/Broadwell/Haswell/Skylake scheduler model.
Even those the address was calculated for the load, its calculated again for the store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329415
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 6 Apr 2018 16:16:43 +0000 (16:16 +0000)]
[X86] Merge itineraries for CLC, CMC, and STC.
These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329414
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 16:14:27 +0000 (16:14 +0000)]
[CostModel][X86] Regenerate bit count cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329413
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 6 Apr 2018 16:06:08 +0000 (16:06 +0000)]
[InstCombine] add potential calloc tests and regenerate checks; NFC
D45344 is proposing to remove the use restriction that made the calloc
transform safe, but it doesn't currently address the problematic example
given inD16337. Add a test to make sure that doesn't break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329412
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 16:00:28 +0000 (16:00 +0000)]
[CostModel][X86] Regenerate vector shuffle cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329410
91177308-0d34-0410-b5e6-
96231b3b80d8
Mircea Trofin [Fri, 6 Apr 2018 15:54:47 +0000 (15:54 +0000)]
[GlobalOpt] Fix support for casts in ctors.
Summary:
Fixing an issue where initializations of globals where constructors use
casts were silently translated to 0-initialization.
Reviewers: davidxl, evgeny777
Reviewed By: evgeny777
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329409
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Preobrazhensky [Fri, 6 Apr 2018 15:48:39 +0000 (15:48 +0000)]
[AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions
See bug 36839: https://bugs.llvm.org/show_bug.cgi?id=36839
Differential Revision: https://reviews.llvm.org/D45249
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329408
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 15:46:26 +0000 (15:46 +0000)]
[CostModel][X86] Regenerate bswap/bitreverse cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329407
91177308-0d34-0410-b5e6-
96231b3b80d8
Pete Couperus [Fri, 6 Apr 2018 15:43:11 +0000 (15:43 +0000)]
[ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}.
Add disassembler support for instructions which writeback STATUS32.
https://reviews.llvm.org/D45148
Patch by Yan Luo! (Yan.Luo2@synopsys.com)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329404
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Fri, 6 Apr 2018 15:30:02 +0000 (15:30 +0000)]
[llvm-mca] Do not separate iterations with a newline in the timeline view.
Also, update a few tests to minimize the diff in D45369.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329403
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 15:28:26 +0000 (15:28 +0000)]
[CostModel][X86] Regenerate integer extension/truncation cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329402
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 15:23:26 +0000 (15:23 +0000)]
[CostModel][X86] Regenerate integer division/remainder tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329401
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 15:14:34 +0000 (15:14 +0000)]
[CostModel][X86] Regenerate vector shift cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329400
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 15:12:36 +0000 (15:12 +0000)]
[CostModel][X86] Regenerate int<->fp cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329398
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Preobrazhensky [Fri, 6 Apr 2018 15:08:42 +0000 (15:08 +0000)]
[AMDGPU][MC][GFX9] Added s_dcache_discard* instructions
See bug 36838: https://bugs.llvm.org/show_bug.cgi?id=36838
Differential Revision: https://reviews.llvm.org/D45247
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329397
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Fri, 6 Apr 2018 13:57:21 +0000 (13:57 +0000)]
[LoopUnroll] Make LoopPeeling respect the AllowPeeling preference.
The SimpleLoopUnrollPass isn't suppose to perform loop peeling.
Differential Revision: https://reviews.llvm.org/D45334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329395
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Pfaffe [Fri, 6 Apr 2018 13:39:16 +0000 (13:39 +0000)]
Followup for r329293: Temporarily disable the breaking test on windows.
This test is failing on windows bots. Disable it temporarily to unbreak
the windows bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329393
91177308-0d34-0410-b5e6-
96231b3b80d8
Pavel Labath [Fri, 6 Apr 2018 13:34:12 +0000 (13:34 +0000)]
DWARFVerifier: validate information in name index entries
Summary:
This patch add checks to verify that the information in the name index
entries is consistent with the debug_info section. Specifically, we
check that entries point to valid DIEs, and their names, tags, and
compile units match the information in the debug_info sections.
These checks are only run if the previous checks did not find any errors
in the name index headers. Attempting to proceed with the checks anyway
would likely produce a lot of spurious errors and the verification code
would need to be very careful to avoid crashing.
I also add a couple of more checks to the abbreviation-validation code
to verify that some attributes are always present (an index without a
DW_IDX_die_offset attribute is fairly useless).
The entry verification works only on indexes without any type units - I
haven't attempted to extend it to type units, as we don't even have a
DWARF v5-compatible type unit generator at the moment.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329392
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 12:36:27 +0000 (12:36 +0000)]
[UpdateTestChecks] Add update_analyze_test_checks.py for cost model analysis generation
The script allows the auto-generation of checks for cost model tests to speed up their creation and help improve coverage, which will help a lot with PR36550.
If the need arises we can add support for other analyze passes as well, but the cost models was the one I needed to get done - at the moment it just warns that any other analysis mode is unsupported.
I've regenerated a couple of x86 test files to show the effect.
Differential Revision: https://reviews.llvm.org/D45272
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329390
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 11:25:21 +0000 (11:25 +0000)]
[X86][SandyBridge] Add (V)DPPS memory fold latencies
Noticed this during D44654
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329389
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 11:00:51 +0000 (11:00 +0000)]
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds
As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions.
I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent.
As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests...
Differential Revision: https://reviews.llvm.org/D44654
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329388
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Fri, 6 Apr 2018 10:20:19 +0000 (10:20 +0000)]
Tweak an assert message in the verifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329387
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 6 Apr 2018 10:16:36 +0000 (10:16 +0000)]
[X86][SkylakeServer] Merge 2 InstRW entries to the same sched group. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329386
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Fri, 6 Apr 2018 10:14:09 +0000 (10:14 +0000)]
EntryExitInstrumenter: Handle musttail calls
Inserting instrumentation between a musttail call and ret instruction
would create invalid IR. Instead, treat musttail calls as function
exits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329385
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Kazantsev [Fri, 6 Apr 2018 09:47:06 +0000 (09:47 +0000)]
[NFC] Add missing end of line symbols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329383
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Fri, 6 Apr 2018 08:56:25 +0000 (08:56 +0000)]
[MIR] Add support for MachineFrameInfo::LocalFrameSize
MFI.LocalFrameSize was not serialized.
It is usually set from LocalStackSlotAllocation, so if that pass doesn't
run it is impossible do deduce it from the stack objects. Until now, this
information was lost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329382
91177308-0d34-0410-b5e6-
96231b3b80d8
Pavel Labath [Fri, 6 Apr 2018 08:49:57 +0000 (08:49 +0000)]
[debug_loc] Fix typo in DWARFExpression constructor
Summary:
The positions of the DwarfVersion and AddressSize arguments were
reversed, which caused parsing for dwarf opcodes which contained
address-size-dependent operands (such as DW_OP_addr). Amusingly enough,
none of the address-size asserts fired, as dwarf version was always 4,
which is a valid address size.
I ran into this when constructing weird inputs for the DWARF verifier. I
I add a test case as hand-written dwarf -- I am not sure how to trigger
this differently, as having a DW_OP_addr inside a location list is a
fairly non-standard thing to do.
Fixing this error exposed a bug in the debug_loc.dwo parser, which was
always being constructed with an address size of 0. I fix that as well
by following the pattern in the non-dwo parser of picking up the address
size from the first compile unit (which is technically not correct, but
probably good enough in practice).
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329381
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Kazantsev [Fri, 6 Apr 2018 07:23:45 +0000 (07:23 +0000)]
[NFC] Loosen restriction on preheader to fix buildbot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329379
91177308-0d34-0410-b5e6-
96231b3b80d8
Hiroshi Inoue [Fri, 6 Apr 2018 05:41:16 +0000 (05:41 +0000)]
[PowerPC] allow D-form VSX load/store when accessing FrameIndex without offset
VSX D-form load/store instructions of POWER9 require the offset be a multiple of 16 and a helper`isOffsetMultipleOf` is used to check this.
So far, the helper handles FrameIndex + offset case, but not handling FrameIndex without offset case. Due to this, we are missing opportunities to exploit D-form instructions when accessing an object or array allocated on stack.
For example, x-form store (stxvx) is used for int a[4] = {0}; instead of d-form store (stxv). For larger arrays, D-form instruction is not used when accessing the first 16-byte. Using D-form instructions reduces register pressure as well as instructions.
Differential Revision: https://reviews.llvm.org/D45079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329377
91177308-0d34-0410-b5e6-
96231b3b80d8
Robert Widmann [Fri, 6 Apr 2018 04:02:39 +0000 (04:02 +0000)]
[LLVM-C] Fill Out LLVMCallConv
Summary: Bring LLVMCallConv up to date with latest [[ http://llvm.org/doxygen/CallingConv_8h_source.html | CallConv ]]
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45347
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329373
91177308-0d34-0410-b5e6-
96231b3b80d8
Robert Widmann [Fri, 6 Apr 2018 02:31:29 +0000 (02:31 +0000)]
[LLVM-C] Audit Inline Assembly APIs for Consistency
Summary:
- Add a missing getter for module-level inline assembly
- Add a missing append function for module-level inline assembly
- Deprecate LLVMSetModuleInlineAsm and replace it with LLVMSetModuleInlineAsm2 which takes an explicit length parameter
- Deprecate LLVMConstInlineAsm and replace it with LLVMGetInlineAsm, a function that allows passing a dialect and is not mis-classified as a constant operation
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329369
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Fri, 6 Apr 2018 01:21:48 +0000 (01:21 +0000)]
Update method names in documentation.
They were renamed in r328848.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329368
91177308-0d34-0410-b5e6-
96231b3b80d8
Manoj Gupta [Thu, 5 Apr 2018 23:23:29 +0000 (23:23 +0000)]
Fix lld-x86_64-darwin13 build fails.
Use double braces in std::array initialization
to keep Darwin builders happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329363
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 5 Apr 2018 23:21:15 +0000 (23:21 +0000)]
[InstCombine] FP: Z - (X - Y) --> Z + (Y - X)
This restores what was lost with rL73243 but without
re-introducing the bug that was present in the old code.
Note that we already have these transforms if the ops are
marked 'fast' (and I assume that's happening somewhere in
the code added with rL170471), but we clearly don't need
all of 'fast' for these transforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329362
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 5 Apr 2018 22:56:54 +0000 (22:56 +0000)]
[InstCombine] add FP tests for Z - (X - Y); NFC
A fold for this pattern was removed at rL73243 to fix PR4374:
https://bugs.llvm.org/show_bug.cgi?id=4374
...and apparently there were no tests that went with that fold.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329360
91177308-0d34-0410-b5e6-
96231b3b80d8
Manoj Gupta [Thu, 5 Apr 2018 22:47:25 +0000 (22:47 +0000)]
Attempt to fix Mips breakages.
Summary:
Replace ArrayRefs by actual std::array objects so that there are
no dangling references.
Reviewers: rsmith, gkistanova
Subscribers: sdardis, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D45338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329359
91177308-0d34-0410-b5e6-
96231b3b80d8
Zvi Rackover [Thu, 5 Apr 2018 21:57:20 +0000 (21:57 +0000)]
X86 Tests: Add a case for combining sdiv by a splatted pow2 negative. NFC.
Noticed test was missing while working on D42479.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329356
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 5 Apr 2018 21:56:55 +0000 (21:56 +0000)]
[RuntimeDyld][PowerPC] Add a test case for r329335.
Checks that calls to different sections go to the function's global entry point,
rather than the local one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329355
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 5 Apr 2018 21:56:19 +0000 (21:56 +0000)]
[X86] Separate CDQ and CDQE in the scheduler model.
According to Agner's data, CDQE is closer to CWDE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329354
91177308-0d34-0410-b5e6-
96231b3b80d8
Mandeep Singh Grang [Thu, 5 Apr 2018 21:52:24 +0000 (21:52 +0000)]
[IR] Change std::sort to llvm::sort in response to r327219
r327219 added wrappers to std::sort which randomly shuffle the container before
sorting. This will help in uncovering non-determinism caused due to undefined
sorting order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of
std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to
llvm::sort. Refer D44363 for a list of all the required patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329353
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 5 Apr 2018 21:40:32 +0000 (21:40 +0000)]
[X86] Add MOVZPQILo2PQIrr to the Sandy Bridge scheduler model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329351
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 5 Apr 2018 21:37:17 +0000 (21:37 +0000)]
[InstCombine] nsz: -(X - Y) --> Y - X
This restores part of the fold that was removed with rL73243 (PR4374).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329350
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Thu, 5 Apr 2018 21:34:59 +0000 (21:34 +0000)]
[InstCombine][NFC] Regenerate select-of-bittest.ll with instnamer pass
As requested by spatel in https://reviews.llvm.org/D45329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329349
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Thu, 5 Apr 2018 21:34:53 +0000 (21:34 +0000)]
[InstCombine] [NFC] Add more tests for getting rid of select of bittest (D45108, PR36950 / PR17564)
Summary:
More tests for D45108:
* One use tests
* allow shift to be a variable, too
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329348
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 5 Apr 2018 21:16:26 +0000 (21:16 +0000)]
[X86] Add LEAVE instruction to the scheduler models using the same data as LEAVE64. Make LEAVE/LEAVE64 more correct on Sandy Bridge.
This is the 32-bit mode version of LEAVE64. It should be at least somewhat similar to LEAVE64.
The Sandy Bridge version was missing a load port use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329347
91177308-0d34-0410-b5e6-
96231b3b80d8
Wolfgang Pieb [Thu, 5 Apr 2018 21:01:49 +0000 (21:01 +0000)]
[DWARF v5][NFC]: Refactor DebugRnglists to prepare for the support of the DW_AT_ranges
attribute in conjunction with .debug_rnglists.
Reviewers: JDevlieghere
Differential Revision: https://reviews.llvm.org/D45307
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329345
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 5 Apr 2018 21:01:21 +0000 (21:01 +0000)]
[X86][SSE] Add floating point add/mul fast-math vector.reduce tests
Strict versions aren't working at all (PR36732) and the accumulators aren't supported (PR36734)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329344
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 5 Apr 2018 20:54:55 +0000 (20:54 +0000)]
[X86][SSE] Add floating point min/max vector.reduce tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329343
91177308-0d34-0410-b5e6-
96231b3b80d8
Konstantin Zhuravlyov [Thu, 5 Apr 2018 20:46:04 +0000 (20:46 +0000)]
AMDGPU/Metadata: Always report a fixed number of hidden arguments
Currently it is 6. If the "feature" was not used, report dummy
hidden argument. Otherwise it does not match the kernarg size
reported in the kernel header.
Differential Revision: https://reviews.llvm.org/D45129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329341
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 5 Apr 2018 20:04:06 +0000 (20:04 +0000)]
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329339
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Moroz [Thu, 5 Apr 2018 19:43:24 +0000 (19:43 +0000)]
[llvm-cov] Prevent llvm-cov from hanging when a symblink doesn't exist.
Summary:
Previous code hangs indefinitely when trying to iterate through a
symbol link file that points to an non-exist directory. This change
fixes the bug to make the addCollectedPath function exit ealier and
print out correct warning messages.
Patch by Yuke Liao (@liaoyuke).
Reviewers: Dor1s, vsk
Reviewed By: vsk
Subscribers: bruno, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D44960
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329338
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 5 Apr 2018 19:37:05 +0000 (19:37 +0000)]
[RuntimeDyld][PowerPC] Use global entry points for calls between sections.
Functions in different objects may use different TOCs, so calls between such
functions should use the global entry point of the callee which updates the
TOC pointer.
This should fix a bug that the Numba developers encountered (see
https://github.com/numba/numba/issues/2451).
Patch by Olexa Bilaniuk. Thanks Olexa!
No RuntimeDyld checker test case yet as I am not familiar enough with how
RuntimeDyldELF fixes up call-sites, but I do not want to hold up landing
this. I will continue to work on it and see if I can rope some powerpc
experts in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329335
91177308-0d34-0410-b5e6-
96231b3b80d8
Mandeep Singh Grang [Thu, 5 Apr 2018 19:27:04 +0000 (19:27 +0000)]
[Bitcode] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: pcc, mehdi_amini, dexonsmith
Reviewed By: dexonsmith
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45132
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329334
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Neilson [Thu, 5 Apr 2018 18:51:45 +0000 (18:51 +0000)]
[InstCombine] Properly change GEP type when reassociating loop invariant GEP chains
Summary:
This is a fix to PR37005.
Essentially, rL328539 ([InstCombine] reassociate loop invariant GEP chains to enable LICM) contains a bug
whereby it will convert:
%src = getelementptr inbounds i8, i8* %base, <2 x i64> %val
%res = getelementptr inbounds i8, <2 x i8*> %src, i64 %val2
into:
%src = getelementptr inbounds i8, i8* %base, i64 %val2
%res = getelementptr inbounds i8, <2 x i8*> %src, <2 x i64> %val
By swapping the index operands if the GEPs are in a loop, and %val is loop variant while %val2
is loop invariant.
This fix recreates new GEP instructions if the index operand swap would result in the type
of %src changing from vector to scalar, or vice versa.
Reviewers: sebpop, spatel
Reviewed By: sebpop
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329331
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 5 Apr 2018 18:38:45 +0000 (18:38 +0000)]
[X86] Synchronize the SchedRW on some EVEX instructions with their VEX equivalents.
Mostly vector load, store, and move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329330
91177308-0d34-0410-b5e6-
96231b3b80d8
Mandeep Singh Grang [Thu, 5 Apr 2018 18:31:50 +0000 (18:31 +0000)]
[ARM] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: t.p.northover, RKSimon, MatzeB, bkramer
Reviewed By: bkramer
Subscribers: javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D44855
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329329
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 5 Apr 2018 18:20:14 +0000 (18:20 +0000)]
[X86] Disassembler support for having an ADSIZE prefix affect instructions with 0xf2 and 0xf3 prefixes.
Needed to support umonitor from D45253.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329327
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Thu, 5 Apr 2018 18:18:12 +0000 (18:18 +0000)]
[llvm-pdbutil] Display types from MSVC precompiled header object files.
These appear in a .debug$P section, which is exactly the same in
format as a .debug$T section. So we shouldn't ignore these when
dumping types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329326
91177308-0d34-0410-b5e6-
96231b3b80d8
Konstantin Zhuravlyov [Thu, 5 Apr 2018 18:16:02 +0000 (18:16 +0000)]
llvm-exegesis: Fix unittests include dirs when llvm is a part of another project
When llvm is a part of another project (i.e. opencl),
CMAKE_SOURCE_DIR and CMAKE_BINARY_DIR are pointing to
the parent project, which lead to build failures.
Differential Revision: https://reviews.llvm.org/D45328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329325
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 5 Apr 2018 17:40:51 +0000 (17:40 +0000)]
[InstCombine] add test for fneg+fsub with nsz; NFC
There used to be a fold that would handle this case more generally,
but it was removed at rL73243 to fix PR4374:
https://bugs.llvm.org/show_bug.cgi?id=4374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329322
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 5 Apr 2018 17:37:35 +0000 (17:37 +0000)]
[X86][SSE] Add integer add/mul vector.reduce tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329321
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 5 Apr 2018 17:29:51 +0000 (17:29 +0000)]
[X86][SSE] Add integer and/or/xor vector.reduce tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329320
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 5 Apr 2018 17:25:40 +0000 (17:25 +0000)]
[X86][SSE] Add integer min/max vector.reduce tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329319
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Pfaffe [Thu, 5 Apr 2018 17:20:45 +0000 (17:20 +0000)]
Another fix for r329293: Unbreak the windows bots
Only build the unittest if plugins are enabled. Link components into the
TestPlugin on windows and cygwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329318
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 5 Apr 2018 17:06:45 +0000 (17:06 +0000)]
[InstCombine] use pattern matchers for fsub --> fadd folds
This allows folding for vectors with undef elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329316
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Thu, 5 Apr 2018 17:01:39 +0000 (17:01 +0000)]
[WebAssembly] Allow for the creation of user-defined custom sections
This patch adds a way for users to create their own custom sections to
be added to wasm files. At the LLVM IR layer, they are defined through
the "wasm.custom_sections" named metadata. The expected use case for
this is bindings generators such as wasm-bindgen.
Patch by Dan Gohman
Differential Revision: https://reviews.llvm.org/D45297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329315
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 5 Apr 2018 16:51:09 +0000 (16:51 +0000)]
[InstCombine] add tests for fsub --> fadd; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329313
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Thu, 5 Apr 2018 16:42:32 +0000 (16:42 +0000)]
[documentation][llvm-mca] Update the documentation.
Scheduling models can now describe processor register files and retire control
units. This updates the existing documentation and the README file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329311
91177308-0d34-0410-b5e6-
96231b3b80d8