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Justin Bogner [Mon, 28 Aug 2017 23:38:12 +0000 (23:38 +0000)]
[sanitizer-coverage] Clean up trailing whitespace. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311954
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Juergen Ributzka [Mon, 28 Aug 2017 23:24:03 +0000 (23:24 +0000)]
Revert "Fix cmake check for futimens when deploying to earlier macOS releases."
This reverts r311949. The ARM bots don't like it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311953
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Adrian Prantl [Mon, 28 Aug 2017 23:07:43 +0000 (23:07 +0000)]
Fix a logic error in DwarfExpression::addMachineReg()
This fixes PR34323 and thus splitting undescribable registers into
smaller, describable sub-registers.
https://bugs.llvm.org/show_bug.cgi?id=34323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311951
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Juergen Ributzka [Mon, 28 Aug 2017 23:04:38 +0000 (23:04 +0000)]
Fix cmake check for futimens when deploying to earlier macOS releases.
macOS 10.13 added a new API (futimens). This API is only available on macOS 10.13
and later, but the cmake check we have in place only tests if the symbol is
present and ignores the availability attribute. Luckily we have new warning for
this and by making this warning an error the cmake check will return the correct
result.
See also rdar://problem/
33992750.
Differential Revision: https://reviews.llvm.org/D37027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311949
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Adam Nemet [Mon, 28 Aug 2017 23:00:13 +0000 (23:00 +0000)]
Remove an unnecessary const_cast.
I think that this is dating back to when emit used to take a const reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311948
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Marek Sokolowski [Mon, 28 Aug 2017 22:58:31 +0000 (22:58 +0000)]
[llvm-rc] Add ACCELERATORS parsing ability. (parser, pt 3/8).
This improves the current llvm-rc parser by the ability of parsing
ACCELERATORS statement.
Moreover, some small improvements to the original parsing commit
were made.
Thanks for Nico Weber for his original work in this area.
Differential Revision: https://reviews.llvm.org/D36894
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311946
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Evandro Menezes [Mon, 28 Aug 2017 22:51:52 +0000 (22:51 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Add new predicate to more accurately model the scheduling around branches
and function calls and of loads and stores of pairs and integer
multiplications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311944
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Evandro Menezes [Mon, 28 Aug 2017 22:51:32 +0000 (22:51 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Add new predicate to more accurately model the cost of arithmetic and
logical operations shifted left.
Differential revision: https://reviews.llvm.org/D37151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311943
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Kamil Rytarowski [Mon, 28 Aug 2017 22:13:52 +0000 (22:13 +0000)]
Define NetBSD/amd64 ASAN Shadow Offset
Summary:
Catch up after compiler-rt changes and define kNetBSD_ShadowOffset64
as (1ULL << 46).
Sponsored by <The NetBSD Foundation>
Reviewers: kcc, joerg, filcab, vitalybuka, eugenis
Reviewed By: eugenis
Subscribers: llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D37234
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311941
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Craig Topper [Mon, 28 Aug 2017 22:00:27 +0000 (22:00 +0000)]
[InstCombine] Teach select01 helper of foldSelectIntoOp to handle vector splats
We were handling some vectors in foldSelectIntoOp, but not if the operand of the bin op was any kind of vector constant. This patch fixes it to treat vector splats the same as scalars.
Differential Revision: https://reviews.llvm.org/D37232
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311940
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Marek Sokolowski [Mon, 28 Aug 2017 21:59:54 +0000 (21:59 +0000)]
[llvm-rc] Add ICON and HTML parsing ability (parser, pt 2/8).
This extends the current llvm-rc parser by ICON and HTML resources.
Moreover, some tests have been slightly rewritten.
Thanks for Nico Weber for his original work in this area.
Differential Revision: https://reviews.llvm.org/D36891
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311939
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Sanjay Patel [Mon, 28 Aug 2017 21:14:26 +0000 (21:14 +0000)]
[InstCombine] add tests to show failure of SimplifyDemandedVectorElts + shuffle combining; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311934
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Geoff Berry [Mon, 28 Aug 2017 20:48:43 +0000 (20:48 +0000)]
[AArch64][Falkor] Avoid generating STRQro* instructions
Summary:
STRQro* instructions are slower than the alternative ADD/STRQui expanded
instructions on Falkor, so avoid generating them unless we're optimizing
for code size.
Reviewers: t.p.northover, mcrosier
Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D37020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311931
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Davide Italiano [Mon, 28 Aug 2017 20:29:33 +0000 (20:29 +0000)]
[LoopUnroll] Properly update loop structure in case of successful peeling.
When peeling kicks in, it updates the loop preheader.
Later, a successful full unroll of the loop needs to update a PHI
which i-th argument comes from the loop preheader, so it'd better look
at the correct block. Fixes PR33437.
Differential Revision: https://reviews.llvm.org/D37153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311922
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Joerg Sonnenberger [Mon, 28 Aug 2017 20:20:47 +0000 (20:20 +0000)]
Fix ARMv4 support
ARMv4 doesn't support the "BX" instruction, which has been introduced
with ARMv4t. Adjust the call lowering and tail call implementation
accordingly.
Further changes are necessary to ensure that presence of the v4t feature
is correctly set. Most importantly, the "generic" CPU for thumb-*
triples should include ARMv4t, since thumb mode without thumb support
would naturally be pointless.
Add a couple of asserts to ensure thumb instructions are not emitted
without CPU support.
Differential Revision: https://reviews.llvm.org/D37030
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311921
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Matthias Braun [Mon, 28 Aug 2017 20:11:28 +0000 (20:11 +0000)]
Try to fix compilation problem with libstdc++
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311918
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Matthias Braun [Mon, 28 Aug 2017 20:11:27 +0000 (20:11 +0000)]
Address r311914 review comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311917
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Davide Italiano [Mon, 28 Aug 2017 19:50:55 +0000 (19:50 +0000)]
[LoopUnroll] Add a cl::opt to force peeling, for testing purposes.
Will be used to test the patch proposed in D37153.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311915
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Matthias Braun [Mon, 28 Aug 2017 19:48:42 +0000 (19:48 +0000)]
TableGen: Fix subreg composition/concatenation
This fixes 2 problems in subregister hierarchies with multiple levels
and tuples:
1) For bigger tuples computing secondary subregs would miss 2nd order
effects. In the test case a register like `S10_S11_S12_S13_S14` with D5
= S10_S11, D6 = S12_S13 we would correctly compute sub0 = D5, sub1 = D6
but would miss the fact that we could now form ssub0_ssub1_ssub2_ssub3
(aka sub0_sub1) = D5_D6. This is fixed by changing
computeSecondarySubRegs() to compute a fixpoint.
2) Fixing 1) exposed a problem where TableGen would create multiple
names for effectively the same subregister index. In the test case
the subregister index sub0 is composed from ssub0 and ssub1, and sub1 is
composed from ssub2 and ssub3. TableGen should not create both sub0_sub1
and ssub0_ssub1_ssub2_ssub3 as infered subregister indexes. This changes
the code to build a transitive closure of the subregister components
before forming new concatenated subregister indexes.
This fix was developed for an out of tree target. For the in-tree
targets the only change is in the register information computed for ARM.
There is a slight chance this fixed/improved some register coalescing
around the QQQQ/QQ register classes there but I couldn't see/provoke any
code generation differences.
Differential Revision: https://reviews.llvm.org/D36913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311914
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Matthias Braun [Mon, 28 Aug 2017 19:48:40 +0000 (19:48 +0000)]
TableGen: Add -gen-register-info-debug-dump
Adds a new --gen-register-info-debug-dump mode to tablegen that dumps various register related information:
- List of register classes with super and subclasses
- List of subregister indexes with lanemasks
- List of registers with subregisters
I will use this in an upcoming commit to create a test.
It may also be useful for target developers wanting to get an overview
of all the register related information, esp. the things inferred by
tablegen and not directly visible in the .td file.
Differential Revision: https://reviews.llvm.org/D36911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311913
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Geoff Berry [Mon, 28 Aug 2017 19:03:45 +0000 (19:03 +0000)]
[ARM] Fix bug in ARMLoadStoreOptimizer when kill flags are missing.
Summary:
ARMLoadStoreOpt::FixInvalidRegPairOp() was only checking if one of the
load destination registers to be split overlapped with the base register
if the base register was marked as killed. Since kill flags may not
always be present, this can lead to incorrect code.
This bug was exposed by my MachineCopyPropagation change D30751 breaking
the sanitizer-x86_64-linux-android buildbot.
Also clean up some dead code and add an assert that a register offset is
never encountered by this code, since it does not handle them correctly.
Reviewers: MatzeB, qcolombet, t.p.northover
Subscribers: aemerson, javed.absar, kristof.beyls, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D37164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311907
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Taewook Oh [Mon, 28 Aug 2017 18:57:00 +0000 (18:57 +0000)]
Create PHI node for the return value only when the return value has uses.
Summary:
Currently, a phi node is created in the normal destination to unify the return values from promoted calls and the original indirect call. This patch makes this phi node to be created only when the return value has uses.
This patch is necessary to generate valid code, as compiler crashes with the attached test case without this patch. Without this patch, an illegal phi node that has no incoming value from `entry`/`catch` is created in `cleanup` block.
I think existing implementation is good as far as there is at least one use of the original indirect call. `insertCallRetPHI` creates a new phi node in the normal destination block only when the original indirect call dominates its use and the normal destination block. Otherwise, `fixupPHINodeForNormalDest` will handle the unification of return values naturally without creating a new phi node. However, if there's no use, `insertCallRetPHI` still creates a new phi node even when the original indirect call does not dominate the normal destination block, because `getCallRetPHINode` returns false.
Reviewers: xur, davidxl, danielcdh
Reviewed By: xur
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311906
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Zachary Turner [Mon, 28 Aug 2017 18:49:04 +0000 (18:49 +0000)]
[CodeView] Don't output S_UDT symbols for forward decls.
S_UDT symbols are the debugger's "index" for all the structs,
typedefs, classes, and enums in a program. If any of those
structs/classes don't have a complete declaration, or if there
is a typedef to something that doesn't have a complete definition,
then emitting the S_UDT is unhelpful because it doesn't give
the debugger enough information to do anything useful. On the
other hand, it results in a huge size blow-up in the resulting
PDB, which is exacerbated by an order of magnitude when linking
with /DEBUG:FASTLINK.
With this patch, we drop S_UDT records for types that refer either
directly or indirectly (e.g. through a typedef, pointer, etc) to
a class/struct/union/enum without a complete definition. This
brings us about 50% of the way towards parity with /DEBUG:FASTLINK
PDBs generated from cl-compiled object files.
Differential Revision: https://reviews.llvm.org/D37162
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311904
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Stefan Pintilie [Mon, 28 Aug 2017 18:46:01 +0000 (18:46 +0000)]
[Power9] Add new instructions for floating point status and control registers.
Added the following P9 instructions: mffsce, mffscdrn, mffscdrni, mffscrn,
mffscrni, mffsl
Differential Revision: https://reviews.llvm.org/D37167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311903
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Craig Topper [Mon, 28 Aug 2017 18:44:28 +0000 (18:44 +0000)]
[InstCombine] Call hasNoSignedWrap instead of hasNoUnsignedWrap to get the NSW flag when handling Add in SimplifyDemandedUseBits.
This is a typo from r311789.
This should fix PR34349.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311902
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Krzysztof Parzyszek [Mon, 28 Aug 2017 18:36:21 +0000 (18:36 +0000)]
[Hexagon] Check for potential bank conflicts in post-RA scheduling
Insert artificial edges between loads that could cause a cache bank
conflict.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311901
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Stanislav Mekhanoshin [Mon, 28 Aug 2017 18:00:08 +0000 (18:00 +0000)]
[AMDGPU] Fix regression in AMDGPULibCalls allowing native for doubles
Under -cl-fast-relaxed-math we could use native_sqrt, but f64 was
allowed to produce HSAIL's nsqrt instruction. HSAIL is not here
and we stick with non-existing native_sqrt(double) as a result.
Add check for f64 to not return native functions and also remove
handling of f64 case for fold_sqrt.
Differential Revision: https://reviews.llvm.org/D37223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311900
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Stanislav Mekhanoshin [Mon, 28 Aug 2017 16:35:37 +0000 (16:35 +0000)]
[AMDGPU] computeKnownBitsForTargetNode for 24 bit mul
Differential Revision: https://reviews.llvm.org/D37168
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311896
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Krzysztof Parzyszek [Mon, 28 Aug 2017 16:24:22 +0000 (16:24 +0000)]
[Hexagon] Break up DAG mutations into separate classes, move to subtarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311895
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Krzysztof Parzyszek [Mon, 28 Aug 2017 15:52:54 +0000 (15:52 +0000)]
[Hexagon] Move pre-RA DAG mutations to scheduler constructor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311894
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Craig Topper [Mon, 28 Aug 2017 15:32:50 +0000 (15:32 +0000)]
[X86] Make 128/256-bit extract_subvector Legal instead of Custom. Move combining with BUILD_VECTOR from Legalization to DAG combine
EXTRACT_SUBVECTOR was marked Custom solely so we could combine it with BUILD_VECTOR operations to create smaller BUILD_VECTORS during Legalization. But that sort of combining should really be done by the DAG combiner.
This patch adds the last piece of needed supported DAG combine to handle this. Once that's done we can make the EXTRACT_SUBVECTOR operations Legal.
Differential Revision: https://reviews.llvm.org/D37197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311893
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Craig Topper [Mon, 28 Aug 2017 15:28:33 +0000 (15:28 +0000)]
[DAGCombiner] Teach visitEXTRACT_SUBVECTOR to turn extracts of BUILD_VECTOR into smaller BUILD_VECTORs
Only do this before operations are legalized of BUILD_VECTOR is Legal for the target.
Differential Revision: https://reviews.llvm.org/D37186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311892
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Ilya Biryukov [Mon, 28 Aug 2017 15:12:24 +0000 (15:12 +0000)]
Changed Dockerfiles to install LLVM into /usr/local
Summary:
Previously, the installation path was simply '/'.
Using '/usr/local' would ensure that LLVM installation does not
conflict with software installed via package managers.
Reviewers: mehdi_amini, klimek
Reviewed By: klimek
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311890
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Evgeny Mankov [Mon, 28 Aug 2017 13:39:43 +0000 (13:39 +0000)]
[Support][CommandLine] Add cl::Option::setDefault()
Add abstract virtual method setDefault() to class Option and implement it in its inheritors in order to be able to set all the options to its default values in user's code without actually knowing all these options. For instance:
for (auto &OM : cl::getRegisteredOptions(*cl::TopLevelSubCommand)) {
cl::Option *O = OM.second;
O->setDefault();
}
Reviewed by: rampitec, Eugene.Zelenko, kasaurov
Differential Revision: http://reviews.llvm.org/D36877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311887
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Andrew V. Tischenko [Mon, 28 Aug 2017 10:43:14 +0000 (10:43 +0000)]
The current version of LLVM X86 disassembler incorrectly interprets some possible sets of x86 prefixes. This patch is the first step to close PR7709 and PR17697. There will be next patch(es) to close relative PRs.
Differential Revision: https://reviews.llvm.org/D36788
M lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
M lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
A test/MC/Disassembler/X86/prefixes-i386.s
A test/MC/Disassembler/X86/prefixes-x86_64.s
M test/MC/Disassembler/X86/prefixes.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311882
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Gadi Haber [Mon, 28 Aug 2017 10:04:16 +0000 (10:04 +0000)]
[X86][Haswell] Updating HSW instruction scheduling information
This patch completely replaces the instruction scheduling information for the Haswell architecture target by modifying the file X86SchedHaswell.td located under the X86 Target.
We used the scheduling information retrieved from the Haswell architects in order to replace and modify the existing scheduling.
The patch continues the scheduling replacement effort started with the SNB target in r307529 and r310792.
Information includes latency, number of micro-Ops and used ports by each HSW instruction.
Please expect some performance fluctuations due to code alignment effects.
Reviewers: RKSimon, zvi, aymanmus, craig.topper, m_zuckerman, igorb, dim, chandlerc, aaboud
Differential Revision: https://reviews.llvm.org/D36663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311879
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NAKAMURA Takumi [Mon, 28 Aug 2017 07:48:37 +0000 (07:48 +0000)]
Prune whitespaces in blank lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311876
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NAKAMURA Takumi [Mon, 28 Aug 2017 06:47:47 +0000 (06:47 +0000)]
Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311875
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Craig Topper [Mon, 28 Aug 2017 05:14:38 +0000 (05:14 +0000)]
[X86] Use getUnpackl helper to create an ISD::VECTOR_SHUFFLE instead of using X86ISD::UNPCKL in reduceVMULWidth.
This runs fairly early, we should use target independent nodes if possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311873
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Craig Topper [Mon, 28 Aug 2017 04:29:08 +0000 (04:29 +0000)]
[X86] Add an early out to combineLoopMAddPattern and combineLoopSADPattern when SSE2 is disabled.
Without this the madd.ll and sad.ll test cases both throw assertions if you run them with SSE2 disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311872
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Lang Hames [Mon, 28 Aug 2017 03:36:46 +0000 (03:36 +0000)]
[Error] Add a handleExpected utility.
handleExpected is similar to handleErrors, but takes an Expected<T> as its first
input value and a fallback functor as its second, followed by an arbitary list
of error handlers (equivalent to the handler list of handleErrors). If the first
input value is a success value then it is returned from handleErrors
unmodified. Otherwise the contained error(s) are passed to handleErrors, along
with the handlers. If handleErrors returns success (indicating that all errors
have been handled) then handleExpected runs the fallback functor and returns its
result. If handleErrors returns a failure value then the failure value is
returned and the fallback functor is never run.
This simplifies the process of re-trying operations that return Expected values.
Without this utility such retry logic is cumbersome as the internal Error must
be explicitly extracted from the Expected value, inspected to see if its
handleable and then consumed:
enum FooStrategy { Aggressive, Conservative };
Expected<Foo> tryFoo(FooStrategy S);
Expected<Foo> Result;
(void)!!Result; // "Check" Result so that it can be safely overwritten.
if (auto ValOrErr = tryFoo(Aggressive))
Result = std::move(ValOrErr);
else {
auto Err = ValOrErr.takeError();
if (Err.isA<HandleableError>()) {
consumeError(std::move(Err));
Result = tryFoo(Conservative);
} else
return std::move(Err);
}
with handleExpected, this can be re-written as:
auto Result =
handleExpected(
tryFoo(Aggressive),
[]() { return tryFoo(Conservative); },
[](HandleableError&) { /* discard to handle */ });
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311870
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Dehao Chen [Sun, 27 Aug 2017 22:22:39 +0000 (22:22 +0000)]
revert r310985 which breaks for the following case:
struct string {
~string();
};
void f2();
void f1(int) { f2(); }
void run(int c) {
string body;
while (true) {
if (c)
f1(c);
else
f1(c);
}
}
Will recommit once the issue is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311864
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Petar Jovanovic [Sun, 27 Aug 2017 21:07:24 +0000 (21:07 +0000)]
[mips] Generate NMADD and NMSUB instructions when fneg node is present
This patch enables generation of NMADD and NMSUB instructions when fneg node
is present. These instructions are currently only generated if fsub node is
present.
Patch by Stanislav Ocovaj.
Differential Revision: https://reviews.llvm.org/D34507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311862
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Javed Absar [Sun, 27 Aug 2017 20:38:28 +0000 (20:38 +0000)]
[ARM] Tidy-up condition-code support functions
Move condition code support functions to Utils and remove code duplication.
Reviewed by: @fhahn, @asb
Differential Revision: https://reviews.llvm.org/D37179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311860
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Craig Topper [Sun, 27 Aug 2017 19:03:36 +0000 (19:03 +0000)]
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311856
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Sanjay Patel [Sun, 27 Aug 2017 17:29:30 +0000 (17:29 +0000)]
[DAGCombiner] allow undef shuffle operands when eliminating bitcasts (PR34111)
As noted in the FIXME, this could be improved more, but this is the smallest fix
that helps:
https://bugs.llvm.org/show_bug.cgi?id=34111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311853
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Sanjay Patel [Sun, 27 Aug 2017 17:15:49 +0000 (17:15 +0000)]
[x86] add haddps test for PR34111; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311852
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Javed Absar [Sun, 27 Aug 2017 14:46:57 +0000 (14:46 +0000)]
[ARM] Tidy-up ARMAsmParser. NFC.
Simplify getDRegFromQReg function
Reviewed by: @fhahn, @asb
Differential Revision: https://reviews.llvm.org/D37118
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311850
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Ayal Zaks [Sun, 27 Aug 2017 12:55:46 +0000 (12:55 +0000)]
[LV] Fix PR34248 - recommit D32871 after revert r311304
Original commit r311077 of D32871 was reverted in r311304 due to failures
reported in PR34248.
This recommit fixes PR34248 by restricting the packing of predicated scalars
into vectors only when vectorizing, avoiding doing so when unrolling w/o
vectorizing. Added a test derived from the reproducer of PR34248.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311849
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Jatin Bhateja [Sun, 27 Aug 2017 12:43:25 +0000 (12:43 +0000)]
[X86] Adding more tests for horizontal [F]HADD/[F]SUB for AVX512 vectors types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311847
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Craig Topper [Sun, 27 Aug 2017 05:39:57 +0000 (05:39 +0000)]
[X86] Add a target-specific DAG combine to combine extract_subvector from all zero/one build_vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311841
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Craig Topper [Sun, 27 Aug 2017 03:26:04 +0000 (03:26 +0000)]
[X86] Use getOnesVector instead of using DAG.getConstant(-1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311840
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Davide Italiano [Sat, 26 Aug 2017 22:31:10 +0000 (22:31 +0000)]
[NewGVN] Use `auto` when the type is obvious NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311838
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Craig Topper [Sat, 26 Aug 2017 22:24:57 +0000 (22:24 +0000)]
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine.
We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't.
Add some more test cases to ensure we've also got most of the zero masking covered too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311837
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Don Hinton [Sat, 26 Aug 2017 21:08:51 +0000 (21:08 +0000)]
[Dominators] Remove redundant explicit template instantiation.
Summary:
Remove redundant explicit template instantiation.
This was reported by Andrew Kelley building release_50 with gcc7.2.0 on MacOS: duplicate symbol llvm::DominatorTreeBase.
Reviewers: kuhar, andrewrk, davide, hans
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311835
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Jatin Bhateja [Sat, 26 Aug 2017 19:02:49 +0000 (19:02 +0000)]
[X86] Adding a test for horizontal [f]add/[f]sub for avx512 vector type 16x32.
Differential Revision: https://reviews.llvm.org/D37183
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311834
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Jatin Bhateja [Sat, 26 Aug 2017 19:02:36 +0000 (19:02 +0000)]
[DAGCombiner] Extending pattern detection for vector shuffle.
Summary:
If all the operands of a BUILD_VECTOR extract elements from same vector then split the
vector efficiently based on the maximum vector access index.
This will also fix PR 33784
Reviewers: zvi, delena, RKSimon, thakis
Reviewed By: RKSimon
Subscribers: chandlerc, eladcohen, llvm-commits
Differential Revision: https://reviews.llvm.org/D35788
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311833
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Jatin Bhateja [Sat, 26 Aug 2017 19:02:17 +0000 (19:02 +0000)]
Revert rL311247 : To rectify commit message.
Summary: This reverts commit rL311247.
Differential Revision: https://reviews.llvm.org/D36927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311832
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Daniel Berlin [Sat, 26 Aug 2017 07:37:11 +0000 (07:37 +0000)]
NewGVN: Fix PR33204 - We need to add memory users when we bypass memorydefs for loads, not just when we do it for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311829
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Craig Topper [Sat, 26 Aug 2017 06:24:25 +0000 (06:24 +0000)]
[X86] Qualify the RMW INC/DEC patterns with NotSlowIncDec.
We were suppressing most uses of INC/DEC, but this one seems to have been missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311828
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Petr Hosek [Sat, 26 Aug 2017 03:22:25 +0000 (03:22 +0000)]
Revert "[llvm] Add symbol table support to llvm-objcopy"
This reverts commit r311826 because it's failing on llvm-i686-linux-RA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311827
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Petr Hosek [Sat, 26 Aug 2017 03:18:41 +0000 (03:18 +0000)]
[llvm] Add symbol table support to llvm-objcopy
This change adds support for SHT_SYMTAB sections.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D34167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311826
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Petr Hosek [Sat, 26 Aug 2017 01:32:20 +0000 (01:32 +0000)]
[llvm-objcopy] New layout algorithm that lays out segments first
The current file layout algorithm in llvm-objcopy is simple but
difficult to reason about. It also makes it very complicated to support
nested segments and to support segments that have offsets that come
before a point after the program headers. To support these cases and
simplify one of the most critical parts llvm-objcopy I rewrote the
layout algorithm. Laying out segments first solves most of the issues
encountered by the previous algorithm.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D36494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311825
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Hiroshi Yamauchi [Sat, 26 Aug 2017 00:31:00 +0000 (00:31 +0000)]
Add options to dump block frequency/branch probability info in text.
Summary:
Add options -print-bfi/-print-bpi that dump block frequency and branch
probability info like -view-block-freq-propagation-dags and
-view-machine-block-freq-propagation-dags do but in text.
This is useful when the graph is very large and complex (the dot command
crashes, lines/edges too close to tell apart, hard to navigate without textual
search) or simply when text is preferred.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37165
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311822
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Craig Topper [Fri, 25 Aug 2017 23:34:59 +0000 (23:34 +0000)]
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector.
This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311821
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Craig Topper [Fri, 25 Aug 2017 23:34:57 +0000 (23:34 +0000)]
[AVX512] Add additional test cases for masked extract subvector.
This includes tests for extracting 128-bits from a 256-bit vector and zero masking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311820
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Craig Topper [Fri, 25 Aug 2017 23:34:55 +0000 (23:34 +0000)]
[X86] Add patterns to show more failures to use TBM instructions when we're trying to check flags.
We can probably add patterns to fix some of them. But the ones that use 'and' as their root node emit a X86ISD::CMP node in front of the 'and' and then pattern matching that to 'test' instruction. We can't use a tablegen pattern to fix that because we can't remap the cmp result to the flag output of a TBM instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311819
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Chandler Carruth [Fri, 25 Aug 2017 22:50:52 +0000 (22:50 +0000)]
[x86] Teach the backend to fold more read-modify-write memory operands
to instructions.
These can't be reasonably matched in tablegen due to the handling of
flags, so we have to do this in C++ code. We only did it for `inc` and
`dec` historically, this starts fleshing that out to more interesting
instructions. Notably, this handles transfering operands to `add` and
`sub`.
Currently this forces them into a register. The next patch will add
support for keeping immediate operands as immediates. Then I'll extend
this beyond just `add` and `sub`.
I'm not super thrilled by the repeated switches in the code but
everything else I tried was really ugly or problematic.
Many thanks to Craig Topper for the suggestions about where to even
begin here and how to make this stuff work.
Differential Revision: https://reviews.llvm.org/D37130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311806
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Davide Italiano [Fri, 25 Aug 2017 22:08:15 +0000 (22:08 +0000)]
[Verifier] Diagnose invalid DIType references instead of crashing.
Fixes PR34325.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311805
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Davide Italiano [Fri, 25 Aug 2017 22:01:42 +0000 (22:01 +0000)]
[Inliner] Only compute fully inline cost when remarks are enabled.
Prior to this change (and after r311371), we computed it
unconditionally, causin gsevere compile time regressions (in some
cases, 5 to 10x).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311804
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Matt Morehouse [Fri, 25 Aug 2017 22:01:21 +0000 (22:01 +0000)]
Revert "[SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzer"
This reverts r311801 due to a bot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311803
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Matt Morehouse [Fri, 25 Aug 2017 21:18:29 +0000 (21:18 +0000)]
[SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzer
Summary:
- Don't sanitize __sancov_lowest_stack.
- Don't instrument leaf functions.
- Add CoverageStackDepth to Fuzzer and FuzzerNoLink.
Reviewers: vitalybuka, kcc
Reviewed By: kcc
Subscribers: cfe-commits, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D37156
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311801
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Sanjay Patel [Fri, 25 Aug 2017 19:33:18 +0000 (19:33 +0000)]
[utils] add aarch64 target as an option
I don't know enough to add a custom scrubber for AArch64, so I just re-used ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311795
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Kostya Serebryany [Fri, 25 Aug 2017 19:29:47 +0000 (19:29 +0000)]
[sanitizer-coverage] extend fsanitize-coverage=pc-table with flags for every PC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311794
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Sanjay Patel [Fri, 25 Aug 2017 19:25:03 +0000 (19:25 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311793
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Haicheng Wu [Fri, 25 Aug 2017 19:00:33 +0000 (19:00 +0000)]
[InlineCost] Small changes to early exit condition. NFC.
Change the early exit condition from Cost > Threshold to Cost >= Threshold
because the inline condition is Cost < Threshold.
Differential Revision: https://reviews.llvm.org/D37087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311791
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Craig Topper [Fri, 25 Aug 2017 18:39:40 +0000 (18:39 +0000)]
[InstCombine] Don't fall back to only calling computeKnownBits if the upper bit of Add/Sub is demanded.
Just create an all 1s demanded mask and continue recursing like normal. The recursive calls should be able to handle an all 1s mask and do the right thing.
The only time we should care about knowing whether the upper bit was demanded is when we need to know if we should clear the NSW/NUW flags.
Now that we have a consistent path through the code for all cases, use KnownBits::computeForAddSub to compute the known bits at the end since we already have the LHS and RHS.
My larger goal here is to move the code that turns add into xor if only 1 bit is demanded and no bits below it are non-zero from InstCombiner::OptAndOp to here. This will allow it to be more general instead of just looking for 'add' and 'and' with constant RHS.
Differential Revision: https://reviews.llvm.org/D36486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311789
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Craig Topper [Fri, 25 Aug 2017 17:14:35 +0000 (17:14 +0000)]
[InstCombine] Add tests to show missed opportunities to combine bit tests hidden by a sign compare and a truncate. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311784
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Florian Hahn [Fri, 25 Aug 2017 16:52:29 +0000 (16:52 +0000)]
[LoopInterchange] Skip zext instructions when looking for induction var.
Summary:
SimplifyIndVar may introduce zext instructions to widen arguments of the
loop exit check. They should not prevent us from splitting the loop at
the induction variable, but maybe the check should be more conservative,
e.g. making sure it only extends arguments used by a comparison?
Reviewers: karthikthecool, mcrosier, mzolotukhin
Reviewed By: mcrosier
Subscribers: mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D34879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311783
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David Blaikie [Fri, 25 Aug 2017 16:46:07 +0000 (16:46 +0000)]
Fix unused-lambda-capture warning by using default capture-by-ref
Since the lambda isn't escaped (via a std::function or similar) it's
fine/better to use default capture-by-ref to provide semantics similar
to language-level nested scopes (if/for/while/etc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311782
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Matt Morehouse [Fri, 25 Aug 2017 16:19:26 +0000 (16:19 +0000)]
Fix buildbot breakage from r311763. Remove unused lambda capture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311781
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David Green [Fri, 25 Aug 2017 16:14:56 +0000 (16:14 +0000)]
[gold] Fix up a new test to allow it to pass on non x86 builds.
Fix a test that is failing on a downstream ARM/AArch64
bootstrap. We just need add an elf_x86_64 parameter to
gold.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311780
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Michael Kruse [Fri, 25 Aug 2017 12:38:53 +0000 (12:38 +0000)]
Normlize to LF line endings.
Commit r297442 introduced mixed CRLF/LF line endings to two files.
Normalize to to LF-only line endings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311774
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Amjad Aboud [Fri, 25 Aug 2017 11:07:54 +0000 (11:07 +0000)]
[InstCombine] Consider more cases where SimplifyDemandedUseBits does not convert AShr to LShr.
There are cases where AShr have better chance to be optimized than LShr, especially when the demanded bits are not known to be Zero, and also known to be similar to the sign bit.
Differential Revision: https://reviews.llvm.org/D36936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311773
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Ilya Biryukov [Fri, 25 Aug 2017 09:03:57 +0000 (09:03 +0000)]
Use temporary directory when building docker image.
Summary:
This avoids races on copying of compiled clang from 'build' image
to 'release' image.
Reviewers: klimek, mehdi_amini
Reviewed By: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37098
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311769
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Craig Topper [Fri, 25 Aug 2017 05:36:29 +0000 (05:36 +0000)]
[X86] Use SDValue::getOpcode instead of calling getNode and calling getOpcode on that. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311765
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Craig Topper [Fri, 25 Aug 2017 05:04:34 +0000 (05:04 +0000)]
[X86] Use isUInt and isShiftedUInt instead of using our own masking and compares. NFCI
While there use a local variable instead of calling C->getZExtValue() repeatedly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311764
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Aditya Nandakumar [Fri, 25 Aug 2017 04:57:27 +0000 (04:57 +0000)]
[GISel]: Implement widenScalar for Legalizing G_PHI
https://reviews.llvm.org/D37018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311763
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Chandler Carruth [Fri, 25 Aug 2017 02:32:51 +0000 (02:32 +0000)]
[x86] NFC - normalize test case formatting of IR and generate CHECK
lines with the script rather than using manually written checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311753
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Chandler Carruth [Fri, 25 Aug 2017 02:32:48 +0000 (02:32 +0000)]
Teach the llc check updater to recognize the end-of-function comment
used on Windows and sometimes Darwin. Cleans up generated patterns for
me quite a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311752
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Gor Nishanov [Fri, 25 Aug 2017 02:25:10 +0000 (02:25 +0000)]
[coroutines] Add support for symmetric control transfer (musttail on coro.resumes followed by a suspend)
Summary:
Add musttail to any resume instructions that is immediately followed by a
suspend (i.e. ret). We do this even in -O0 to support guaranteed tail call
for symmetrical coroutine control transfer (C++ Coroutines TS extension).
This transformation is done only in the resume part of the coroutine that has
identical signature and calling convention as the coro.resume call.
Reviewers: GorNishanov
Reviewed By: GorNishanov
Subscribers: EricWF, majnemer, llvm-commits
Differential Revision: https://reviews.llvm.org/D37125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311751
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Chandler Carruth [Fri, 25 Aug 2017 02:06:36 +0000 (02:06 +0000)]
[x86] NFC: More refactoring to pave the way to extending this ISel logic
to handle other x86 pseudos that carry flags and thus can't be matched
by our ISel patterns with fused memory accesses.
Differential Revision: https://reviews.llvm.org/D37088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311749
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Chandler Carruth [Fri, 25 Aug 2017 02:04:03 +0000 (02:04 +0000)]
[x86] NFC - Refactor the custom lowering of `(load; op; store)` RMW sequences.
This extracts the code out of a giant switch in preparation for expanding it to
handle operations other thin `inc` and `dec`. Add a FIXME indicating what's
coming here.
Differential Revision: https://reviews.llvm.org/D37045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311748
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Craig Topper [Fri, 25 Aug 2017 01:59:06 +0000 (01:59 +0000)]
[X86] Add TBM instructions to X86InstrInfo::isDefConvertible.
This allows us to remove "test" instructions and use the flags from the TBM instructions directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311747
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Matt Arsenault [Fri, 25 Aug 2017 01:26:13 +0000 (01:26 +0000)]
DAG: Fix naming crime
Because isOperationCustom was only checking for custom
lowering on illegal types, this was behaving inconsistently
with the other isOperation* functions, so that
isOperationLegalOrCustom != (isOperationLegal || isOperationCustom)
Luckily this is only used in one place which already checks the
type legality on its own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311743
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Justin Bogner [Fri, 25 Aug 2017 01:24:54 +0000 (01:24 +0000)]
[sanitizer-coverage] Make sure pc-tables aren't dead stripped
Add a reference to the PC array in llvm.used so that linkers that
aggressively dead strip (like ld64) don't remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311742
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Mandeep Singh Grang [Fri, 25 Aug 2017 01:11:28 +0000 (01:11 +0000)]
[unittests] Remove reverse iteration tests which use pointer-like keys
Summary: The expected order of pointer-like keys is hash-function-dependent which in turn depends on the platform/environment. Need to come up with a better way to test reverse iteration of containers with pointer-like keys.
Reviewers: dblaikie, mehdi_amini, efriedma, mgrang
Reviewed By: mgrang
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311741
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Chandler Carruth [Fri, 25 Aug 2017 00:56:05 +0000 (00:56 +0000)]
[x86] Back out one aspect of r311318: don't generically set
FeatureSlowUAMem32.
The idea was to mark things that are slow on widely available processors
as slow in the generic CPU so that the code generated for that CPU would
be fast across those processors. However, for this feature that doesn't
work out very well at all.
The problem here is that you can very easily enable AVX or AVX2 on top
of this generic CPU. For example, this can happen just by using AVX2
intrinsics from Clang within a region of code guarded by a dynamic CPU
feature test. When you do that, the generated code with SlowUAMem32 set
is ... amazingly slower. The problem is that there really aren't very
good alternatives to the unaligned loads, and so our vector codegen
regresses significantly.
The other issue is that there are plenty of AMD CPUs with AVX1 that
don't set FeatureSlowUAMem32 and so we shouldn't just check for AVX2
instead of this special feature. =/
It would be nice to have the target attriute logic be able to
enable/disable more than just one feature at a time and control this in
a more fine grained and useful way, but that doesn't seem easy. Given
that it is only Sandybridge and Ivybridge that set this feature, for now
I'm just backing it out of the generic CPU. That has the additional
advantage of going back to the previous state that people seemed vaguely
happy with.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311740
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Stephen Hines [Fri, 25 Aug 2017 00:48:21 +0000 (00:48 +0000)]
Fix two (three) more issues with unchecked Error.
Summary:
If assertions are disabled, but LLVM_ABI_BREAKING_CHANGES is enabled,
this will cause an issue with an unchecked Success. Switching to
consumeError() is the correct way to bypass the check. This patch also
includes disabling 2 tests that can't work without assertions enabled,
since llvm_unreachable() with NDEBUG won't crash.
Reviewers: llvm-commits, lhames
Reviewed By: lhames
Subscribers: lhames, pirama
Differential Revision: https://reviews.llvm.org/D36729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311739
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Chandler Carruth [Fri, 25 Aug 2017 00:34:07 +0000 (00:34 +0000)]
[x86] Fix an amazing goof in the handling of sub, or, and xor lowering.
The comment for this code indicated that it should work similar to our
handling of add lowering above: if we see uses of an instruction other
than flag usage and store usage, it tries to avoid the specialized
X86ISD::* nodes that are designed for flag+op modeling and emits an
explicit test.
Problem is, only the add case actually did this. In all the other cases,
the logic was incomplete and inverted. Any time the value was used by
a store, we bailed on the specialized X86ISD node. All of this appears
to have been historical where we had different logic here. =/
Turns out, we have quite a few patterns designed around these nodes. We
should actually form them. I fixed the code to match what we do for add,
and it has quite a positive effect just within some of our test cases.
The only thing close to a regression I see is using:
notl %r
testl %r, %r
instead of:
xorl -1, %r
But we can add a pattern or something to fold that back out. The
improvements seem more than worth this.
I've also worked with Craig to update the comments to no longer be
actively contradicted by the code. =[ Some of this still remains
a mystery to both Craig and myself, but this seems like a large step in
the direction of consistency and slightly more accurate comments.
Many thanks to Craig for help figuring out this nasty stuff.
Differential Revision: https://reviews.llvm.org/D37096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311737
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