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Nicholas Kazlauskas [Mon, 25 Mar 2019 16:06:23 +0000 (12:06 -0400)]
drm/amd/display: Update plane scaling parameters for fast updates
[Why]
Plane scaling parameters are not correctly filled or updated when
performing fast updates.
They're filled when creating the dc plane state and during atomic check.
While the atomic check code path happens for the plane even during fast
updates, the issue is that they're done in place on the dc_plane_state
directly. This dc_plane_state may be the current state plane state
being used by the hardware, so these parameters won't be correctly
programmed.
The new scaling parameters should instead be passed as an update
to the plane.
[How]
Update fill_rects_from_plane_state to not modify dc_plane_state
directly. Update the call sites that use this to fill in the appropriate
values.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Fri, 29 Mar 2019 20:27:50 +0000 (16:27 -0400)]
drm/amd/display: 3.2.26
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Tue, 26 Mar 2019 00:33:35 +0000 (20:33 -0400)]
drm/amd/display: Read eDP link settings on detection
[Why]
Unlike external DP panels, internal eDP does not perform
verify link caps because the panel connection is fixed.
So if GOP enabled the eDP at boot, we can retain its
trained link settings to optimize.
[How]
Read the lane count and link rate by reading this
information from DPCD 100h, 101h, 115h
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Thu, 28 Mar 2019 20:49:42 +0000 (16:49 -0400)]
drm/amd/display: define HUBP_MASK_SH_LIST_DCN for Raven
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Francis [Mon, 25 Mar 2019 13:44:04 +0000 (09:44 -0400)]
drm/amd/display: Handle get crtc position error
[Why]
dc_stream_get_crtc_position can return false.
This was unhandled in delay_cursor_until_vupdate
[How]
If dc_stream_get_crtc_position returns false, something
is weird. Don't delay.
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Tue, 26 Mar 2019 21:32:59 +0000 (17:32 -0400)]
drm/amd/display: expand plane caps to include fp16 and scaling capability
[why]
there are some scaling capabilities such as fp16 which are known to be unsupported
on a given ASIC. exposing these static capabilities allows much simpler implementation
for OS interfaces which require to report such static capabilities to reduce the
number of dynamic validation calls
[how]
refactor the existing plane caps to be more extensible, and add fp16 and scaling
capabilities
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 15 Mar 2019 19:55:43 +0000 (15:55 -0400)]
drm/amd/display: Add DRM color properties for primary planes
[Why]
We need DC's color space to match the color encoding and color space
specified by userspace to correctly render YUV surfaces.
[How]
Add the DRM color properties when the DC plane supports NV12.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 15 Mar 2019 19:45:34 +0000 (15:45 -0400)]
drm/amd/display: Expose support for NV12 on suitable planes
[Why]
Hardware can support video surfaces and DC tells us which planes are
suitable via DC plane caps.
[How]
The supported formats array will now vary based on what DC tells us,
so create an array and fill it dynamically based on plane types and
caps.
Ideally we'd query support for every format via DC plane caps, but for
the framework is in place to do so later with this.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Thu, 28 Mar 2019 16:39:48 +0000 (12:39 -0400)]
drm/amd/display: Add switch for Fractional PWM on or off
[Why]
Some LED Driver might not like Fractional PWM especially at extreme
ranges near 0% or 100%.
For example, backlight flashing could be observed.
We want a way to switch fractional PWM on/off either for debug, or
possibly production.
[How]
Add DC code that can send new FW command to enable/disable
fractional PWM.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
shaoyunl [Fri, 5 Apr 2019 15:55:27 +0000 (11:55 -0400)]
drm/amdgpu: Set proper function to set xgmi pstate
Driver need to call SMU to set xgmi pstate
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
shaoyunl [Thu, 11 Apr 2019 15:01:07 +0000 (11:01 -0400)]
drm/powerplay: Add smu set xgmi pstate interface
XGMI pstate is controlled by SMU, driver need this interface to communicate
with SMU
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 29 Mar 2019 18:30:23 +0000 (19:30 +0100)]
drm/amdgpu: fix old fence check in amdgpu_fence_emit
We don't hold a reference to the old fence, so it can go away
any time we are waiting for it to signal.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 1 Apr 2019 09:51:03 +0000 (17:51 +0800)]
drm/amdgpu: update version for timeline syncobj support in amdgpu v2
v2: update version for amd-staging-drm-next merge
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 1 Apr 2019 09:51:00 +0000 (17:51 +0800)]
drm/amdgpu: add timeline support in amdgpu CS v3
syncobj wait/signal operation is appending in command submission.
v2: separate to two kinds in/out_deps functions
v3: fix checking for timeline syncobj
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Cc: Tobias Hector <Tobias.Hector@amd.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Fri, 12 Apr 2019 04:46:10 +0000 (14:46 +1000)]
Merge branch 'drm-next-5.2' of git://people.freedesktop.org/~agd5f/linux into drm-next
- Fixes for powerplay custom profiles
- DC bandwidth clean ups and fixes
- RAS fixes for vega20
- DC atomic resume fix
- Better plane handling in DC
- Freesync improvements
- Misc bug fixes and cleanups
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190411031242.3337-1-alexander.deucher@amd.com
Dave Airlie [Fri, 12 Apr 2019 04:27:37 +0000 (14:27 +1000)]
Merge tag 'drm-misc-next-2019-04-10' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for 5.2:
UAPI Changes:
- None
Cross-subsystem Changes:
-MAINTAINERS: Add moderation flag for lima mailing list (Randy)
-dt-bindings: Add Mali Bifrost bindings (Neil)
-dt-bindings: Add G12A compatibility strings to meson bindings (Neil)
Core Changes:
-Add a handful of format helpers (Gerd)
Driver Changes:
-cirrus: Driver rewrite megapatch (Gerd)
-meson: Add G12A support to meson driver (Neil)
-lima: Couple fixes (Qiang)
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Sean Paul <sean@poorly.run>
Link: https://patchwork.freedesktop.org/patch/msgid/20190410194907.GA108842@art_vandelay
Dmytro Laktyushkin [Tue, 26 Mar 2019 17:26:37 +0000 (13:26 -0400)]
drm/amd/display: fix is odm head pipe logic
Simply return true/false, don't iterate up the tree.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 14 Mar 2019 19:58:51 +0000 (15:58 -0400)]
drm/amd/display: Pass plane caps into amdgpu_dm_plane_init
[Why]
When deciding to add properties or expose formats on DRM planes we
should be querying the caps for the DC plane it's supposed to represent.
[How]
Pass plane caps down into plane initialization, refactoring overlay
plane initialization to have the overlay plane be represented by
the first overlay capable DC plane.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Li [Wed, 20 Mar 2019 13:52:14 +0000 (09:52 -0400)]
drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()
[Why]
dcn*_disable_plane() doesn't unlock the pipe anymore, making the extra
lock unnecessary.
In addition - during full plane updates - all necessary pipes should be
locked/unlocked together when modifying hubp to avoid tearing in
pipesplit setups.
[How]
Remove redundant locks, and add function to lock all pipes. If an
interdependent pipe update is required, lock down all pipes. Otherwise,
lock only the top pipe for the updated pipe tree.
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Li [Tue, 19 Mar 2019 23:29:16 +0000 (19:29 -0400)]
drm/amd/display: Recreate private_obj->state during S3 resume
[Why]
When entering S3, amdgpu first calls DRM to cache the current atomic
state, then commit the 'all-disabled' state. This sets dc->current_state
to point at the private atomic object's dm_atomic_state->context, as
any regular atomic commit would.
Afterwards, amdgpu_dm calls dc_set_power_state() with S3 power state.
This invalidates dc->current_state by wiping it to 0, consequently
wiping dm_atomic_state->context.
During resume, the cached atomic state is restored. When getting the
private object however, the dm_atomic_state - containing the wiped
context - is duplicated into the atomic state. This causes DC validation
to fail during atomic check, as necessary function pointers in dc_state
are now NULL.
[How]
Recreate the private object's dm_atomic_state->context during resume,
restoring any static values such as function pointers.
A TODO item is added to move static read-only values out of dc_state -
they shouldn't be there anyways.
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Murton Liu [Mon, 25 Mar 2019 18:51:28 +0000 (14:51 -0400)]
drm/amd/display: HDR visual confirmation incorrectly reports black color
[Why]
Checking against a TF that is unused causes us to default to black
[How]
Check against PQ instead
Signed-off-by: Murton Liu <murton.liu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Mon, 25 Mar 2019 20:11:43 +0000 (16:11 -0400)]
drm/amd/display: fix underflow on boot
[Why]
New seamless boot sequence introduced a bug where front end is disabled
without blanking otg.
[How]
Adjust the condition of blanking otg to match seamless boot.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Mon, 25 Mar 2019 18:30:12 +0000 (14:30 -0400)]
drm/amd/display: disable link before changing link settings
[Why]
If link is already enabled at a different rate (for example 5.4 Gbps)
then calling VBIOS command table to switch to a new rate
(for example 2.7 Gbps) will not take effect.
This can lead to link training failure to occur.
[How]
If the requested link rate is different than the current link rate,
the link must be disabled in order to re-enable at the new
link rate.
In today's logic it is currently only impacting eDP since DP
connection types will always disable the link during display
detection, when initial link verification occurs.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sat, 23 Mar 2019 17:46:40 +0000 (13:46 -0400)]
drm/amd/display: init dc_config before rest of DC init
[Why]
In some cases we want DC init to take in some config options
[How]
Init dc_config before rest of DC init
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
SivapiriyanKumarasamy [Mon, 25 Mar 2019 18:04:30 +0000 (14:04 -0400)]
drm/amd/display: Call hwss.set_cursor_sdr_white_level, if available
[Why]
In HDR configurations, the cursor - in SDR - needs to have it's white
level boosted.
[How]
Program the cursor boost in update_dchubp_dpp like the other cursor
attributes.
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Reza Amini <Reza.Amini@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 15 Mar 2019 14:31:50 +0000 (10:31 -0400)]
drm/amd/display: Set surface color space from DRM plane state
[Why]
We need DC's color space to match the color encoding and color space
specified by userspace to correctly render YUV surfaces.
[How]
Convert the DRM color encoding and color range properties to the
appropriate DC colorspace option and update the color space when
performing surface updates.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Fri, 22 Mar 2019 23:33:46 +0000 (19:33 -0400)]
drm/amd/display: prefer preferred link cap over verified link settings
[why]
when preferred link cap is set, we should always use
preferred in all validation.
we should not use preferred for some validation but use
verified for others.
[how]
create getter function that gets verified link cap.
if preferred is set, return preferred link settings instead.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Josip Pavic [Thu, 21 Mar 2019 19:04:32 +0000 (15:04 -0400)]
drm/amd/display: remove min reduction for abm 2.2 level 3
[Why]
Image brightness compensation for solid color full screen images is
expected to be optimal for ABM 2.2 at level 3. The min reduction that is
currently being enforced prevents this from being achieved.
[How]
Remove the min reduction for ABM 2.2 at level 3
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Fri, 22 Mar 2019 21:27:52 +0000 (17:27 -0400)]
drm/amd/display: 3.2.25
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Su Sung Chung [Thu, 21 Mar 2019 19:40:44 +0000 (15:40 -0400)]
drm/amd/display: return correct dc_status for dcn10_validate_global
[Why]
Before it was returning false in the case of failure even though return type should be enum dc_status
[How]
Return DC_FAIL_UNSUPPORTED_1 instead
Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 14 Mar 2019 17:46:44 +0000 (13:46 -0400)]
drm/amd/display: Use plane->color_space for dpp if specified
[Why]
The input color space for the plane was previously ignored even if it
was set.
If a limited range YUV format was given to DC then the
wrong color transformation matrix was being used since DC assumed that
it was full range instead.
[How]
Respect the given color_space format for the plane if it isn't
COLOR_SPACE_UNKNOWN. Otherwise, use the implicit default since DM
didn't specify.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Tue, 19 Mar 2019 23:47:32 +0000 (19:47 -0400)]
drm/amd/display: Calculate link bandwidth in a common function
[why]
Currently link bandwidth is calculated in two places, using the same
formula. They should be unified into calling one function.
[how]
Replace all implementations of link bandwidth calculation with a call
to a function.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Wed, 20 Mar 2019 21:10:41 +0000 (17:10 -0400)]
drm/amd/display: fix clk_mgr naming
clk_mgr is called dccg in dc_state, this change fixes that
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Thu, 21 Mar 2019 17:05:36 +0000 (13:05 -0400)]
drm/amd/display: use proper formula to calculate bandwidth from timing
[why]
The existing calculation uses a wrong formula to
calculate bandwidth from timing.
[how]
Expose the existing proper function that calculates the bandwidth,
so dc_link can use it to calculate timing bandwidth correctly.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
SivapiriyanKumarasamy [Tue, 19 Mar 2019 19:21:50 +0000 (15:21 -0400)]
drm/amd/display: fix dp_hdmi_max_pixel_clk units
[Why]
We are incorrectly using dp_hdmi_max_pixel_clk because the units are not clear.
[How]
Rename to dp_hdmi_max_pixel_clk_in_khz, and change mode timing validation to use
the value correctly.
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 22 Mar 2019 14:11:14 +0000 (10:11 -0400)]
drm/amd/display: Add debugfs entry for amdgpu_dm_visual_confirm
[Why]
DC provides a few visual confirmation debug options that can be
dynamically changed at runtime to help debug surface programming issues
but we don't have any way to access it from userspace.
[How]
Add the amdgpu_dm_visual_confirm debugfs entry.
It accepts a string containing the DC visual confirm enum value using
the debugfs attribute helpers.
The debugfs_create_file_unsafe can be used instead of
debugfs_create_file as per the documentation.
v2: Use debugfs helpers for getting and setting the value (Christian)
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 22 Mar 2019 13:59:32 +0000 (09:59 -0400)]
drm/amd/display: Initialize stream_update with memset
The brace initialization used here generates warnings on some
compilers. For example, on GCC 4.9:
[...] In function ‘dm_determine_update_type_for_commit’:
[...] error: missing braces around initializer [-Werror=missing-braces]
struct dc_stream_update stream_update = { 0 };
^
Use memset to make this more portable.
v2: Specify the compiler / diagnostic in the commit message (Paul)
Cc: Sun peng Li <Sunpeng.Li@amd.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Mon, 25 Mar 2019 19:27:01 +0000 (15:27 -0400)]
drm/amd/display: Remove semicolon from to_dm_plane_state definition
The extra ; in the macro definition creates an empty statement
preventing any variable declarations from occuring after
any use of to_dm_plane_state(...).
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yintian Tao [Tue, 9 Apr 2019 12:33:20 +0000 (20:33 +0800)]
drm/amdgpu: support dpm level modification under virtualization v3
Under vega10 virtualuzation, smu ip block will not be added.
Therefore, we need add pp clk query and force dpm level function
at amdgpu_virt_ops to support the feature.
v2: add get_pp_clk existence check and use kzalloc to allocate buf
v3: return -ENOMEM for allocation failure and correct the coding style
Signed-off-by: Yintian Tao <yttao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
shaoyunl [Mon, 8 Apr 2019 22:28:22 +0000 (18:28 -0400)]
drm/amdgpu: Always enable memory sharing within same XGMI hive
XGMI Memory sharing will be disbaled by default for security reason after
boot up, it depends on driver to enable the memory sharing
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Tue, 9 Apr 2019 08:53:08 +0000 (16:53 +0800)]
drm/amdgpu: Add a check to avoid panic because of unexpected irqs
IP initialize ras in late_init, because of the BUGs of PSP or any
other components, driver receives unexpected irqs. It is ok to add such
check anyway.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 8 Apr 2019 06:57:28 +0000 (14:57 +0800)]
drm/amdgpu: sdma use amdgpu_ras_feature_enable_on_boot
handle ras enable on boot.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 8 Apr 2019 06:56:46 +0000 (14:56 +0800)]
drm/amdgpu: gmc use amdgpu_ras_feature_enable_on_boot
handle ras enable on boot.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 8 Apr 2019 06:55:45 +0000 (14:55 +0800)]
drm/amdgpu: gfx use amdgpu_ras_feature_enable_on_boot
handle ras enable on boot.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 8 Apr 2019 06:49:37 +0000 (14:49 +0800)]
drm/amdgpu: Introduce another ras enable function
Many parts of the whole SW stack can program the ras enablement state
during the boot. Now we handle that case by adding one function which
check the ras flags and choose different code path.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Wed, 3 Apr 2019 01:52:59 +0000 (09:52 +0800)]
drm/amdgpu: Make default ras error type to none
Unless IP has implemented its own ras, use ERROR_NONE as the default
type.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Mon, 8 Apr 2019 08:29:49 +0000 (16:29 +0800)]
drm/amd/powerplay: simplify the code of [get|set]_activity_monitor_coeff
use smu_update_table_with_arg to replace old code logic
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Mon, 8 Apr 2019 08:15:36 +0000 (16:15 +0800)]
drm/amd/powerplay: optimization function of smu_update_table
in fact, the firmware need 2 parameter: 1.table_id, 2.XferArg
so change the function interface to match the firmware code
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Qiang Yu [Tue, 9 Apr 2019 00:36:17 +0000 (08:36 +0800)]
drm/lima: include used header file explicitly
To prevent build fail on some platform which does
not have it in the include file chain.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Suggested-by: Randy Dunlap <rdunlap@infradead.org>
Fixes:
a1d2a6339961 ("drm/lima: driver for ARM Mali4xx GPUs")
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190409003617.4470-2-yuq825@gmail.com
Qiang Yu [Tue, 9 Apr 2019 00:36:16 +0000 (08:36 +0800)]
drm/lima: add missing Kconfig dependency
Current implementation does not support MMU-less
plarforms.
Suggested-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Fixes:
a1d2a6339961 ("drm/lima: driver for ARM Mali4xx GPUs")
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190409003617.4470-1-yuq825@gmail.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:24 +0000 (15:18 +0100)]
drm/meson: Add G12A support for the DW-HDMI Glue
The Amlogic G12A embeds the same Synopsys DW-HDMI Controller,
but with :
- a "backport" of the HDR signaling registers from more recent
DW-HDMI controllers, this will need a tweak since it's not
normally present on this version of the DW-HDMI controller
- A direct mapping of TOP and DW-HDMI registers instead of an
internal bus accessed using read/write registers
- Support for RX-SENSE, but not yet implemented
- Support for HDMI 2.1 Dynamic HDR, but not yet implemented
- Different registers mapping for the HDMI PHY setup
This patchs adds support for these changes while providing exact
same support as the previous GXBB, GXL & GXM SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-12-narmstrong@baylibre.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:23 +0000 (15:18 +0100)]
drm/meson: Add G12A compatible
Finally add the Amlogic G12A SoC compatible for the VPU driver.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-11-narmstrong@baylibre.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:22 +0000 (15:18 +0100)]
drm/meson: Add G12A Video Clock setup
While switching to the Common Clock Framework is still Work In Progress,
this patch adds the corresponding G12A HDMI PLL setup to be on-par
with the other SoCs support.
The G12A has only a single tweak about the high frequency setup,
where the HDMI PLL needs a specific setup to handle correctly the
5.94GHz DCO frequency.
Apart that, it handls ecorrectly all the other HDMI frequencies
and can achieve even better DMT clock frequency precision with
the larger fractional dividier width.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-10-narmstrong@baylibre.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:21 +0000 (15:18 +0100)]
drm/meson: Add G12A support for CVBS Encoder
The Meson G12A SoCs uses the exact same CVBS encoder except a simple
CVBS DAC register offset and settings delta.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: fixed subject typo]
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-9-narmstrong@baylibre.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:20 +0000 (15:18 +0100)]
drm/meson: Add G12A support for plane handling in CRTC driver
This patch adds support for the new OSD+VD Plane blending module
in the CRTC code by adding the G12A code to manage the blending
module and setting the right OSD1 & VD1 plane registers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-8-narmstrong@baylibre.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:19 +0000 (15:18 +0100)]
drm/meson: Add G12A Support for the Overlay video plane
Amlogic G12A SoC supports the same set of Video Planes, but now
are handled by the new OSD plane blender module.
This patch uses the same VD1 plane for G12A, using the exact same scaler
and VD1 setup registers, except using the new blender register to
disable the plane.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: fix typo in commit log]
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-7-narmstrong@baylibre.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:18 +0000 (15:18 +0100)]
drm/meson: Add G12A support for OSD1 Plane
Amlogic G12A SoC supports now up to 3 OSD planes (1 more than the
previous SoCs) and a brand new OSD plane blender module.
This patch uses the same OSD1 plane for G12A, using the exact same scaler
and OSD1 setup registers, except using the new blender register to
disable the plane.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: fixed typo in commit log]
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-6-narmstrong@baylibre.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:17 +0000 (15:18 +0100)]
drm/meson: Add G12A Support for VIU setup
Amlogic G12A SoC needs a different VIU setup code,
handle it.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-5-narmstrong@baylibre.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:16 +0000 (15:18 +0100)]
drm/meson: Add G12A Support for VPP setup
Amlogic G12A needs a different VPP setup code, handle it here.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-4-narmstrong@baylibre.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:15 +0000 (15:18 +0100)]
drm/meson: Add registers for G12A SoC
This patch adds the new VPU registers added since the
Amlogic GXM SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-3-narmstrong@baylibre.com
Neil Armstrong [Mon, 25 Mar 2019 14:18:14 +0000 (15:18 +0100)]
drm/meson: Switch PLL to 5.94GHz base for 297Mhz pixel clock
On Amlogic G12A SoC, the 2,97GHz PLL frequency is not stable enough
to provide a correct 297MHz pixel clock, so switch the PLL base
frequency with a /2 OD when the 297MHz pixel clock is requested.
This solves the issue on G12A and also works fine on GXBB, GXL & GXM.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-2-narmstrong@baylibre.com
Neil Armstrong [Wed, 13 Mar 2019 14:10:29 +0000 (15:10 +0100)]
dt-bindings: display: amlogic, meson-dw-hdmi: Add G12A compatible and ports
The Amlogic G12A SoC has a slighly modified DW-HDMI Glue with
support for HDMI 2.1 and a different DW-HDMI register access.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190313141030.5958-3-narmstrong@baylibre.com
Neil Armstrong [Wed, 13 Mar 2019 14:10:28 +0000 (15:10 +0100)]
dt-bindings: display: amlogic, meson-vpu: Add G12A compatible and ports
The Amlogic G12A VPU is very similar to the Amlogic GXM VPU but with :
- an enhanced plane blender, with up to 3 OSD planes
- support for AFBC 1.2 decoder (for Bifrost GPU)
- support display mode up to 4k60@75Hz
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190313141030.5958-2-narmstrong@baylibre.com
Neil Armstrong [Mon, 1 Apr 2019 08:09:49 +0000 (10:09 +0200)]
dt-bindings: gpu: add bindings for the ARM Mali Bifrost GPU
Add the bindings for the Bifrost family of ARM Mali GPUs.
The Bifrost GPU architecture is similar to the Midgard family,
but with a different Shader Core & Execution Engine structures.
Bindings are based on the Midgard family bindings, but the inner
architectural changes makes it a separate family needing separate
bindings.
The Bifrost GPUs are present in a number of recent SoCs, like the
Amlogic G12A Family, and many other vendors.
The Amlogic vendor specific compatible is added to handle the
specific IP integration differences and dependencies.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
[narmstrong: fixed small typo in compatible description]
Link: https://patchwork.freedesktop.org/patch/msgid/20190401080949.14550-1-narmstrong@baylibre.com
Randy Dunlap [Sun, 7 Apr 2019 19:12:10 +0000 (12:12 -0700)]
MAINTAINERS: mark lima mailing list as moderated
Note that the lima mailing list is moderated.
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Qiang Yu <yuq825@gmail.com>
Cc: dri-devel@lists.freedesktop.org
Cc: lima@lists.freedesktop.org
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9138d8e8-5390-0650-9bc3-050b869e978c@infradead.org
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Gerd Hoffmann [Fri, 5 Apr 2019 09:52:19 +0000 (11:52 +0200)]
drm/cirrus: rewrite and modernize driver.
Time to kill some bad sample code people are copying from ;)
This is a complete rewrite of the cirrus driver. The cirrus_mode_set()
function is pretty much the only function which is carried over largely
unmodified. Everything else is upside down.
It is a single monster patch. But given that it does some pretty
fundamental changes to the drivers workflow and also reduces the code
size by roughly 70% I think it'll still be alot easier to review than a
longish baby-step patch series.
Changes summary:
- Given the small amout of video memory (4 MB) the cirrus device has
the rewritten driver doesn't try to manage buffers there. Instead
it will blit (memcpy) the active framebuffer to video memory.
- All gem objects are stored in main memory and are manged using the
new shmem helpers. ttm is out.
- It supports RG16, RG24 and XR24 formats. XR24 gets converted to RG24
or RG16 at blit time if needed, to avoid the pitch becoming larger
than what the cirrus hardware can handle.
- The simple display pipeline is used.
- The generic fbdev emulation is used.
- It's a atomic driver now.
- It runs wayland.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Acked-by: Noralf Trønnes <noralf@tronnes.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20190405095219.9231-6-kraxel@redhat.com
Gerd Hoffmann [Fri, 5 Apr 2019 09:52:18 +0000 (11:52 +0200)]
drm: add drm_fb_xrgb8888_to_rgb888_dstclip()
Simliar to drm_fb_xrgb8888_to_rgb565_dstclip() but converts to rgb888
instead of rgb565.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Noralf Trønnes <noralf@tronnes.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20190405095219.9231-5-kraxel@redhat.com
Gerd Hoffmann [Fri, 5 Apr 2019 09:52:17 +0000 (11:52 +0200)]
drm: add drm_fb_xrgb8888_to_rgb565_dstclip()
It is a drm_fb_xrgb8888_to_rgb565() variant which checks the clip
rectangle for the destination too.
Common code between drm_fb_xrgb8888_to_rgb565() and
drm_fb_xrgb8888_to_rgb565_dstclip() was factored out into the
drm_fb_xrgb8888_to_rgb565_lines() helper function.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Noralf Trønnes <noralf@tronnes.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20190405095219.9231-4-kraxel@redhat.com
Gerd Hoffmann [Fri, 5 Apr 2019 09:52:16 +0000 (11:52 +0200)]
drm: add drm_fb_memcpy_dstclip() helper
It is a drm_fb_memcpy() variant which checks the clip rectangle for the
destination too.
Common code between drm_fb_memcpy() and drm_fb_memcpy_dstclip() was
factored out into the drm_fb_memcpy_lines() helper function.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Noralf Trønnes <noralf@tronnes.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20190405095219.9231-3-kraxel@redhat.com
Gerd Hoffmann [Fri, 5 Apr 2019 09:52:15 +0000 (11:52 +0200)]
drm: move tinydrm format conversion helpers to new drm_format_helper.c
Also rename them from tinydrm_* to drm_fb_*
Pure code motion, no functional change.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Noralf Trønnes <noralf@tronnes.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20190405095219.9231-2-kraxel@redhat.com
Sean Paul [Wed, 3 Apr 2019 20:56:45 +0000 (16:56 -0400)]
Documentation/gpu/meson: Remove link to meson_canvas.c
The file was removed in the below patch and is causing this error:
WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -function Canvas ../drivers/gpu/drm/meson/meson_canvas.c' failed with return code
Fixes:
2bf6b5b0e374 ("drm/meson: exclusively use the canvas provider module")
Cc: Maxime Jourdan <mjourdan@baylibre.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190403205652.183496-1-sean@poorly.run
Dave Airlie [Fri, 5 Apr 2019 01:21:47 +0000 (11:21 +1000)]
Merge tag 'drm-misc-next-2019-04-04' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for 5.2:
UAPI Changes:
-syncobj: Add TIMELINE_WAIT|QUERY|TRANSFER|TIMELINE_SIGNAL ioctls (Chunming)
-Clarify that 1.0 can be represented by drm_color_lut (Daniel)
Cross-subsystem Changes:
-dt-bindings: Add binding for rk3066 hdmi (Johan)
-dt-bindings: Add binding for Feiyang FY07024DI26A30-D panel (Jagan)
-dt-bindings: Add Rocktech vendor prefix and jh057n00900 panel bindings (Guido)
-MAINTAINERS: Add lima and ASPEED entries (Joel & Qiang)
Core Changes:
-memory: use dma_alloc_coherent when mem encryption is active (Christian)
-dma_buf: add support for a dma_fence chain (Christian)
-shmem_gem: fix off-by-one bug in new shmem gem helpers (Dan)
Driver Changes:
-rockchip: Add support for rk3066 hdmi (Johan)
-ASPEED: Add driver supporting ASPEED BMC display controller to drm (Joel)
-lima: Add driver supporting Arm Mali4xx gpus to drm (Qiang)
-vc4/v3d: Various cleanups and improved error handling (Eric)
-panel: Add support for Feiyang FY07024DI26A30-D MIPI-DSI panel (Jagan)
-panel: Add support for Rocktech jh057n00900 MIPI-DSI panel (Guido)
Cc: Johan Jonker <jbx6244@gmail.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Chunming Zhou <david1.zhou@amd.com>
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Eric Anholt <eric@anholt.net>
Cc: Qiang Yu <yuq825@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Guido Günther <agx@sigxcpu.org>
Cc: Joel Stanley <joel@jms.id.au>
[airlied: fixed XA limit build breakage, Rodrigo also submitted the same patch, but
I squashed it in the merge.]
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Sean Paul <sean@poorly.run>
Link: https://patchwork.freedesktop.org/patch/msgid/20190404201016.GA139524@art_vandelay
Wen Yang [Wed, 3 Apr 2019 16:04:13 +0000 (00:04 +0800)]
drm/pl111: fix possible object reference leak
The call to of_find_matching_node_and_match returns a node pointer with
refcount incremented thus it must be explicitly decremented after the
last usage.
Detected by coccinelle with the following warnings:
drivers/gpu/drm/pl111/pl111_versatile.c:333:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function.
drivers/gpu/drm/pl111/pl111_versatile.c:340:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function.
drivers/gpu/drm/pl111/pl111_versatile.c:346:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function.
drivers/gpu/drm/pl111/pl111_versatile.c:354:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function.
drivers/gpu/drm/pl111/pl111_versatile.c:395:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function.
drivers/gpu/drm/pl111/pl111_versatile.c:402:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function.
Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Cc: Eric Anholt <eric@anholt.net> (supporter:DRM DRIVER FOR ARM PL111 CLCD)
Cc: David Airlie <airlied@linux.ie> (maintainer:DRM DRIVERS)
Cc: Daniel Vetter <daniel@ffwll.ch> (maintainer:DRM DRIVERS)
Cc: dri-devel@lists.freedesktop.org (open list:DRM DRIVERS)
Cc: linux-kernel@vger.kernel.org (open list)
Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/1554307455-40361-6-git-send-email-wen.yang99@zte.com.cn
kbuild test robot [Wed, 3 Apr 2019 21:36:29 +0000 (05:36 +0800)]
drm/vc4: vc4_debugfs_regset32() can be static
Fixes:
c9be804c8c7a ("drm/vc4: Use common helpers for debugfs setup by the driver components.")
Signed-off-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20190403213629.GA31570@lkp-ib03
Joe Perches [Thu, 4 Apr 2019 15:06:09 +0000 (08:06 -0700)]
drm/panel: Rocktech jh057n00900: Add terminating newlines to logging
These were missing '\n' terminations, add them.
Signed-off-by: Joe Perches <joe@perches.com>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/da6f2344396555034cf2476c8338b0ce1c56e0a7.camel@perches.com
Evan Quan [Thu, 28 Mar 2019 01:46:36 +0000 (09:46 +0800)]
drm/amd/powerplay: check for invalid profile mode before switching
Need to check for invalid profile mode settings before determining
to switch to that.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joel Stanley [Wed, 3 Apr 2019 00:19:09 +0000 (10:49 +1030)]
MAINTAINERS: Add ASPEED BMC GFX DRM driver entry
This hardware is found inside ASPEED Baseboard Management Controller
(BMC) system on chips. It is called the 'SOC Display Controller' or 'GFX'.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20190403001909.31637-4-joel@jms.id.au
Joel Stanley [Wed, 3 Apr 2019 00:19:08 +0000 (10:49 +1030)]
drm: Add ASPEED GFX driver
This driver is for the ASPEED BMC SoC's GFX display hardware. This
driver runs on the ARM based BMC systems, unlike the ast driver which
runs on a host CPU and is is for a PCI graphics device.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Noralf Trønnes <noralf@tronnes.org>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190403001909.31637-3-joel@jms.id.au
Joel Stanley [Wed, 3 Apr 2019 00:19:07 +0000 (10:49 +1030)]
dt-bindings: gpu: Add ASPEED GFX bindings document
This describes the ASPEED BMC SoC's display controller.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20190403001909.31637-2-joel@jms.id.au
Eric Anholt [Mon, 1 Apr 2019 18:35:59 +0000 (11:35 -0700)]
drm/vc4: Disable V3D interactions if the v3d component didn't probe.
One might want to use the VC4 display stack without using Mesa.
Similar to the debugfs fixes for not having all of the possible
display bits enabled, make sure you can't oops in vc4 if v3d isn't
enabled.
v2: Fix matching against other v3d variants (review by Paul), don't
forget to set irq_enabled so that the vblank uapi works
v3: Use -ENODEV instead of -EINVAL on Paul's suggestion.
Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20190401183559.3823-2-eric@anholt.net
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Eric Anholt [Mon, 1 Apr 2019 18:35:58 +0000 (11:35 -0700)]
drm/vc4: Use common helpers for debugfs setup by the driver components.
The global list of all debugfs entries for the driver was painful: the
list couldn't see into the components' structs, so each component had
its own debugs show function to find the component, then find the
regset and dump it. The components also had to be careful to check
that they were actually registered in vc4 before dereferencing
themselves, in case they weren't probed on a particular platform.
They routinely failed at that.
Instead, we can have the components add their debugfs callbacks to a
little list in vc4 to be registered at drm_dev_register() time, which
gets vc4_debugfs.c out of the business of knowing the whole list of
components.
Thanks to this change, dsi0 (if it existed) would register its node.
v2: Rebase on hvs_underrun addition.
v3: whitespace fixup
Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20190401183559.3823-1-eric@anholt.net
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Nicholas Kazlauskas [Mon, 11 Mar 2019 14:33:35 +0000 (10:33 -0400)]
drm/amd/display: Prevent cursor hotspot overflow for RV overlay planes
[Why]
The actual position for the cursor on the screen is essentially:
x_out = x - x_plane - x_hotspot
y_out = y - y_plane - y_hotspot
The register values for cursor position and cursor hotspot need to be
greater than zero when programmed, but we also need to subtract off
the plane position to display the cursor at the correct position.
Since we don't want x or y to be less than zero, we add the plane
position as a positive value to x_hotspot or y_hotspot. However, what
this doesn't take into account is that the hotspot registers are limited
by the maximum cursor size.
On DCN10 the cursor hotspot regitsers are masked to 0xFF, so they have
a maximum value of 0-255. Values greater this will wrap, causing the
cursor to display in the wrong position.
In practice this means that for sufficiently large plane positions, the
cursor will be drawn twice on the screen, and can cause screen flashes
or p-state WARNS depending on what the wrapped value is.
So we need a way to remove the value from x_plane and y_plane without
exceeding the maximum cursor size.
[How]
Subtract as much as x_plane/y_plane as possible from x and y and place
the remainder in the cursor hotspot register.
The value for x_hotspot and y_hotspot can still wrap around but it
won't happen in a case where the cursor is actually enabled.
The cursor plane needs to intersect at least one pixel of the plane's
rectangle to be enabled, so the cursor position + hotspot provided by
userspace must always be strictly less than the maximum cursor size for
the cursor to actually be enabled.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Li [Thu, 21 Mar 2019 14:36:07 +0000 (10:36 -0400)]
drm/amd/display: Fix "dc has no member named dml" compile error
For DCN disabled builds, dc->dml is stripped out. Therefore, guard usage
in dc_create_state() with CONFIG_DRM_AMD_DC_DCN1_0.
It fixes the following error:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c: In function 'dc_create_state':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:1237:34: error: 'struct dc' has no member named 'dml'
memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
^~
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aidan Wood [Fri, 22 Feb 2019 18:37:03 +0000 (13:37 -0500)]
drm/amd/display: Fix multi-thread writing to 1 state
[Why]
Multiple threads were writing back to one global VBA in DC resulting
in multiple threads overwriting eachother's data
[How]
Add an instance of DML (which contains VBA) to each context and
change all calls that used dc->dml to use context->dml. Created a
seperate copy constructor for linux in a case where there is no
access to DC.
Signed-off-by: Aidan Wood <Aidan.Wood@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yannick Fertré [Thu, 21 Mar 2019 08:07:26 +0000 (09:07 +0100)]
drm/panel: otm8009a: Set clock to 29.70 Mhz
The panel does not support clock frequency over 30.74 MHz. The clock
rate has been reduced to 29.70 MHz & new timings have been computed to
get a framerate of 50 fps.
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
Tested-by: Philippe Cornu <philippe.cornu@st.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1553155646-13636-1-git-send-email-yannick.fertre@st.com
Yannick Fertré [Thu, 21 Mar 2019 08:05:35 +0000 (09:05 +0100)]
drm/panel: rm68200: No error msg if probe deferred
Do not print an error message if the regulator framework returns
EPROBE_DEFER.
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1553155535-13555-1-git-send-email-yannick.fertre@st.com
Yannick Fertré [Thu, 21 Mar 2019 08:04:44 +0000 (09:04 +0100)]
drm/panel: otm8009a: No error msg if probe deferred
Do not print an error message if the regulator framework returns
EPROBE_DEFER.
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
Tested-by: Philippe Cornu <philippe.cornu@st.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1553155484-13460-1-git-send-email-yannick.fertre@st.com
Yannick Fertré [Thu, 21 Mar 2019 08:04:05 +0000 (09:04 +0100)]
drm/panel: otm8009a: Add delay at the end of initialization
At the end of initialization, a delay is required by the panel. Without
this delay, the panel could received a frame early & generate a crash of
panel (black screen).
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
Tested-by: Philippe Cornu <philippe.cornu@st.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1553155445-13407-1-git-send-email-yannick.fertre@st.com
Guido Günther [Mon, 1 Apr 2019 10:35:35 +0000 (12:35 +0200)]
drm/panel: Add Rocktech jh057n00900 panel driver
Support Rocktech jh057n00900 5.5" 720x1440 TFT LCD panel. It is a MIPI
DSI video mode panel.
The panel seems to use a Sitronix ST7703 look alike (most of the
commands look similar to the ST7703's data sheet but use a different
number of parameters). The initial version of the DSI init sequence
(including sleeps) were provided by the vendor. Sleeps were reduced
considerably though to speed up initialization.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1a9ce687be283c66dfb26d1dfb52a7bf695090fa.1554114302.git.agx@sigxcpu.org
Guido Günther [Mon, 1 Apr 2019 10:35:34 +0000 (12:35 +0200)]
dt-bindings: Add Rocktech jh057n00900 panel bindings
The Rocktec jh057n00900 is a 5.5" MIPI DSI video mode panel with a
720x1440 resolution and a built in backlight.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ec59b22907ac28764ffb3bec33445b6e019945a4.1554114302.git.agx@sigxcpu.org
Guido Günther [Mon, 1 Apr 2019 10:35:33 +0000 (12:35 +0200)]
dt-bindings: Add vendor prefix for ROCKTECH DISPLAYS LIMITED
Add ROCKTECH DISPLAYS LIMITED (https://rocktech.com.hk) LCD panel
supplier.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b8db03faa344c834e6cc81eef1eca154e1a1bd90.1554114302.git.agx@sigxcpu.org
Guido Günther [Mon, 25 Mar 2019 16:08:10 +0000 (17:08 +0100)]
dt-bindings: display/panel: Add missing unit names
Some examples were missing the unit names triggering
Warning (unit_address_vs_reg): .../panel: node has a reg or ranges property, but no unit name
warnings when used verbatim in DTs and running dtc with W=1.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/901e836ea06889a9d91a799102b2a6b836d93dcd.1553529797.git.agx@sigxcpu.org
Jagan Teki [Tue, 12 Feb 2019 20:41:09 +0000 (02:11 +0530)]
drm/panel: Add Feiyang FY07024DI26A30-D MIPI-DSI LCD panel
Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
Add panel driver for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Tested-by: Bhushan Shah <bshah@kde.org>
Tested-by: Merlijn Wajer <merlijn@wizzup.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190212204109.3528-2-jagan@amarulasolutions.com
Jagan Teki [Tue, 12 Feb 2019 20:41:08 +0000 (02:11 +0530)]
dt-bindings: panel: Add Feiyang FY07024DI26A30-D MIPI-DSI LCD panel
Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
Add dt-bingings for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190212204109.3528-1-jagan@amarulasolutions.com
Daniel Vetter [Fri, 29 Mar 2019 09:20:27 +0000 (10:20 +0100)]
drm/gamma: Clarify gamma lut uapi
Interpreting it as a 0.16 fixed point means we can't accurately
represent 1.0. Which is one of the values we really should be able to
represent.
Since most (all?) luts have lower precision this will only affect
rounding of 0xffff.
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: "Kumar, Kiran S" <kiran.s.kumar@intel.com>
Cc: Kausal Malladi <kausalmalladi@gmail.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rob Bradford <robert.bradford@intel.com>
Cc: Daniel Stone <daniels@collabora.com>
Cc: Stefan Schake <stschake@gmail.com>
Cc: Eric Anholt <eric@anholt.net>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Cc: James (Qian) Wang <james.qian.wang@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Cc: CK Hu <ck.hu@mediatek.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Yannick Fertre <yannick.fertre@st.com>
Cc: Philippe Cornu <philippe.cornu@st.com>
Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Vincent Abriou <vincent.abriou@st.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190329092027.3430-1-daniel.vetter@ffwll.ch
Mario Kleiner [Fri, 29 Mar 2019 12:00:57 +0000 (13:00 +0100)]
drm/amd/display: Make pageflip event delivery compatible with VRR.
We want vblank counts and timestamps of flip completion as sent
in pageflip completion events to be consistent with the vblank
count and timestamp of the vblank of flip completion, like in non
VRR mode.
In VRR mode, drm_update_vblank_count() - and thereby vblank
count and timestamp updates - must be delayed until after the
end of front-porch of each vblank, as it is only safe to
calculate vblank timestamps outside of the front-porch, when
we actually know when the vblank will end or has ended.
The function drm_update_vblank_count() which updates timestamps
and counts gets called by drm_crtc_accurate_vblank_count() or by
drm_crtc_handle_vblank().
Therefore we must make sure that pageflip events for a completed
flip are only sent out after drm_crtc_accurate_vblank_count() or
drm_crtc_handle_vblank() is executed, after end of front-porch
for the vblank of flip completion.
Two cases:
a) Pageflip irq handler executes inside front-porch:
In this case we must defer sending pageflip events until
drm_crtc_handle_vblank() executes after end of front-porch,
and thereby calculates proper vblank count and timestamp.
Iow. the pflip irq handler must just arm a pageflip event
to be sent out by drm_crtc_handle_vblank() later on.
b) Pageflip irq handler executes after end of front-porch, e.g.,
after flip completion in back-porch or due to a massively
delayed handler invocation into the active scanout of the new
frame. In this case we can call drm_crtc_accurate_vblank_count()
to safely force calculation of a proper vblank count and
timestamp, and must send the pageflip completion event
ourselves from the pageflip irq handler.
This is the same behaviour as needed for standard fixed refresh
rate mode.
To decide from within pageflip handler if we are in case a) or b),
we check the current scanout position against the boundary of
front-porch. In non-VRR mode we just do what we did in the past.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Fri, 29 Mar 2019 12:00:56 +0000 (13:00 +0100)]
drm/amd/display: In VRR mode, do DRM core vblank handling at end of vblank. (v2)
In VRR mode, proper vblank/pageflip timestamps can only be computed
after the display scanout position has left front-porch. Therefore
delay calls to drm_crtc_handle_vblank(), and thereby calls to
drm_update_vblank_count() and pageflip event delivery, to after the
end of front-porch when in VRR mode.
We add a new vupdate irq, which triggers at the end of the vupdate
interval, ie. at the end of vblank, and calls the core vblank handler
function. The new irq handler is not executed in standard non-VRR
mode, so vblank handling for fixed refresh rate mode is identical
to the past implementation.
v2: Implement feedback by Nicholas and Paul Menzel.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Tue, 2 Apr 2019 22:00:06 +0000 (17:00 -0500)]
drm/amd/display: Rework vrr flip throttling for late vblank irq.
For throttling to work correctly, we always need a baseline vblank
count last_flip_vblank that increments at start of front-porch.
This is the case for drm_crtc_vblank_count() in non-VRR mode, where
the vblank irq fires at start of front-porch and triggers DRM core
vblank handling, but it is no longer the case in VRR mode, where
core vblank handling is done later, after end of front-porch.
Therefore drm_crtc_vblank_count() is no longer useful for this.
We also can't use drm_crtc_accurate_vblank_count(), as that would
screw up vblank timestamps in VRR mode when called in front-porch.
To solve this, use the cooked hardware vblank counter returned by
amdgpu_get_vblank_counter_kms() instead, as that one is cooked to
always increment at start of front-porch, independent of when
vblank related irq's fire.
This patch allows vblank irq handling to happen anywhere within
vblank of even after it, without a negative impact on flip
throttling, so followup patches can shift the vblank core
handling trigger point wherever they need it.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Fri, 29 Mar 2019 12:00:54 +0000 (13:00 +0100)]
drm/amd/display: Prevent vblank irq disable while VRR is active. (v3)
During VRR mode we can not allow vblank irq dis-/enable
transitions, as an enable after a disable can happen at
an arbitrary time during the video refresh cycle, e.g.,
with a high likelyhood inside vblank front-porch. An
enable during front-porch would cause vblank timestamp
updates/calculations which are completely bogus, given
the code can't know when the vblank will end as long
as we are in front-porch with no page flip completed.
Hold a permanent vblank reference on the crtc while
in active VRR mode to prevent a vblank disable, and
drop the reference again when switching back to fixed
refresh rate non-VRR mode.
v2: Make sure transition is also handled if vrr is
disabled and stream gets disabled in the same
atomic commit by moving the call to the transition
function outside of plane commit.
Suggested by Nicholas.
v3: Trivial rebase onto previous patch.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Fri, 29 Mar 2019 12:00:53 +0000 (13:00 +0100)]
drm/amd/display: Update VRR state earlier in atomic_commit_tail.
We need the VRR active/inactive state info earlier in
the commit sequence, so VRR related setup functions like
amdgpu_dm_handle_vrr_transition() know the final VRR state
when they need to do their hw setup work.
Split update_freesync_state_on_stream() into an early part,
that can run at the beginning of commit tail before the
vrr transition handling, and a late part that must run after
vrr transition handling inside the commit planes code for
enabled crtc's.
Suggested by Nicholas Kazlauskas.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>