OSDN Git Service
Timothy Arceri [Thu, 14 Jun 2018 01:00:23 +0000 (11:00 +1000)]
util: add allow_glsl_builtin_const_expression to drirc for Google Earth VR
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Thu, 14 Jun 2018 01:00:22 +0000 (11:00 +1000)]
mesa/util: add allow_glsl_builtin_const_expression driconf override
Google Earth VR shaders uses builtins in constant expressions with
GLSL 1.10. That feature wasn't allowed until GLSL 1.20.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Thu, 14 Jun 2018 01:00:21 +0000 (11:00 +1000)]
util: manually extract the program name from program_invocation_name
Glibc has the same code to get program_invocation_short_name. However
for some reason the short name gets mangled for some wine apps.
For example with Google Earth VR I get:
program_invocation_name:
"/home/tarceri/.local/share/Steam/steamapps/common/EarthVR/Earth.exe"
program_invocation_short_name:
"e"
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Bas Nieuwenhuizen [Mon, 18 Jun 2018 14:29:16 +0000 (16:29 +0200)]
ac/surface: Set compressZ for stencil-only surfaces.
We HTILE compress stencil-only surfaces too.
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Sun, 17 Jun 2018 23:28:02 +0000 (16:28 -0700)]
anv: Use a single global API patch version
The Vulkan API has only one patch version shared among all of the
major.minor versions. We should also advertise the same patch version
regardless of major.minor.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106941
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Mon, 18 Jun 2018 05:23:20 +0000 (15:23 +1000)]
radeonsi: enable OpenGL 3.3 compat profile
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 18 Jun 2018 02:36:54 +0000 (12:36 +1000)]
mesa: add ff fragment shader support for geom and tess shaders
This is required for compatibility profile support.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Eric Anholt [Sat, 16 Jun 2018 00:08:29 +0000 (17:08 -0700)]
v3d: Set the SO offsets correctly if we have to re-emit.
This should fix TF across a glFlush() or TF pause/restart. Fixes
dEQP-GLES3.functional.transform_feedback.array.interleaved.lines.highp_float
and many, many others.
Marek Olšák [Fri, 8 Jun 2018 23:49:22 +0000 (19:49 -0400)]
gallium/hud: = should rename the last added data source
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Rafael Antognolli [Fri, 15 Jun 2018 18:44:28 +0000 (11:44 -0700)]
anv: Disable constant buffer 0 being relative.
If we are on gen8+ and have context isolation support, just make that
constant buffer address be absolute, so we can use it for push UBOs too.
v2: Do not duplicate constant_buffer_0_is_relative flag (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rafael Antognolli [Fri, 15 Jun 2018 16:31:25 +0000 (09:31 -0700)]
anv/device: Check for kernel support of context isolation.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Rafael Antognolli [Fri, 15 Jun 2018 18:43:45 +0000 (11:43 -0700)]
intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Alok Hota [Tue, 5 Jun 2018 18:59:53 +0000 (13:59 -0500)]
swr/rast: Clang-Format most rasterizer source code
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Eric Engestrom [Fri, 15 Jun 2018 16:49:08 +0000 (17:49 +0100)]
radv: fix reported number of available VGPRs
It's a bit late to round up after an integer division.
Fixes:
de889794134e6245e08a2 "radv: Implement VK_AMD_shader_info"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Alex Smith <asmith@feralinteractive.com>
Eric Engestrom [Mon, 18 Jun 2018 10:39:05 +0000 (11:39 +0100)]
mesa: add missing return in error path
Fixes:
67f40dadaa6666dacd90 "mesa: add support for ARB_sample_locations"
Cc: Rhys Perry <pendingchaos02@gmail.com>
Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Bas Nieuwenhuizen [Sun, 17 Jun 2018 01:37:49 +0000 (03:37 +0200)]
radv: Use less conservative approximation for context rolls.
Drops the number of time we set the scissor by 4x for F1 2017,
which results in a consistent performance improvement of about 4%.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Eric Engestrom [Fri, 15 Jun 2018 16:58:17 +0000 (17:58 +0100)]
radv: fix bitwise check
Fixes:
922cd38172b8a2bc286bd "radv: implement out-of-order rasterization when it's safe on VI+"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Eric Engestrom [Fri, 15 Jun 2018 10:31:52 +0000 (11:31 +0100)]
meson: fix i965/anv/isl genX static lib names
Shouldn't make any functional difference, just that `liblibanv_gen90.a`
will now be called `libanv_gen90.a`.
Fixes:
3218056e0eb375eeda470 "meson: Build i965 and dri stack"
Fixes:
d1992255bb29054fa5176 "meson: Add build Intel "anv" vulkan driver"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Timothy Arceri [Sun, 17 Jun 2018 00:00:29 +0000 (10:00 +1000)]
mesa: Unconditionally enable floating-point textures
ARB_texture_float references US Patent #6,650,327 [1] which has a filing date
of June 16 1998.
According to [2], patents filed after 1995 expire 20 years from the filing
date, giving an expiration of June 17 2018.
[1] https://www.google.com/patents/US6650327
[2] https://en.wikipedia.org/wiki/Term_of_patent_in_the_United_States
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:46:34 +0000 (11:46 +0200)]
intel/fs: shuffle_64bit_data_for_32bit_write is not used anymore
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:46:17 +0000 (11:46 +0200)]
intel/fs: Use new shuffle_32bit_write for all 64-bit storage writes
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:46:14 +0000 (11:46 +0200)]
intel/fs: shuffle_32bit_load_result_to_64bit_data is not used anymore
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:46:11 +0000 (11:46 +0200)]
intel/fs: Use shuffle_from_32bit_read for 64-bit FS load_input
As the previous use of shuffle_32bit_load_result_to_64bit_data
had a source/destination overlap for 64-bit. Now a temporary destination
is used for 64-bit cases to use shuffle_from_32bit_read that doesn't
handle src/dst overlaps.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:46:07 +0000 (11:46 +0200)]
intel/fs: shuffle_from_32bit_read at load_per_vertex_input at TCS/TES
Previously, the shuffle function had a source/destination overlap that
needs to be avoided to use shuffle_from_32bit_read. As we can use for
the shuffle destination the destination of removed MOVs.
This change also avoids the internal MOVs done by the previous shuffle
to deal with possible overlaps.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:46:04 +0000 (11:46 +0200)]
intel/fs: Use shuffle_from_32bit_read at VS load_input
shuffle_from_32bit_read manages 32-bit reads to 32-bit destination
in the same way that the previous loop so now we just call the new
function for all bitsizes, simplifying also the 64-bit load_input.
v2: Add comment about future 16-bit support (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:46:01 +0000 (11:46 +0200)]
intel/fs: Use shuffle_from_32bit_read for 64-bit gs_input_load
This implementation avoids two unneeded MOVs for each 64-bit
component. One was done in the old shuffle, to avoid cases of
src/dst overlap but this is not the case. And the removed MOV
was already being being done in the shuffle.
Copy propagation wasn't able to remove them because shuffle
destination values are defined with partial writes because they
have stride == 2.
v2: Reword commit log summary (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:57 +0000 (11:45 +0200)]
intel/fs: shuffle_from_32bit_read for 64-bit do_untyped_vector_read
do_untyped_vector_read is used at load_ssbo and load_shared.
The previous MOVs are removed because shuffle_from_32bit_read
can handle storing the shuffle results in the expected destination
just using the proper offset.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:54 +0000 (11:45 +0200)]
intel/fs: Remove old 16-bit shuffle/unshuffle functions
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:50 +0000 (11:45 +0200)]
intel/fs: Use shuffle_for_32bit_write for 16-bits store_ssbo
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:47 +0000 (11:45 +0200)]
intel/fs: Use shuffle_from_32bit_read to read 16-bit SSBO
Using shuffle_from_32bit_read instead of 16-bit shuffle functions
avoids the need of retype. At the same time new function are
ready for 8-bit type SSBO reads.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:42 +0000 (11:45 +0200)]
intel/fs: Use shuffle_from_32bit_read at VARYING_PULL_CONSTANT_LOAD
shuffle_from_32bit_read can manage the shuffle/unshuffle needed
for different 8/16/32/64 bit-sizes at VARYING PULL CONSTANT LOAD.
To get the specific component the first_component parameter is used.
In the case of the previous 16-bit shuffle, the shuffle operation was
generating not needed MOVs where its results where never used. This
behaviour passed unnoticed on SIMD16 because dead_code_eliminate
pass removed the generated instructions but for SIMD8 they cound't be
removed because of being partial writes.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:22 +0000 (11:45 +0200)]
intel/fs: New shuffle_for_32bit_write and shuffle_from_32bit_read
These new shuffle functions deal with the shuffle/unshuffle operations
needed for read/write operations using 32-bit components when the
read/written components have a different bit-size (8, 16, 64-bits).
Shuffle from 32-bit to 32-bit becomes a simple MOV.
shuffle_src_to_dst takes care of doing a shuffle when source type is
smaller than destination type and an unshuffle when source type is
bigger than destination. So this new read/write functions just need
to call shuffle_src_to_dst assuming that writes use a 32-bit
destination and reads use a 32-bit source.
As shuffle_for_32bit_write/from_32bit_read components take components
in unit of source/destination types and shuffle_src_to_dst takes units
of the smallest type component, we adjust components and first_component
parameters.
To enable this new functions it is needed than there is no
source/destination overlap in the case of shuffle_from_32bit_read.
That never happens on shuffle_for_32bit_write as it allocates a new
destination register as it was at shuffle_64bit_data_for_32bit_write.
v2: Reword commit log and add comments to explain why first_component
and components parameters are adjusted. (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:01 +0000 (11:45 +0200)]
intel/fs: general 8/16/32/64-bit shuffle_src_to_dst function
This new function takes care of shuffle/unshuffle components of a
particular bit-size in components with a different bit-size.
If source type size is smaller than destination type size the operation
needed is a component shuffle. The opposite case would be an unshuffle.
Component units are measured in terms of the smaller type between
source and destination. As we are un/shuffling the smaller components
from/into a bigger one.
The operation allows to skip first_component number of components from
the source.
Shuffle MOVs are retyped using integer types avoiding problems with
denorms and float types if source and destination bitsize is different.
This allows to simplify uses of shuffle functions that are dealing with
these retypes individually.
Now there is a new restriction so source and destination can not overlap
anymore when calling this shuffle function. Following patches that migrate
to use this new function will take care individually of avoiding source
and destination overlaps.
v2: (Jason Ekstrand)
- Rewrite overlap asserts.
- Manage type_sz(src.type) == type_sz(dst.type) case using MOVs
from source to dest. This works for 64-bit to 64-bits
operation that on Gen7 as it doesn't support Q registers.
- Explain that components units are based in the smallest type.
v3: - Fix unshuffle overlap assert (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Fonseca [Sat, 16 Jun 2018 09:02:15 +0000 (10:02 +0100)]
appveyor: Consume LLVM 5.0.1.
https://ci.appveyor.com/project/jrfonseca/mesa/build/47
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Bas Nieuwenhuizen [Thu, 14 Jun 2018 22:01:43 +0000 (00:01 +0200)]
ac: Clear meminfo to avoid valgrind warning.
Somehow valgrind misses that the value is initialized by the ioctl.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Fri, 15 Jun 2018 15:50:35 +0000 (17:50 +0200)]
radv: fix emitting the TCS regs on GFX9
The primitive ID is NULL and this generates an invalid
select instruction which crashes because one operand is NULL.
This fixes crashes in The Long Journey Home, Quantum Break
and Just Cause 3 with DXVK.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106756
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Ian Romanick [Wed, 6 Jun 2018 02:00:42 +0000 (19:00 -0700)]
nir: Document a couple instances of parent_instr
nir_ssa_def::parent_instr and nir_src::parent_instr have the same name,
but they mean really different things. I choose to save the next person
the hour+ that I just spent figuring that out. Even now that I know, I
doubt I'd notice in code review that someone typed foo->parent_instr
when they actually meant foo->ssa->parent_instr.
v2: Minor wording tweak in nir_ssa_def::parent_instr. Suggested by
Jason.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ian Romanick [Wed, 13 Jun 2018 17:36:42 +0000 (10:36 -0700)]
i965/fs: Propagate conditional modifiers from not instructions
Skylake
total instructions in shared programs:
14399081 ->
14399010 (<.01%)
instructions in affected programs: 26961 -> 26890 (-0.26%)
helped: 57
HURT: 0
helped stats (abs) min: 1 max: 6 x̄: 1.25 x̃: 1
helped stats (rel) min: 0.16% max: 0.80% x̄: 0.30% x̃: 0.18%
95% mean confidence interval for instructions value: -1.50 -0.99
95% mean confidence interval for instructions %-change: -0.35% -0.25%
Instructions are helped.
total cycles in shared programs:
532978307 ->
532976050 (<.01%)
cycles in affected programs: 468629 -> 466372 (-0.48%)
helped: 33
HURT: 20
helped stats (abs) min: 3 max: 360 x̄: 116.52 x̃: 98
helped stats (rel) min: 0.06% max: 3.63% x̄: 1.66% x̃: 1.27%
HURT stats (abs) min: 2 max: 172 x̄: 79.40 x̃: 43
HURT stats (rel) min: 0.04% max: 3.02% x̄: 1.48% x̃: 0.44%
95% mean confidence interval for cycles value: -81.29 -3.88
95% mean confidence interval for cycles %-change: -1.07% 0.12%
Inconclusive result (%-change mean confidence interval includes 0).
All Gen6+ platforms, except Ivy Bridge, had similar results. (Haswell shown)
total instructions in shared programs:
12973897 ->
12973838 (<.01%)
instructions in affected programs: 25970 -> 25911 (-0.23%)
helped: 55
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.07 x̃: 1
helped stats (rel) min: 0.16% max: 0.62% x̄: 0.28% x̃: 0.18%
95% mean confidence interval for instructions value: -1.14 -1.00
95% mean confidence interval for instructions %-change: -0.32% -0.24%
Instructions are helped.
total cycles in shared programs:
410355841 ->
410352067 (<.01%)
cycles in affected programs: 578454 -> 574680 (-0.65%)
helped: 47
HURT: 5
helped stats (abs) min: 3 max: 360 x̄: 85.74 x̃: 18
helped stats (rel) min: 0.05% max: 3.68% x̄: 1.18% x̃: 0.38%
HURT stats (abs) min: 2 max: 242 x̄: 51.20 x̃: 4
HURT stats (rel) min: <.01% max: 0.45% x̄: 0.15% x̃: 0.11%
95% mean confidence interval for cycles value: -104.89 -40.27
95% mean confidence interval for cycles %-change: -1.45% -0.66%
Cycles are helped.
Ivy Bridge
total instructions in shared programs:
11679351 ->
11679301 (<.01%)
instructions in affected programs: 28208 -> 28158 (-0.18%)
helped: 50
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.12% max: 0.54% x̄: 0.23% x̃: 0.16%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -0.27% -0.19%
Instructions are helped.
total cycles in shared programs:
257445362 ->
257444662 (<.01%)
cycles in affected programs: 419338 -> 418638 (-0.17%)
helped: 40
HURT: 3
helped stats (abs) min: 1 max: 170 x̄: 65.05 x̃: 24
helped stats (rel) min: 0.02% max: 3.51% x̄: 1.26% x̃: 0.41%
HURT stats (abs) min: 2 max: 1588 x̄: 634.00 x̃: 312
HURT stats (rel) min: 0.05% max: 2.97% x̄: 1.21% x̃: 0.62%
95% mean confidence interval for cycles value: -97.96 65.41
95% mean confidence interval for cycles %-change: -1.56% -0.62%
Inconclusive result (value mean confidence interval includes 0).
No changes on Iron Lake or GM45.
v2: Move 'if (cond != BRW_CONDITIONAL_Z && cond != BRW_CONDITIONAL_NZ)'
check outside the loop. Suggested by Iago.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Ian Romanick [Wed, 13 Jun 2018 17:11:31 +0000 (10:11 -0700)]
i965/fs: Rearrange code to remove most of the gotos
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Ian Romanick [Wed, 13 Jun 2018 17:04:55 +0000 (10:04 -0700)]
i965/fs: Refactor propagation of conditional modifiers from compares to adds
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Ian Romanick [Wed, 13 Jun 2018 22:07:41 +0000 (15:07 -0700)]
i965/vec4: Optimize OR with 0 into a MOV
All of the affected shaders are geometry shaders... the same ones from
the similar fs changes.
The "No changes on any other platforms" comment below is not quite
right. Without the previous change to register coalescing, this
optimization caused quite a few regressions in tests that either used
gl_ClipVertex or used different interpolation modes. I observed that
with both patches applied,
glsl-1.10/execution/interpolation/interpolation-none-gl_BackSecondaryColor-smooth-vertex.shader_test
was one instruction shorter. I suspect other shaders would be similarly
affected. Since this is all based on NOS, shader-db does not reflect
it.
Haswell
total instructions in shared programs:
12954955 ->
12954918 (<.01%)
instructions in affected programs: 3603 -> 3566 (-1.03%)
helped: 37
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.21% max: 2.50% x̄: 1.99% x̃: 2.50%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -2.30% -1.69%
Instructions are helped.
total cycles in shared programs:
410012108 ->
410012098 (<.01%)
cycles in affected programs: 3540 -> 3530 (-0.28%)
helped: 5
HURT: 0
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 0.28% max: 0.28% x̄: 0.28% x̃: 0.28%
95% mean confidence interval for cycles value: -2.00 -2.00
95% mean confidence interval for cycles %-change: -0.28% -0.28%
Cycles are helped.
Ivy Bridge
total instructions in shared programs:
11679387 ->
11679351 (<.01%)
instructions in affected programs: 3292 -> 3256 (-1.09%)
helped: 36
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.21% max: 2.50% x̄: 2.04% x̃: 2.50%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -2.34% -1.74%
Instructions are helped.
No changes on any other platforms.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Ian Romanick [Thu, 14 Jun 2018 22:26:58 +0000 (15:26 -0700)]
i965/vec4: Don't register coalesce into source of VS_OPCODE_UNPACK_FLAGS_SIMD4X2
This prevents regressions in a bunch of clipping and interpolation tests
caused by the next patch (i965/vec4: Optimize OR with 0 into a MOV).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Ian Romanick [Wed, 13 Jun 2018 19:32:27 +0000 (12:32 -0700)]
i965/fs: Optimize OR with 0 into a MOV
fs_visitor::set_gs_stream_control_data_bits generates some code like
"control_data_bits | stream_id << ((2 * (vertex_count - 1)) % 32)" as
part of EmitVertex. The first time this (dynamically) occurs in the
shader, control_data_bits is zero. Many times we can determine this
statically and various optimizations will collaborate to make one of the
OR operands literal zero.
Converting the OR to a MOV usually allows it to be copy-propagated away.
However, this does not happen in at least some shaders (in the assembly
output of shaders/closed/UnrealEngine4/EffectsCaveDemo/301.shader_test,
search for shl).
All of the affected shaders are geometry shaders.
Broadwell and Skylake had similar results. (Skylake shown)
total instructions in shared programs:
14375452 ->
14375413 (<.01%)
instructions in affected programs: 6422 -> 6383 (-0.61%)
helped: 39
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.14% max: 2.56% x̄: 1.91% x̃: 2.56%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -2.26% -1.57%
Instructions are helped.
total cycles in shared programs:
531981179 ->
531980555 (<.01%)
cycles in affected programs: 27493 -> 26869 (-2.27%)
helped: 39
HURT: 0
helped stats (abs) min: 16 max: 16 x̄: 16.00 x̃: 16
helped stats (rel) min: 0.60% max: 7.92% x̄: 5.94% x̃: 7.92%
95% mean confidence interval for cycles value: -16.00 -16.00
95% mean confidence interval for cycles %-change: -6.98% -4.90%
Cycles are helped.
No changes on earlier platforms.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Fri, 15 Jun 2018 01:05:50 +0000 (18:05 -0700)]
v3d: Handle a no-intersection scissor even if it's outside of the VP.
The min/maxes ended up producing a negative clip width/height for
dEQP-GLES3.functional.fragment_ops.scissor.outside_render_line. Just make
sure they stay at 0 (or v3d 3.x's workaround) if that happens.
Eric Anholt [Thu, 14 Jun 2018 18:32:37 +0000 (11:32 -0700)]
v3d: Use the proper depth texture type for sampling.
Fixes failing tests in dEQP-GLES3.functional.texture.shadow
Eric Anholt [Thu, 14 Jun 2018 18:17:11 +0000 (11:17 -0700)]
v3d: Limit shader threading according to our maximum TMU fifo usage.
Fixes simulator assertion failures in
dEQP-GLES3.functional.shaders.texture_functions.texture.samplercubeshadow_bias_fragment
and similar complicated cases.
Eric Anholt [Thu, 14 Jun 2018 18:04:05 +0000 (11:04 -0700)]
v3d: Fix shaders using pixel center W but no varyings.
The docs called this field "uses both center W and centroid W", but
actually it's "do you need center W even if varyings don't obviously call
for it?"
Fixes dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_w
Dylan Baker [Fri, 15 Jun 2018 20:53:25 +0000 (13:53 -0700)]
docs: Update release-notes and calendar
Dylan Baker [Fri, 15 Jun 2018 20:45:10 +0000 (13:45 -0700)]
docs: Add release notes for 18.1.2
Rafael Antognolli [Tue, 12 Jun 2018 19:18:19 +0000 (12:18 -0700)]
intel/aubinator: Use int to store getopt_long flags.
getopt_long flag parameter is an int pointer, so if we use bool to store
those values, when getopt_long writes to one of them, it might end up
overwriting the next one.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Samuel Pitoiset [Fri, 15 Jun 2018 14:50:11 +0000 (16:50 +0200)]
Revert "radv: always set/load both depth and stencil clear values"
This fixes a rendering regression with RoTR.
This reverts commit
4bdad9faddc82a4560603936ce5ade5707ecb254.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 15 Jun 2018 13:53:23 +0000 (15:53 +0200)]
radv: don't check for linear images in emit_fast_color_clear()
We don't enable CMASK for linear surfaces and addrlib only
enables DCC for tiling surfaces.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 09:06:02 +0000 (11:06 +0200)]
radv: allow RADV_PERFTEST=dccmsaa on GFX9
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 12:28:58 +0000 (14:28 +0200)]
radv: add RADV_DEBUG=checkir
This allows to run the LLVM verifier pass.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:23 +0000 (13:26 +0200)]
radv: update ZRANGE_PRECISION in radv_update_bound_fast_clear_ds()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:22 +0000 (13:26 +0200)]
radv: clean up radv_{set,load}_depth_clear_regs() helpers
And replace _regs by _metadata because it makes more sense.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:21 +0000 (13:26 +0200)]
radv: always set/load both depth and stencil clear values
I don't think that matter much to emit both values and that
makes the code a bit simpler.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:20 +0000 (13:26 +0200)]
radv: update the fast ds clear values only if the image is bound
It's unnecessary to update the fast depth/stencil clear values
if the fast cleared depth/stencil image isn't currently bound.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:19 +0000 (13:26 +0200)]
radv: clean up radv_{set,load}_color_clear_regs() helpers
And replace _regs by _metadata because it makes more sense.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:18 +0000 (13:26 +0200)]
radv: update the fast color clear values only if the image is bound
It's unnecessary to update the fast color clear values if the
fast cleared color image isn't currently bound.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Christian Gmeiner [Fri, 15 Jun 2018 10:18:56 +0000 (12:18 +0200)]
util/bitset: include util/macro.h
BITSET_FFS(x) macro makes use of ARRAY_SIZE(x) macro which is
defined in util/macro.h. Include it directy to make usage more
straightforward.
Fixes:
692bd4a1ab9 ("util: replace Elements() with ARRAY_SIZE()")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Lukas Rusak [Mon, 4 Jun 2018 19:38:41 +0000 (12:38 -0700)]
meson: fix private libs when building without glx
I noticed that the generated pkg-config files will include
glx and x11 dependencies even when x11 isn't a selected platform.
This fixes the private libs and was tested by building kmscube
V2:
- check if gallium-xlib is being used for glx
Fixes:
108d257a16859898f5ce0 "meson: build libEGL"
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
docs: document addition of GL_ARB_sample_locations for nvc0
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
nvc0: add support for programmable sample locations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
st/mesa: add support for ARB_sample_locations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
gallium: add support for programmable sample locations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
mesa: add support for ARB_sample_locations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Eric Anholt [Wed, 13 Jun 2018 20:44:01 +0000 (13:44 -0700)]
v3d: Fix polygon offset for Z16 buffers.
Fixes:
dEQP-GLES3.functional.polygon_offset.fixed16_displacement_with_units
dEQP-GLES3.functional.polygon_offset.fixed16_render_with_units
Eric Anholt [Wed, 13 Jun 2018 20:38:33 +0000 (13:38 -0700)]
v3d: Fix configuration setup of mixed f32 and f16 render targets.
Fixes dEQP-GLES3.functional.fragment_out.random.26 and 6 others.
Eric Anholt [Wed, 13 Jun 2018 19:58:22 +0000 (12:58 -0700)]
v3d: Don't set the first_ez_state to DISABLED if after only UNDECIDED draws.
We need to have the RCL start with EZ enabled, since those undecided draws
had EZ enabled. But we do need to update from UNDECIDED to LT or GT as
necessary still.
Fixes many simulator assertion fails in deqp
fragment_ops/interaction/basic_shader/*
Eric Anholt [Fri, 8 Jun 2018 15:35:50 +0000 (08:35 -0700)]
v3d: Use the right size for v3d 4.x TEXTURE_SHADER_STATE BO.
This doesn't really matter, since they both get rounded up to 4096.
Eric Anholt [Fri, 8 Jun 2018 15:31:58 +0000 (08:31 -0700)]
v3d: Add static asserts for other packed packet sizes.
Eric Anholt [Fri, 8 Jun 2018 15:31:30 +0000 (08:31 -0700)]
v3d: Fix the size of the packed attribute state.
Fixes segfaults in dEQP-GLES3.functional.vertex_array_objects.all_attributes.
Eric Anholt [Fri, 8 Jun 2018 15:04:00 +0000 (08:04 -0700)]
v3d: Remove some unused context fields from vc4.
Eric Anholt [Fri, 8 Jun 2018 15:32:34 +0000 (08:32 -0700)]
v3d: Remove unused QUNIFORM_STENCIL left over from vc4.
Eric Anholt [Fri, 8 Jun 2018 15:00:31 +0000 (08:00 -0700)]
v3d: Use our #define for max attributes in shader caps.
Eric Anholt [Thu, 7 Jun 2018 04:06:44 +0000 (21:06 -0700)]
v3d: Fix undefined results for a swap_color_rb RT from a float shader output.
Fixes segfaults and undefined behavior in
dEQP-GLES3.functional.fragment_out.basic.fixed.srgb8_alpha8_lowp_float
Dave Airlie [Thu, 14 Jun 2018 22:48:54 +0000 (08:48 +1000)]
radv: remove multisample bit from shader key.
This wasn't being used anywhere inside the shader from what I can see.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Fri, 8 Jun 2018 21:24:16 +0000 (14:24 -0700)]
intel/compiler: Properly consider UBO loads that cross 32B boundaries.
The UBO push analysis pass incorrectly assumed that all values would fit
within a 32B chunk, and only recorded a bit for the 32B chunk containing
the starting offset.
For example, if a UBO contained the following, tightly packed:
vec4 a; // [0, 16)
float b; // [16, 20)
vec4 c; // [20, 36)
then, c would start at offset 20 / 32 = 0 and end at 36 / 32 = 1,
which means that we ought to record two 32B chunks in the bitfield.
Similarly, dvec4s would suffer from the same problem.
v2: Rewrite the accounting, my calculations were wrong.
v3: Write a comment about partial values (requested by Jason).
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> [v1]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v3]
Ian Romanick [Tue, 5 Jun 2018 23:02:25 +0000 (16:02 -0700)]
glsl: Don't copy propagate elements from SSBO or shared variables either
Since SSBOs can be written by a different GPU thread, copy propagating a
read can cause the value to magically change. SSBO reads are also very
expensive, so doing it twice will be slower.
The same shader was helped by this patch and the previous.
Haswell, Broadwell, and Skylake had similar results. (Skylake shown)
total instructions in shared programs:
14399119 ->
14399113 (<.01%)
instructions in affected programs: 683 -> 677 (-0.88%)
helped: 1
HURT: 0
total cycles in shared programs:
532973113 ->
532971865 (<.01%)
cycles in affected programs: 524666 -> 523418 (-0.24%)
helped: 1
HURT: 0
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106774
Ian Romanick [Tue, 5 Jun 2018 22:04:24 +0000 (15:04 -0700)]
glsl: Don't copy propagate from SSBO or shared variables either
Since SSBOs can be written by other GPU threads, copy propagating a read
can cause the value to magically change. SSBO reads are also very
expensive, so doing it twice will be slower.
Haswell, Broadwell, and Skylake had similar results. (Skylake shown)
total instructions in shared programs:
14399120 ->
14399119 (<.01%)
instructions in affected programs: 684 -> 683 (-0.15%)
helped: 1
HURT: 0
total cycles in shared programs:
532978931 ->
532973113 (<.01%)
cycles in affected programs: 530484 -> 524666 (-1.10%)
helped: 1
HURT: 0
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106774
Lukas Rusak [Fri, 1 Jun 2018 21:09:42 +0000 (14:09 -0700)]
meson: only build vl_winsys_dri.c when x11 platform is used
This seems to have been missed in the move from autotools
This fixes the following build issue:
../src/gallium/auxiliary/vl/vl_winsys_dri.c:34:10: fatal error: X11/Xlib-xcb.h: No such file or directory
#include <X11/Xlib-xcb.h>
^~~~~~~~~~~~~~~~
Fixes:
b1b65397d0c4978e36a84c0a1c98a4bd6cb9588e
("meson: Build gallium auxiliary")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Brian Paul [Thu, 14 Jun 2018 15:12:19 +0000 (09:12 -0600)]
st/mesa: add missing switch cases in glsl_to_tgsi_visitor::visit()
To silence compiler warning about unhandled switch cases.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Bas Nieuwenhuizen [Wed, 13 Jun 2018 21:31:54 +0000 (23:31 +0200)]
radv: Fix output for sparse MRTs.
We need to init the cb_shader_format correctly with the changed
col_format, so this moves the col_format adjustment to before the
adjustment to before the cb_shader_mask gets generated.
Fixes:
06d3c650980 "radv: fix a GPU hang when MRTs are sparse"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106903
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 13 Jun 2018 12:27:40 +0000 (14:27 +0200)]
radv: update the ZRANGE_PRECISION value for the TC-compat bug
On GFX8+, there is a bug that affects TC-compatible depth surfaces
when the ZRange is not reset after LateZ kills pixels.
The workaround is to always set DB_Z_INFO.ZRANGE_PRECISION to match
the last fast clear value. Because the value is set to 1 by default,
we only need to update it when clearing Z to 0.0.
We also need to set the depth clear regs and to update
ZRANGE_PRECISION when initializing a TC-compat depth image to 0.
Original patch from James Legg.
This fixes random CTS fails with
dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.input.*
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105396
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Iglesias Gonsálvez [Mon, 28 May 2018 09:42:15 +0000 (11:42 +0200)]
anv: reduce maxFragmentInputComponents
If the application asks for the maximum number of fragment input
components (128), use all of them plus some builtins that are
passed in the VUE, then we exceed the maximum number of used VUE
slots (32) and we break one assert that checks this limit.
Also, with separate shader objects, we add CLIP_DIST0, CLIP_DIST1
builtins in brw_compute_vue_map() because we don't know if
gl_ClipDistance is going to be read/write by an adjacent stage.
Fixes VK-GL-CTS CL#2569.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Fri, 1 Jun 2018 23:29:45 +0000 (19:29 -0400)]
radeonsi/gfx9: fix si_get_buffer_from_descriptors for 48-bit pointers
This fixes:
GL45-CTS.pipeline_statistics_query_tests_ARB.functional_compute_shader_invocations
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Fri, 1 Jun 2018 04:33:57 +0000 (00:33 -0400)]
radeonsi/gfx9: update & clean up a DPBB heuristic
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 1 Jun 2018 04:21:49 +0000 (00:21 -0400)]
radeonsi/gfx9: set POPS_DRAIN_PS_ON_OVERLAP due to a hw bug
This may not be needed yet, but let's set it now.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 1 Jun 2018 04:06:35 +0000 (00:06 -0400)]
radeonsi/gfx9: remove UINT_MAX array terminators in bin size tables
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 1 Jun 2018 03:48:03 +0000 (23:48 -0400)]
radeonsi/gfx9: update bin sizes
This is based on our docs (recently updated), not amdvlk.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 1 Jun 2018 03:47:17 +0000 (23:47 -0400)]
radeonsi/gfx9: update primitive binning code for EQAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 03:21:28 +0000 (23:21 -0400)]
radeonsi: assume that rasterizer state is non-NULL in draw_vbo
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 02:59:41 +0000 (22:59 -0400)]
radeonsi: micro-optimize prim checking and fix guardband with lines+adjacency
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 02:38:05 +0000 (22:38 -0400)]
radeonsi: move the guardband registers into a separate state atom
They have a different frequency of updates and don't change when scissors
change.
I think this even fixes something in si_update_vs_viewport_state.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 02:02:00 +0000 (22:02 -0400)]
radeonsi/gfx9: implement the scissor bug workaround without performance drop
This might improve performance on Vega10 and Raven.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 01:24:06 +0000 (21:24 -0400)]
radeonsi: don't set VGT_LS_HS_CONFIG if it doesn't change
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 01:16:14 +0000 (21:16 -0400)]
radeonsi: move VGT_GS_OUT_PRIM_TYPE into si_shader_gs
same as amdvlk.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 25 May 2018 21:37:51 +0000 (17:37 -0400)]
radeonsi: record CLIPVERTEX output usage properly for compatibility profiles
This was missed when adding CLIPVERTEX support into GS & tess.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 18 May 2018 03:26:56 +0000 (23:26 -0400)]
radeonsi: fix FBFETCH with 2D MSAA arrays
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>