OSDN Git Service
Richard Henderson [Sat, 6 May 2023 07:11:52 +0000 (08:11 +0100)]
Merge tag 'pull-loongarch-
20230506' of https://gitlab.com/gaosong/qemu into staging
Add LoongArch LSX instructions.
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# gpg: Signature made Sat 06 May 2023 07:18:03 AM BST
# gpg: using RSA key
B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
* tag 'pull-loongarch-
20230506' of https://gitlab.com/gaosong/qemu: (45 commits)
hw/intc: don't use target_ulong for LoongArch ipi
target/loongarch: CPUCFG support LSX
target/loongarch: Use {set/get}_gpr replace to cpu_fpr
target/loongarch: Implement vldi
target/loongarch: Implement vld vst
target/loongarch: Implement vilvl vilvh vextrins vshuf
target/loongarch: Implement vreplve vpack vpick
target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr
target/loongarch: Implement vbitsel vset
target/loongarch: Implement vfcmp
target/loongarch: Implement vseq vsle vslt
target/loongarch: Implement LSX fpu fcvt instructions
target/loongarch: Implement LSX fpu arith instructions
target/loongarch: Implement vfrstp
target/loongarch: Implement vbitclr vbitset vbitrev
target/loongarch: Implement vpcnt
target/loongarch: Implement vclo vclz
target/loongarch: Implement vssrlrn vssrarn
target/loongarch: Implement vssrln vssran
target/loongarch: Implement vsrlrn vsrarn
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alex Bennée [Tue, 4 Apr 2023 13:27:11 +0000 (14:27 +0100)]
hw/intc: don't use target_ulong for LoongArch ipi
The calling function is already working with hwaddr and uint64_t so
lets avoid bringing target_ulong in if we don't need to.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230404132711.
2563638-1-alex.bennee@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:10 +0000 (20:28 +0800)]
target/loongarch: CPUCFG support LSX
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-45-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:09 +0000 (20:28 +0800)]
target/loongarch: Use {set/get}_gpr replace to cpu_fpr
Introduce set_fpr() and get_fpr() and remove cpu_fpr.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-44-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:08 +0000 (20:28 +0800)]
target/loongarch: Implement vldi
This patch includes:
- VLDI.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-43-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:07 +0000 (20:28 +0800)]
target/loongarch: Implement vld vst
This patch includes:
- VLD[X], VST[X];
- VLDREPL.{B/H/W/D};
- VSTELM.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-42-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:06 +0000 (20:28 +0800)]
target/loongarch: Implement vilvl vilvh vextrins vshuf
This patch includes:
- VILV{L/H}.{B/H/W/D};
- VSHUF.{B/H/W/D};
- VSHUF4I.{B/H/W/D};
- VPERMI.W;
- VEXTRINS.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-41-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:05 +0000 (20:28 +0800)]
target/loongarch: Implement vreplve vpack vpick
This patch includes:
- VREPLVE[I].{B/H/W/D};
- VBSLL.V, VBSRL.V;
- VPACK{EV/OD}.{B/H/W/D};
- VPICK{EV/OD}.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-40-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:04 +0000 (20:28 +0800)]
target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr
This patch includes:
- VINSGR2VR.{B/H/W/D};
- VPICKVE2GR.{B/H/W/D}[U];
- VREPLGR2VR.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-39-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:03 +0000 (20:28 +0800)]
target/loongarch: Implement vbitsel vset
This patch includes:
- VBITSEL.V;
- VBITSELI.B;
- VSET{EQZ/NEZ}.V;
- VSETANYEQZ.{B/H/W/D};
- VSETALLNEZ.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-38-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:02 +0000 (20:28 +0800)]
target/loongarch: Implement vfcmp
This patch includes:
- VFCMP.cond.{S/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-37-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:01 +0000 (20:28 +0800)]
target/loongarch: Implement vseq vsle vslt
This patch includes:
- VSEQ[I].{B/H/W/D};
- VSLE[I].{B/H/W/D}[U];
- VSLT[I].{B/H/W/D/}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-36-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:00 +0000 (20:28 +0800)]
target/loongarch: Implement LSX fpu fcvt instructions
This patch includes:
- VFCVT{L/H}.{S.H/D.S};
- VFCVT.{H.S/S.D};
- VFRINT[{RNE/RZ/RP/RM}].{S/D};
- VFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- VFTINT[RZ].{WU.S/LU.D};
- VFTINT[{RNE/RZ/RP/RM}].W.D;
- VFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- VFFINT.{S.W/D.L}[U];
- VFFINT.S.L, VFFINT{L/H}.D.W.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-35-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:59 +0000 (20:27 +0800)]
target/loongarch: Implement LSX fpu arith instructions
This patch includes:
- VF{ADD/SUB/MUL/DIV}.{S/D};
- VF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- VF{MAX/MIN}.{S/D};
- VF{MAXA/MINA}.{S/D};
- VFLOGB.{S/D};
- VFCLASS.{S/D};
- VF{SQRT/RECIP/RSQRT}.{S/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-34-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:58 +0000 (20:27 +0800)]
target/loongarch: Implement vfrstp
This patch includes:
- VFRSTP[I].{B/H}.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-33-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:57 +0000 (20:27 +0800)]
target/loongarch: Implement vbitclr vbitset vbitrev
This patch includes:
- VBITCLR[I].{B/H/W/D};
- VBITSET[I].{B/H/W/D};
- VBITREV[I].{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-32-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:56 +0000 (20:27 +0800)]
target/loongarch: Implement vpcnt
This patch includes:
- VPCNT.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-31-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:55 +0000 (20:27 +0800)]
target/loongarch: Implement vclo vclz
This patch includes:
- VCLO.{B/H/W/D};
- VCLZ.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-30-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:54 +0000 (20:27 +0800)]
target/loongarch: Implement vssrlrn vssrarn
This patch includes:
- VSSRLRN.{B.H/H.W/W.D};
- VSSRARN.{B.H/H.W/W.D};
- VSSRLRN.{BU.H/HU.W/WU.D};
- VSSRARN.{BU.H/HU.W/WU.D};
- VSSRLRNI.{B.H/H.W/W.D/D.Q};
- VSSRARNI.{B.H/H.W/W.D/D.Q};
- VSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-29-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:53 +0000 (20:27 +0800)]
target/loongarch: Implement vssrln vssran
This patch includes:
- VSSRLN.{B.H/H.W/W.D};
- VSSRAN.{B.H/H.W/W.D};
- VSSRLN.{BU.H/HU.W/WU.D};
- VSSRAN.{BU.H/HU.W/WU.D};
- VSSRLNI.{B.H/H.W/W.D/D.Q};
- VSSRANI.{B.H/H.W/W.D/D.Q};
- VSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-28-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:52 +0000 (20:27 +0800)]
target/loongarch: Implement vsrlrn vsrarn
This patch includes:
- VSRLRN.{B.H/H.W/W.D};
- VSRARN.{B.H/H.W/W.D};
- VSRLRNI.{B.H/H.W/W.D/D.Q};
- VSRARNI.{B.H/H.W/W.D/D.Q}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-27-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:51 +0000 (20:27 +0800)]
target/loongarch: Implement vsrln vsran
This patch includes:
- VSRLN.{B.H/H.W/W.D};
- VSRAN.{B.H/H.W/W.D};
- VSRLNI.{B.H/H.W/W.D/D.Q};
- VSRANI.{B.H/H.W/W.D/D.Q}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-26-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:50 +0000 (20:27 +0800)]
target/loongarch: Implement vsrlr vsrar
This patch includes:
- VSRLR[I].{B/H/W/D};
- VSRAR[I].{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-25-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:49 +0000 (20:27 +0800)]
target/loongarch: Implement vsllwil vextl
This patch includes:
- VSLLWIL.{H.B/W.H/D.W};
- VSLLWIL.{HU.BU/WU.HU/DU.WU};
- VEXTL.Q.D, VEXTL.QU.DU.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-24-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:48 +0000 (20:27 +0800)]
target/loongarch: Implement vsll vsrl vsra vrotr
This patch includes:
- VSLL[I].{B/H/W/D};
- VSRL[I].{B/H/W/D};
- VSRA[I].{B/H/W/D};
- VROTR[I].{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-23-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:47 +0000 (20:27 +0800)]
target/loongarch: Implement LSX logic instructions
This patch includes:
- V{AND/OR/XOR/NOR/ANDN/ORN}.V;
- V{AND/OR/XOR/NOR}I.B.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-22-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:46 +0000 (20:27 +0800)]
target/loongarch: Implement vmskltz/vmskgez/vmsknz
This patch includes:
- VMSKLTZ.{B/H/W/D};
- VMSKGEZ.B;
- VMSKNZ.B.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-21-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:45 +0000 (20:27 +0800)]
target/loongarch: Implement vsigncov
This patch includes:
- VSIGNCOV.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-20-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:44 +0000 (20:27 +0800)]
target/loongarch: Implement vexth
This patch includes:
- VEXTH.{H.B/W.H/D.W/Q.D};
- VEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-19-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:43 +0000 (20:27 +0800)]
target/loongarch: Implement vsat
This patch includes:
- VSAT.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-18-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:42 +0000 (20:27 +0800)]
target/loongarch: Implement vdiv/vmod
This patch includes:
- VDIV.{B/H/W/D}[U];
- VMOD.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-17-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:41 +0000 (20:27 +0800)]
target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}
This patch includes:
- VMADD.{B/H/W/D};
- VMSUB.{B/H/W/D};
- VMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-16-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:40 +0000 (20:27 +0800)]
target/loongarch: Implement vmul/vmuh/vmulw{ev/od}
This patch includes:
- VMUL.{B/H/W/D};
- VMUH.{B/H/W/D}[U];
- VMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-15-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:39 +0000 (20:27 +0800)]
target/loongarch: Implement vmax/vmin
This patch includes:
- VMAX[I].{B/H/W/D}[U];
- VMIN[I].{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-14-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:38 +0000 (20:27 +0800)]
target/loongarch: Implement vadda
This patch includes:
- VADDA.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-13-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:37 +0000 (20:27 +0800)]
target/loongarch: Implement vabsd
This patch includes:
- VABSD.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-12-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:36 +0000 (20:27 +0800)]
target/loongarch: Implement vavg/vavgr
This patch includes:
- VAVG.{B/H/W/D}[U];
- VAVGR.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-11-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:35 +0000 (20:27 +0800)]
target/loongarch: Implement vaddw/vsubw
This patch includes:
- VADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-10-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:34 +0000 (20:27 +0800)]
target/loongarch: Implement vhaddw/vhsubw
This patch includes:
- VHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- VHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-9-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:33 +0000 (20:27 +0800)]
target/loongarch: Implement vsadd/vssub
This patch includes:
- VSADD.{B/H/W/D}[U];
- VSSUB.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-8-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:32 +0000 (20:27 +0800)]
target/loongarch: Implement vneg
This patch includes;
- VNEG.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-7-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:31 +0000 (20:27 +0800)]
target/loongarch: Implement vaddi/vsubi
This patch includes:
- VADDI.{B/H/W/D}U;
- VSUBI.{B/H/W/D}U.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-6-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:30 +0000 (20:27 +0800)]
target/loongarch: Implement vadd/vsub
This patch includes:
- VADD.{B/H/W/D/Q};
- VSUB.{B/H/W/D/Q}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-5-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:29 +0000 (20:27 +0800)]
target/loongarch: Add CHECK_SXE maccro for check LSX enable
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-4-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:28 +0000 (20:27 +0800)]
target/loongarch: meson.build support build LSX
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-3-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:27 +0000 (20:27 +0800)]
target/loongarch: Add LSX data type VReg
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230504122810.
4094787-2-gaosong@loongson.cn>
Richard Henderson [Fri, 5 May 2023 21:29:28 +0000 (22:29 +0100)]
Merge tag 'pull-tcg-
20230505' of https://gitlab.com/rth7680/qemu into staging
softfloat: Fix the incorrect computation in float32_exp2
tcg: Remove compatability helpers for qemu ld/st
target/alpha: Remove TARGET_ALIGNED_ONLY
target/hppa: Remove TARGET_ALIGNED_ONLY
target/sparc: Remove TARGET_ALIGNED_ONLY
tcg: Cleanups preparing to unify calls to qemu_ld/st helpers
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# gpg: Signature made Fri 05 May 2023 10:23:33 PM BST
# gpg: using RSA key
7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-
20230505' of https://gitlab.com/rth7680/qemu: (42 commits)
tcg: Widen helper_*_st[bw]_mmu val arguments
tcg: Introduce arg_slot_stk_ofs
tcg: Replace REG_P with arg_loc_reg_p
tcg: Move TCGLabelQemuLdst to tcg.c
tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}
tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return
tcg/s390x: Introduce HostAddress
tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}
tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}
tcg/riscv: Require TCG_TARGET_REG_BITS == 64
tcg/ppc: Introduce HostAddress
tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}
tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}
tcg/loongarch64: Introduce HostAddress
tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld,st}
tcg/arm: Introduce HostAddress
tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}
tcg/aarch64: Introduce HostAddress
tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st}
tcg/i386: Introduce tcg_out_testi
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 5 May 2023 21:28:48 +0000 (22:28 +0100)]
Merge tag 'pull-ppc-
20230505' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2023-05-05:
This queue includes fixes for ppc and spapr emulation, a build fix for
the pseries machine and a new reviewer for ppc/spapr.
We're also carrying a Coverity fix for the sm501 display.
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# gpg: Signature made Fri 05 May 2023 05:26:00 PM BST
# gpg: using EDDSA key
17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-
20230505' of https://gitlab.com/danielhb/qemu:
hw/ppc/Kconfig: NVDIMM is a hard requirement for the pseries machine
tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions
tcg: ppc64: Fix mask generation for vextractdm
MAINTAINERS: Adding myself in the list for ppc/spapr
ppc: spapr: cleanup cr get/set with helpers.
hw/display/sm501: Remove unneeded increment from loop
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 5 May 2023 18:18:05 +0000 (19:18 +0100)]
Merge tag 'pw-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging
Add PipeWire audio backend
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# gpg: Signature made Fri 05 May 2023 12:37:27 PM BST
# gpg: using RSA key
87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg: issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full]
# gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full]
* tag 'pw-pull-request' of https://gitlab.com/marcandre.lureau/qemu:
audio/pwaudio.c: Add Pipewire audio backend for QEMU
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 5 May 2023 18:17:44 +0000 (19:17 +0100)]
Merge tag 'migration-
20230505-pull-request' of https://gitlab.com/juan.quintela/qemu into staging
Migration Pull request (
20230505 edition)
In this series:
- fix block_bitmap_mapping (juan)
- RDMA cleanup (juan)
- qemu file cleanup (juan)
Please apply.
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# gpg: Signature made Fri 05 May 2023 01:47:17 AM BST
# gpg: using RSA key
1899FF8EDEBF58CCEE034B82F487EF185872D723
# gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [undefined]
# gpg: aka "Juan Quintela <quintela@trasno.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723
* tag 'migration-
20230505-pull-request' of https://gitlab.com/juan.quintela/qemu:
qemu-file: Make ram_control_save_page() use accessors for rate_limit
qemu-file: Make total_transferred an uint64_t
qemu-file: remove shutdown member
qemu-file: No need to check for shutdown in qemu_file_rate_limit
migration: qemu_file_total_transferred() function is monotonic
migration: max_postcopy_bandwidth is a size parameter
migration/rdma: Check for postcopy sooner
migration/rdma: It makes no sense to recive that flag without RDMA
migration/rdma: We can calculate the rioc from the QEMUFile
migration/rdma: simplify ram_control_load_hook()
migration: Make RAM_SAVE_FLAG_HOOK a normal case entry
migration: Rename xbzrle_enabled xbzrle_started
migration: Put zero_pages in alphabetical order
migration: Document all migration_stats
migration/rdma: Don't pass the QIOChannelRDMA as an opaque
migration: Fix block_bitmap_mapping migration
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 10 Apr 2023 05:11:39 +0000 (22:11 -0700)]
tcg: Widen helper_*_st[bw]_mmu val arguments
While the old type was correct in the ideal sense, some ABIs require
the argument to be zero-extended. Using uint32_t for all such values
is a decent compromise.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 9 Apr 2023 02:05:10 +0000 (19:05 -0700)]
tcg: Introduce arg_slot_stk_ofs
Unify all computation of argument stack offset in one function.
This requires that we adjust ref_slot to be in the same units,
by adding max_reg_slots during init_call_layout.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 9 Apr 2023 00:28:07 +0000 (17:28 -0700)]
tcg: Replace REG_P with arg_loc_reg_p
An inline function is safer than a macro, and REG_P
was rather too generic.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 7 Apr 2023 23:18:03 +0000 (18:18 -0500)]
tcg: Move TCGLabelQemuLdst to tcg.c
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 8 Apr 2023 00:32:51 +0000 (19:32 -0500)]
tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}
We need to set this in TCGLabelQemuLdst, so plumb this
all the way through from tcg_out_op.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 8 Apr 2023 00:26:24 +0000 (19:26 -0500)]
tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return
In tcg_canonicalize_memop, we remove MO_SIGN from MO_32 operations
with TCG_TYPE_I32. Thus this is never set. We already have an
identical test just above which does not include is_64
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 23 Apr 2023 20:28:57 +0000 (21:28 +0100)]
tcg/s390x: Introduce HostAddress
Collect the 3 potential parts of the host address into a struct.
Reorg tcg_out_qemu_{ld,st}_direct to use it.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 6 Apr 2023 19:57:43 +0000 (12:57 -0700)]
tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}
We need to set this in TCGLabelQemuLdst, so plumb this
all the way through from tcg_out_op.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 6 Apr 2023 20:27:16 +0000 (13:27 -0700)]
tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}
Interpret the variable argument placement in the caller. Pass data_type
instead of is64 -- there are several places where we already convert back
from bool to type. Clean things up by using type throughout.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 23 Mar 2023 23:03:18 +0000 (23:03 +0000)]
tcg/riscv: Require TCG_TARGET_REG_BITS == 64
The port currently does not support "oversize" guests, which
means riscv32 can only target 32-bit guests. We will soon be
building TCG once for all guests. This implies that we can
only support riscv64.
Since all Linux distributions target riscv64 not riscv32,
this is not much of a restriction and simplifies the code.
The brcond2 and setcond2 opcodes are exclusive to 32-bit hosts,
so we can and should remove the stubs.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 23 Apr 2023 19:10:00 +0000 (20:10 +0100)]
tcg/ppc: Introduce HostAddress
Collect the parts of the host address into a struct.
Reorg tcg_out_qemu_{ld,st} to use it.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 6 Apr 2023 19:53:46 +0000 (12:53 -0700)]
tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}
Interpret the variable argument placement in the caller. Pass data_type
instead of is64 -- there are several places where we already convert back
from bool to type. Clean things up by using type throughout.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 6 Apr 2023 19:52:26 +0000 (12:52 -0700)]
tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}
Interpret the variable argument placement in the caller. There are
several places where we already convert back from bool to type.
Clean things up by using type throughout.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 23 Apr 2023 15:31:16 +0000 (16:31 +0100)]
tcg/loongarch64: Introduce HostAddress
Collect the 2 parts of the host address into a struct.
Reorg tcg_out_qemu_{ld,st}_direct to use it.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 8 Apr 2023 22:13:04 +0000 (15:13 -0700)]
tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld,st}
Interpret the variable argument placement in the caller. Shift some
code around slightly to share more between softmmu and user-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 22 Apr 2023 04:32:22 +0000 (05:32 +0100)]
tcg/arm: Introduce HostAddress
Collect the parts of the host address, and condition, into a struct.
Merge tcg_out_qemu_*_{index,direct} and use it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 6 Apr 2023 19:51:01 +0000 (12:51 -0700)]
tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}
Interpret the variable argument placement in the caller.
Pass data_type instead of is_64. We need to set this in
TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 21 Apr 2023 08:52:25 +0000 (09:52 +0100)]
tcg/aarch64: Introduce HostAddress
Collect the 3 potential parts of the host address into a struct.
Reorg tcg_out_qemu_{ld,st}_direct to use it.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 6 Apr 2023 19:47:15 +0000 (12:47 -0700)]
tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st}
Rename the 'ext' parameter 'data_type' to make the use clearer;
pass it to tcg_out_qemu_st as well to even out the interfaces.
Rename the 'otype' local 'addr_type' to make the use clearer.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 8 Nov 2022 03:30:27 +0000 (14:30 +1100)]
tcg/i386: Introduce tcg_out_testi
Split out a helper for choosing testb vs testl.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 19 Apr 2023 16:43:35 +0000 (18:43 +0200)]
tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load
Use TCG_REG_L[01] constants directly.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 19 Apr 2023 16:29:14 +0000 (18:29 +0200)]
tcg/i386: Introduce HostAddress
Collect the 4 potential parts of the host address into a struct.
Reorg tcg_out_qemu_{ld,st}_direct to use it.
Reorg guest_base handling to use it.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 16 Apr 2023 13:56:41 +0000 (15:56 +0200)]
tcg/i386: Generalize multi-part load overlap test
Test for both base and index; use datahi as a temporary, overwritten
by the final load. Always perform the loads in ascending order, so
that any (user-only) fault sees the correct address.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 6 Apr 2023 19:42:40 +0000 (12:42 -0700)]
tcg/i386: Rationalize args to tcg_out_qemu_{ld,st}
Interpret the variable argument placement in the caller. Pass data_type
instead of is64 -- there are several places where we already convert back
from bool to type. Clean things up by using type throughout.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 15:15:23 +0000 (16:15 +0100)]
target/sparc: Remove TARGET_ALIGNED_ONLY
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 15:14:19 +0000 (16:14 +0100)]
target/sparc: Use cpu_ld*_code_mmu
This passes on the memop as given as argument to
helper_ld_asi to the ultimate load primitive.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 15:12:44 +0000 (16:12 +0100)]
target/sparc: Use MO_ALIGN where required
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 08:53:13 +0000 (09:53 +0100)]
target/hppa: Remove TARGET_ALIGNED_ONLY
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 14:30:10 +0000 (15:30 +0100)]
target/hppa: Use MO_ALIGN for system UNALIGN()
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 08:43:44 +0000 (09:43 +0100)]
target/alpha: Remove TARGET_ALIGNED_ONLY
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 14:36:47 +0000 (15:36 +0100)]
target/alpha: Use MO_ALIGN where required
Mark all memory operations that are not already marked with UNALIGN.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 14:31:25 +0000 (15:31 +0100)]
target/alpha: Use MO_ALIGN for system UNALIGN()
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 13:57:41 +0000 (14:57 +0100)]
tcg: Remove compatability helpers for qemu ld/st
Remove the old interfaces with the implicit MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Hildenbrand <david@redhat.com>
Message-Id: <
20230502135741.
1158035-10-richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 13:57:40 +0000 (14:57 +0100)]
target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Message-Id: <
20230502135741.
1158035-9-richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 13:57:39 +0000 (14:57 +0100)]
target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_*
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <
20230502135741.
1158035-8-richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 13:57:38 +0000 (14:57 +0100)]
target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_*
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <
20230502135741.
1158035-7-richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 13:57:37 +0000 (14:57 +0100)]
target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <
20230502135741.
1158035-6-richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 13:57:36 +0000 (14:57 +0100)]
target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_*
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <
20230502135741.
1158035-5-richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 13:57:35 +0000 (14:57 +0100)]
target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*
Convert away from the old interface with the implicit
MemOp argument. Importantly, this removes some incorrect
casts generated by idef-parser's gen_load().
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <
20230502135741.
1158035-4-richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 13:57:34 +0000 (14:57 +0100)]
target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_*
Convert away from the old interface with the implicit
MemOp argument. In this case we can fold the calls
using the size bits of MemOp.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <
20230502135741.
1158035-3-richard.henderson@linaro.org>
Richard Henderson [Tue, 2 May 2023 13:57:33 +0000 (14:57 +0100)]
target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <
20230502135741.
1158035-2-richard.henderson@linaro.org>
Shivaprasad G Bhat [Tue, 2 May 2023 15:25:30 +0000 (20:55 +0530)]
softfloat: Fix the incorrect computation in float32_exp2
The float32_exp2 function is computing wrong exponent of 2.
For example, with the following set of values {0.1, 2.0, 2.0, -1.0},
the expected output would be {1.071773, 4.000000, 4.000000, 0.500000}.
Instead, the function is computing {1.119102, 3.382044, 3.382044, -0.191022}
Looking at the code, the float32_exp2() attempts to do this
2 3 4 5 n
x x x x x x x
e = 1 + --- + --- + --- + --- + --- + ... + --- + ...
1! 2! 3! 4! 5! n!
But because of the typo it ends up doing
x x x x x x x
e = 1 + --- + --- + --- + --- + --- + ... + --- + ...
1! 2! 3! 4! 5! n!
This is because instead of the xnp which holds the numerator, parts_muladd
is using the xp which is just 'x'. Commit '
572c4d862ff2' refactored this
function, and mistakenly used xp instead of xnp.
Cc: qemu-stable@nongnu.org
Fixes:
572c4d862ff2 "softfloat: Convert float32_exp2 to FloatParts"
Partially-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1623
Reported-By: Luca Barbato (https://gitlab.com/lu-zero)
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
Message-Id: <
168304110865.537992.
13059030916325018670.stgit@localhost.localdomain>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Thomas Huth [Thu, 4 May 2023 18:05:21 +0000 (20:05 +0200)]
hw/ppc/Kconfig: NVDIMM is a hard requirement for the pseries machine
When building QEMU with "--without-default-devices", the pseries
machine fails to start even when running with the --nodefaults option:
$ ./qemu-system-ppc64 --nodefaults -M pseries
Type 'spapr-nvdimm' is missing its parent 'nvdimm'
Aborted (core dumped)
Looks like NVDIMM is a hard requirement for this machine nowadays.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20230504180521.220404-1-thuth@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Shivaprasad G Bhat [Thu, 4 May 2023 09:36:04 +0000 (05:36 -0400)]
tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions
Add test for vextractbm, vextractwm, vextractdm and vextractqm
instructions. Test works for both qemu-ppc64 and qemu-ppc64le.
Based on the test case written by John Platts posted at [1]
References:
[1] - https://gitlab.com/qemu-project/qemu/-/issues/1536
Signed-off-by: John Platts <john_platts@hotmail.com>
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-Id: <
168319294881.
1159309.
17060400720026083557.stgit@ltc-boston1.aus.stglabs.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Shivaprasad G Bhat [Thu, 4 May 2023 09:35:39 +0000 (05:35 -0400)]
tcg: ppc64: Fix mask generation for vextractdm
In function do_extractm() the mask is calculated as
dup_const(1 << (element_width - 1)). '1' being signed int
works fine for MO_8,16,32. For MO_64, on PPC64 host
this ends up becoming 0 on compilation. The vextractdm
uses MO_64, and it ends up having mask as 0.
Explicitly use 1ULL instead of signed int 1 like its
used everywhere else.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1536
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-Id: <
168319292809.
1159309.
5817546227121323288.stgit@ltc-boston1.aus.stglabs.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Harsh Prateek Bora [Wed, 3 May 2023 09:36:19 +0000 (15:06 +0530)]
MAINTAINERS: Adding myself in the list for ppc/spapr
Would like to get notified of changes in this area and review them.
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20230503093619.
2530487-3-harshpb@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Harsh Prateek Bora [Wed, 3 May 2023 09:36:18 +0000 (15:06 +0530)]
ppc: spapr: cleanup cr get/set with helpers.
The bits in cr reg are grouped into eight 4-bit fields represented
by env->crf[8] and the related calculations should be abstracted to
keep the calling routines simpler to read. This is a step towards
cleaning up the related/calling code for better readability.
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230503093619.
2530487-2-harshpb@linux.ibm.com>
[danielhb: add 'const' modifier to fix linux-user build]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
BALATON Zoltan [Wed, 5 Apr 2023 15:57:19 +0000 (17:57 +0200)]
hw/display/sm501: Remove unneeded increment from loop
As Coverity points out (CID
1508621) the calculation to increment i in
the fill fallback loop is ineffective as it is overwritten in next
statement. This was left there by mistake from a previous version but
is not needed in the current approach so remove the superfluous
increment statement.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <
20230405161234.
6EF0A74633D@zero.eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Dorinda Bassey [Mon, 17 Apr 2023 10:56:54 +0000 (12:56 +0200)]
audio/pwaudio.c: Add Pipewire audio backend for QEMU
This commit adds a new audiodev backend to allow QEMU to use Pipewire as
both an audio sink and source. This backend is available on most systems
Add Pipewire entry points for QEMU Pipewire audio backend
Add wrappers for QEMU Pipewire audio backend in qpw_pcm_ops()
qpw_write function returns the current state of the stream to pwaudio
and Writes some data to the server for playback streams using pipewire
spa_ringbuffer implementation.
qpw_read function returns the current state of the stream to pwaudio and
reads some data from the server for capture streams using pipewire
spa_ringbuffer implementation. These functions qpw_write and qpw_read
are called during playback and capture.
Added some functions that convert pw audio formats to QEMU audio format
and vice versa which would be needed in the pipewire audio sink and
source functions qpw_init_in() & qpw_init_out().
These methods that implement playback and recording will create streams
for playback and capture that will start processing and will result in
the on_process callbacks to be called.
Built a connection to the Pipewire sound system server in the
qpw_audio_init() method.
Signed-off-by: Dorinda Bassey <dbassey@redhat.com>
Reviewed-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <
20230417105654.32328-1-dbassey@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Richard Henderson [Fri, 5 May 2023 08:25:13 +0000 (09:25 +0100)]
Merge tag 'pull-riscv-to-apply-
20230505-1' of https://github.com/alistair23/qemu into staging
First RISC-V PR for 8.1
* CPURISCVState related cleanup and simplification
* Refactor Zicond and reuse in XVentanaCondOps
* Fix invalid riscv,event-to-mhpmcounters entry
* Support subsets of code size reduction extension
* Fix itrigger when icount is used
* Simplification for RVH related check and code style fix
* Add signature dump function for spike to run ACT tests
* Rework MISA writing
* Fix mstatus.MPP related support
* Use check for relationship between Zdinx/Zhinx{min} and Zfinx
* Fix the H extension TVM trap
* A large collection of mstatus sum changes and cleanups
* Zero init APLIC internal state
* Implement query-cpu-definitions
* Restore the predicate() NULL check behavior
* Fix Guest Physical Address Translation
* Make sure an exception is raised if a pte is malformed
* Add Ventana's Veyron V1 CPU
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# gpg: Signature made Fri 05 May 2023 01:53:35 AM BST
# gpg: using RSA key
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# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
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* tag 'pull-riscv-to-apply-
20230505-1' of https://github.com/alistair23/qemu: (89 commits)
target/riscv: add Ventana's Veyron V1 CPU
riscv: Make sure an exception is raised if a pte is malformed
target/riscv: Fix Guest Physical Address Translation
target/riscv: Restore the predicate() NULL check behavior
target/riscv: add TYPE_RISCV_DYNAMIC_CPU
target/riscv: add query-cpy-definitions support
target/riscv: add CPU QOM header
hw/intc/riscv_aplic: Zero init APLIC internal state
target/riscv: Reorg sum check in get_physical_address
target/riscv: Reorg access check in get_physical_address
target/riscv: Merge checks for reserved pte flags
target/riscv: Don't modify SUM with is_debug
target/riscv: Suppress pte update with is_debug
target/riscv: Move leaf pte processing out of level loop
target/riscv: Hoist pbmte and hade out of the level loop
target/riscv: Hoist second stage mode change to callers
target/riscv: Check SUM in the correct register
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
target/riscv: Move hstatus.spvp check to check_access_hlsv
target/riscv: Introduce mmuidx_2stage
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>