OSDN Git Service
Petr Hosek [Sat, 26 Aug 2017 01:32:20 +0000 (01:32 +0000)]
[llvm-objcopy] New layout algorithm that lays out segments first
The current file layout algorithm in llvm-objcopy is simple but
difficult to reason about. It also makes it very complicated to support
nested segments and to support segments that have offsets that come
before a point after the program headers. To support these cases and
simplify one of the most critical parts llvm-objcopy I rewrote the
layout algorithm. Laying out segments first solves most of the issues
encountered by the previous algorithm.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D36494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311825
91177308-0d34-0410-b5e6-
96231b3b80d8
Hiroshi Yamauchi [Sat, 26 Aug 2017 00:31:00 +0000 (00:31 +0000)]
Add options to dump block frequency/branch probability info in text.
Summary:
Add options -print-bfi/-print-bpi that dump block frequency and branch
probability info like -view-block-freq-propagation-dags and
-view-machine-block-freq-propagation-dags do but in text.
This is useful when the graph is very large and complex (the dot command
crashes, lines/edges too close to tell apart, hard to navigate without textual
search) or simply when text is preferred.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37165
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311822
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Aug 2017 23:34:59 +0000 (23:34 +0000)]
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector.
This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311821
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Aug 2017 23:34:57 +0000 (23:34 +0000)]
[AVX512] Add additional test cases for masked extract subvector.
This includes tests for extracting 128-bits from a 256-bit vector and zero masking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311820
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Aug 2017 23:34:55 +0000 (23:34 +0000)]
[X86] Add patterns to show more failures to use TBM instructions when we're trying to check flags.
We can probably add patterns to fix some of them. But the ones that use 'and' as their root node emit a X86ISD::CMP node in front of the 'and' and then pattern matching that to 'test' instruction. We can't use a tablegen pattern to fix that because we can't remap the cmp result to the flag output of a TBM instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311819
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 25 Aug 2017 22:50:52 +0000 (22:50 +0000)]
[x86] Teach the backend to fold more read-modify-write memory operands
to instructions.
These can't be reasonably matched in tablegen due to the handling of
flags, so we have to do this in C++ code. We only did it for `inc` and
`dec` historically, this starts fleshing that out to more interesting
instructions. Notably, this handles transfering operands to `add` and
`sub`.
Currently this forces them into a register. The next patch will add
support for keeping immediate operands as immediates. Then I'll extend
this beyond just `add` and `sub`.
I'm not super thrilled by the repeated switches in the code but
everything else I tried was really ugly or problematic.
Many thanks to Craig Topper for the suggestions about where to even
begin here and how to make this stuff work.
Differential Revision: https://reviews.llvm.org/D37130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311806
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Fri, 25 Aug 2017 22:08:15 +0000 (22:08 +0000)]
[Verifier] Diagnose invalid DIType references instead of crashing.
Fixes PR34325.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311805
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Fri, 25 Aug 2017 22:01:42 +0000 (22:01 +0000)]
[Inliner] Only compute fully inline cost when remarks are enabled.
Prior to this change (and after r311371), we computed it
unconditionally, causin gsevere compile time regressions (in some
cases, 5 to 10x).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311804
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Morehouse [Fri, 25 Aug 2017 22:01:21 +0000 (22:01 +0000)]
Revert "[SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzer"
This reverts r311801 due to a bot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311803
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Morehouse [Fri, 25 Aug 2017 21:18:29 +0000 (21:18 +0000)]
[SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzer
Summary:
- Don't sanitize __sancov_lowest_stack.
- Don't instrument leaf functions.
- Add CoverageStackDepth to Fuzzer and FuzzerNoLink.
Reviewers: vitalybuka, kcc
Reviewed By: kcc
Subscribers: cfe-commits, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D37156
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311801
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 25 Aug 2017 19:33:18 +0000 (19:33 +0000)]
[utils] add aarch64 target as an option
I don't know enough to add a custom scrubber for AArch64, so I just re-used ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311795
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Fri, 25 Aug 2017 19:29:47 +0000 (19:29 +0000)]
[sanitizer-coverage] extend fsanitize-coverage=pc-table with flags for every PC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311794
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 25 Aug 2017 19:25:03 +0000 (19:25 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311793
91177308-0d34-0410-b5e6-
96231b3b80d8
Haicheng Wu [Fri, 25 Aug 2017 19:00:33 +0000 (19:00 +0000)]
[InlineCost] Small changes to early exit condition. NFC.
Change the early exit condition from Cost > Threshold to Cost >= Threshold
because the inline condition is Cost < Threshold.
Differential Revision: https://reviews.llvm.org/D37087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311791
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Aug 2017 18:39:40 +0000 (18:39 +0000)]
[InstCombine] Don't fall back to only calling computeKnownBits if the upper bit of Add/Sub is demanded.
Just create an all 1s demanded mask and continue recursing like normal. The recursive calls should be able to handle an all 1s mask and do the right thing.
The only time we should care about knowing whether the upper bit was demanded is when we need to know if we should clear the NSW/NUW flags.
Now that we have a consistent path through the code for all cases, use KnownBits::computeForAddSub to compute the known bits at the end since we already have the LHS and RHS.
My larger goal here is to move the code that turns add into xor if only 1 bit is demanded and no bits below it are non-zero from InstCombiner::OptAndOp to here. This will allow it to be more general instead of just looking for 'add' and 'and' with constant RHS.
Differential Revision: https://reviews.llvm.org/D36486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311789
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Aug 2017 17:14:35 +0000 (17:14 +0000)]
[InstCombine] Add tests to show missed opportunities to combine bit tests hidden by a sign compare and a truncate. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311784
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Fri, 25 Aug 2017 16:52:29 +0000 (16:52 +0000)]
[LoopInterchange] Skip zext instructions when looking for induction var.
Summary:
SimplifyIndVar may introduce zext instructions to widen arguments of the
loop exit check. They should not prevent us from splitting the loop at
the induction variable, but maybe the check should be more conservative,
e.g. making sure it only extends arguments used by a comparison?
Reviewers: karthikthecool, mcrosier, mzolotukhin
Reviewed By: mcrosier
Subscribers: mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D34879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311783
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Fri, 25 Aug 2017 16:46:07 +0000 (16:46 +0000)]
Fix unused-lambda-capture warning by using default capture-by-ref
Since the lambda isn't escaped (via a std::function or similar) it's
fine/better to use default capture-by-ref to provide semantics similar
to language-level nested scopes (if/for/while/etc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311782
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Morehouse [Fri, 25 Aug 2017 16:19:26 +0000 (16:19 +0000)]
Fix buildbot breakage from r311763. Remove unused lambda capture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311781
91177308-0d34-0410-b5e6-
96231b3b80d8
David Green [Fri, 25 Aug 2017 16:14:56 +0000 (16:14 +0000)]
[gold] Fix up a new test to allow it to pass on non x86 builds.
Fix a test that is failing on a downstream ARM/AArch64
bootstrap. We just need add an elf_x86_64 parameter to
gold.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311780
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Kruse [Fri, 25 Aug 2017 12:38:53 +0000 (12:38 +0000)]
Normlize to LF line endings.
Commit r297442 introduced mixed CRLF/LF line endings to two files.
Normalize to to LF-only line endings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311774
91177308-0d34-0410-b5e6-
96231b3b80d8
Amjad Aboud [Fri, 25 Aug 2017 11:07:54 +0000 (11:07 +0000)]
[InstCombine] Consider more cases where SimplifyDemandedUseBits does not convert AShr to LShr.
There are cases where AShr have better chance to be optimized than LShr, especially when the demanded bits are not known to be Zero, and also known to be similar to the sign bit.
Differential Revision: https://reviews.llvm.org/D36936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311773
91177308-0d34-0410-b5e6-
96231b3b80d8
Ilya Biryukov [Fri, 25 Aug 2017 09:03:57 +0000 (09:03 +0000)]
Use temporary directory when building docker image.
Summary:
This avoids races on copying of compiled clang from 'build' image
to 'release' image.
Reviewers: klimek, mehdi_amini
Reviewed By: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37098
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311769
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Aug 2017 05:36:29 +0000 (05:36 +0000)]
[X86] Use SDValue::getOpcode instead of calling getNode and calling getOpcode on that. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311765
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Aug 2017 05:04:34 +0000 (05:04 +0000)]
[X86] Use isUInt and isShiftedUInt instead of using our own masking and compares. NFCI
While there use a local variable instead of calling C->getZExtValue() repeatedly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311764
91177308-0d34-0410-b5e6-
96231b3b80d8
Aditya Nandakumar [Fri, 25 Aug 2017 04:57:27 +0000 (04:57 +0000)]
[GISel]: Implement widenScalar for Legalizing G_PHI
https://reviews.llvm.org/D37018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311763
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 25 Aug 2017 02:32:51 +0000 (02:32 +0000)]
[x86] NFC - normalize test case formatting of IR and generate CHECK
lines with the script rather than using manually written checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311753
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 25 Aug 2017 02:32:48 +0000 (02:32 +0000)]
Teach the llc check updater to recognize the end-of-function comment
used on Windows and sometimes Darwin. Cleans up generated patterns for
me quite a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311752
91177308-0d34-0410-b5e6-
96231b3b80d8
Gor Nishanov [Fri, 25 Aug 2017 02:25:10 +0000 (02:25 +0000)]
[coroutines] Add support for symmetric control transfer (musttail on coro.resumes followed by a suspend)
Summary:
Add musttail to any resume instructions that is immediately followed by a
suspend (i.e. ret). We do this even in -O0 to support guaranteed tail call
for symmetrical coroutine control transfer (C++ Coroutines TS extension).
This transformation is done only in the resume part of the coroutine that has
identical signature and calling convention as the coro.resume call.
Reviewers: GorNishanov
Reviewed By: GorNishanov
Subscribers: EricWF, majnemer, llvm-commits
Differential Revision: https://reviews.llvm.org/D37125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311751
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 25 Aug 2017 02:06:36 +0000 (02:06 +0000)]
[x86] NFC: More refactoring to pave the way to extending this ISel logic
to handle other x86 pseudos that carry flags and thus can't be matched
by our ISel patterns with fused memory accesses.
Differential Revision: https://reviews.llvm.org/D37088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311749
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 25 Aug 2017 02:04:03 +0000 (02:04 +0000)]
[x86] NFC - Refactor the custom lowering of `(load; op; store)` RMW sequences.
This extracts the code out of a giant switch in preparation for expanding it to
handle operations other thin `inc` and `dec`. Add a FIXME indicating what's
coming here.
Differential Revision: https://reviews.llvm.org/D37045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311748
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Aug 2017 01:59:06 +0000 (01:59 +0000)]
[X86] Add TBM instructions to X86InstrInfo::isDefConvertible.
This allows us to remove "test" instructions and use the flags from the TBM instructions directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311747
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Fri, 25 Aug 2017 01:26:13 +0000 (01:26 +0000)]
DAG: Fix naming crime
Because isOperationCustom was only checking for custom
lowering on illegal types, this was behaving inconsistently
with the other isOperation* functions, so that
isOperationLegalOrCustom != (isOperationLegal || isOperationCustom)
Luckily this is only used in one place which already checks the
type legality on its own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311743
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Bogner [Fri, 25 Aug 2017 01:24:54 +0000 (01:24 +0000)]
[sanitizer-coverage] Make sure pc-tables aren't dead stripped
Add a reference to the PC array in llvm.used so that linkers that
aggressively dead strip (like ld64) don't remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311742
91177308-0d34-0410-b5e6-
96231b3b80d8
Mandeep Singh Grang [Fri, 25 Aug 2017 01:11:28 +0000 (01:11 +0000)]
[unittests] Remove reverse iteration tests which use pointer-like keys
Summary: The expected order of pointer-like keys is hash-function-dependent which in turn depends on the platform/environment. Need to come up with a better way to test reverse iteration of containers with pointer-like keys.
Reviewers: dblaikie, mehdi_amini, efriedma, mgrang
Reviewed By: mgrang
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311741
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 25 Aug 2017 00:56:05 +0000 (00:56 +0000)]
[x86] Back out one aspect of r311318: don't generically set
FeatureSlowUAMem32.
The idea was to mark things that are slow on widely available processors
as slow in the generic CPU so that the code generated for that CPU would
be fast across those processors. However, for this feature that doesn't
work out very well at all.
The problem here is that you can very easily enable AVX or AVX2 on top
of this generic CPU. For example, this can happen just by using AVX2
intrinsics from Clang within a region of code guarded by a dynamic CPU
feature test. When you do that, the generated code with SlowUAMem32 set
is ... amazingly slower. The problem is that there really aren't very
good alternatives to the unaligned loads, and so our vector codegen
regresses significantly.
The other issue is that there are plenty of AMD CPUs with AVX1 that
don't set FeatureSlowUAMem32 and so we shouldn't just check for AVX2
instead of this special feature. =/
It would be nice to have the target attriute logic be able to
enable/disable more than just one feature at a time and control this in
a more fine grained and useful way, but that doesn't seem easy. Given
that it is only Sandybridge and Ivybridge that set this feature, for now
I'm just backing it out of the generic CPU. That has the additional
advantage of going back to the previous state that people seemed vaguely
happy with.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311740
91177308-0d34-0410-b5e6-
96231b3b80d8
Stephen Hines [Fri, 25 Aug 2017 00:48:21 +0000 (00:48 +0000)]
Fix two (three) more issues with unchecked Error.
Summary:
If assertions are disabled, but LLVM_ABI_BREAKING_CHANGES is enabled,
this will cause an issue with an unchecked Success. Switching to
consumeError() is the correct way to bypass the check. This patch also
includes disabling 2 tests that can't work without assertions enabled,
since llvm_unreachable() with NDEBUG won't crash.
Reviewers: llvm-commits, lhames
Reviewed By: lhames
Subscribers: lhames, pirama
Differential Revision: https://reviews.llvm.org/D36729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311739
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 25 Aug 2017 00:34:07 +0000 (00:34 +0000)]
[x86] Fix an amazing goof in the handling of sub, or, and xor lowering.
The comment for this code indicated that it should work similar to our
handling of add lowering above: if we see uses of an instruction other
than flag usage and store usage, it tries to avoid the specialized
X86ISD::* nodes that are designed for flag+op modeling and emits an
explicit test.
Problem is, only the add case actually did this. In all the other cases,
the logic was incomplete and inverted. Any time the value was used by
a store, we bailed on the specialized X86ISD node. All of this appears
to have been historical where we had different logic here. =/
Turns out, we have quite a few patterns designed around these nodes. We
should actually form them. I fixed the code to match what we do for add,
and it has quite a positive effect just within some of our test cases.
The only thing close to a regression I see is using:
notl %r
testl %r, %r
instead of:
xorl -1, %r
But we can add a pattern or something to fold that back out. The
improvements seem more than worth this.
I've also worked with Craig to update the comments to no longer be
actively contradicted by the code. =[ Some of this still remains
a mystery to both Craig and myself, but this seems like a large step in
the direction of consistency and slightly more accurate comments.
Many thanks to Craig for help figuring out this nasty stuff.
Differential Revision: https://reviews.llvm.org/D37096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311737
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 24 Aug 2017 23:24:43 +0000 (23:24 +0000)]
[DAG] convert vector select-of-constants to logic/math
This goes back to a discussion about IR canonicalization. We'd like to preserve and convert
more IR to 'select' than we currently do because that's likely the best choice in IR:
http://lists.llvm.org/pipermail/llvm-dev/2016-September/105335.html
...but that's often not true for codegen, so we need to account for this pattern coming in
to the backend and transform it to better DAG ops.
Steps in this patch:
1. Add an EVT param to the existing convertSelectOfConstantsToMath() TLI hook to more finely
enable this transform. Other targets will probably want that anyway to distinguish scalars
from vectors. We're using that here to exclude AVX512 targets, but it may not be necessary.
2. Convert a vselect to ext+add. This eliminates a constant load/materialization, and the
vector ext is often free.
Implementing a more general fold using xor+and can be a follow-up for targets that don't have
a legal vselect. It's also possible that we can remove the TLI hook for the special case fold
implemented here because we're eliminating a constant, but it needs to be tested on other
targets.
Differential Revision: https://reviews.llvm.org/D36840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311731
91177308-0d34-0410-b5e6-
96231b3b80d8
Mandeep Singh Grang [Thu, 24 Aug 2017 23:02:48 +0000 (23:02 +0000)]
[ADT] Enable reverse iteration for DenseMap
Reviewers: mehdi_amini, dexonsmith, dblaikie, davide, chandlerc, davidxl, echristo, efriedma
Reviewed By: dblaikie
Subscribers: rsmith, mgorny, emaste, llvm-commits
Differential Revision: https://reviews.llvm.org/D35043
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311730
91177308-0d34-0410-b5e6-
96231b3b80d8
Xinliang David Li [Thu, 24 Aug 2017 22:54:01 +0000 (22:54 +0000)]
[Profile] backward propagate profile info in JumpThreading
Take-2 after fixing bugs in the original patch.
Differential Revsion: http://reviews.llvm.org/D36864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311727
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 24 Aug 2017 22:54:01 +0000 (22:54 +0000)]
[InstCombine] fix and enhance udiv/urem narrowing
There are 3 small independent changes here:
1. Account for multiple uses in the pattern matching: avoid the transform if it increases the instruction count.
2. Add a missing fold for the case where the numerator is the constant: http://rise4fun.com/Alive/E2p
3. Enable all folds for vector types.
There's still one more potential change - use "shouldChangeType()" to keep from transforming to an illegal integer type.
Differential Revision: https://reviews.llvm.org/D36988
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311726
91177308-0d34-0410-b5e6-
96231b3b80d8
Dehao Chen [Thu, 24 Aug 2017 21:37:04 +0000 (21:37 +0000)]
Move accurate-sample-profile into the function attribute.
Summary: We need to have accurate-sample-profile in function attribute so that it works with LTO.
Reviewers: davidxl, rsmith
Reviewed By: davidxl
Subscribers: sanjoy, mehdi_amini, javed.absar, llvm-commits, eraman
Differential Revision: https://reviews.llvm.org/D37113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311706
91177308-0d34-0410-b5e6-
96231b3b80d8
Eugene Zelenko [Thu, 24 Aug 2017 21:21:39 +0000 (21:21 +0000)]
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311703
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Thu, 24 Aug 2017 21:21:09 +0000 (21:21 +0000)]
[PartialInlining] Formatting. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311702
91177308-0d34-0410-b5e6-
96231b3b80d8
Nathan Hawes [Thu, 24 Aug 2017 21:20:41 +0000 (21:20 +0000)]
test commit: fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311701
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Thu, 24 Aug 2017 20:29:02 +0000 (20:29 +0000)]
[PartialInlining] Type. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311699
91177308-0d34-0410-b5e6-
96231b3b80d8
Konstantin Zhuravlyov [Thu, 24 Aug 2017 20:03:07 +0000 (20:03 +0000)]
AMDGPU: Fix gfx801 features
gfx801 has 1/2 rate F64, Fast F32 FMA
Differential Revision: https://reviews.llvm.org/D36981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311694
91177308-0d34-0410-b5e6-
96231b3b80d8
Jacob Gravelle [Thu, 24 Aug 2017 19:53:44 +0000 (19:53 +0000)]
[WebAssembly] FastISel : Bail to SelectionDAG for constexpr calls
Summary: Currently FastISel lowers constexpr calls as indirect calls.
We'd like those to direct calls, and falling back to SelectionDAGISel
handles that.
Reviewers: dschuff, sunfish
Subscribers: jfb, sbc100, llvm-commits, aheejin
Differential Revision: https://reviews.llvm.org/D37073
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311693
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Thu, 24 Aug 2017 19:43:09 +0000 (19:43 +0000)]
[WebAssembly] Update GCC test suite failure expectations
Summary:
Update GCC test suite failure expectations as we add -O0 to the bare tests in
WebAssembly waterfall. There are still several untriaged lld failures.
Reviewers: sbc100, jgravelle-google, dschuff
Reviewed By: dschuff
Subscribers: jfb
Differential Revision: https://reviews.llvm.org/D37100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311691
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Thu, 24 Aug 2017 19:19:24 +0000 (19:19 +0000)]
[Hexagon] Set access size for vector pseudo loads/stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311690
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Thu, 24 Aug 2017 18:54:16 +0000 (18:54 +0000)]
[globalisel][tablegen] Predicates should start from GIPFP_Invalid+1 not GIPFP_Invalid
This fixes a warning when there are zero defined predicates and also fixes an
unnoticed bug where the first predicate in the table was unusable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311684
91177308-0d34-0410-b5e6-
96231b3b80d8
Victor Leschuk [Thu, 24 Aug 2017 17:02:38 +0000 (17:02 +0000)]
Remove duplicate code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311675
91177308-0d34-0410-b5e6-
96231b3b80d8
Victor Leschuk [Thu, 24 Aug 2017 16:57:10 +0000 (16:57 +0000)]
Add missing break in switch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311673
91177308-0d34-0410-b5e6-
96231b3b80d8
Pete Couperus [Thu, 24 Aug 2017 15:40:33 +0000 (15:40 +0000)]
[ARC] Add ARC backend.
Add the ARC backend as an experimental target to lib/Target.
Reviewed at: https://reviews.llvm.org/D36331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311667
91177308-0d34-0410-b5e6-
96231b3b80d8
Krasimir Georgiev [Thu, 24 Aug 2017 15:03:18 +0000 (15:03 +0000)]
[X86AsmParser] Refactor AsmRewrite constructors, NFCI
Summary:
This is a follow-up of https://reviews.llvm.org/D37105, where a slight refactoring
of the constructors of AsmRewrite is proposed.
Reviewers: coby
Reviewed By: coby
Differential Revision: https://reviews.llvm.org/D37110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311666
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 24 Aug 2017 15:00:13 +0000 (15:00 +0000)]
fix typo; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311665
91177308-0d34-0410-b5e6-
96231b3b80d8
Sjoerd Meijer [Thu, 24 Aug 2017 14:47:06 +0000 (14:47 +0000)]
[AArch64] Add FMOVH0: materialize 0 using zero register for f16 values
Instead of loading 0 from a constant pool, it's of course much better to
materialize it using an fmov and the zero register.
Thanks to Ahmed Bougacha for the suggestion.
Differential Revision: https://reviews.llvm.org/D37102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311662
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 24 Aug 2017 14:43:33 +0000 (14:43 +0000)]
[BypassSlowDivision] move map helper code to header; NFC
We can reuse this code with other div/rem transforms as shown in:
https://reviews.llvm.org/D31037
https://bugs.llvm.org/show_bug.cgi?id=31028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311661
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Thu, 24 Aug 2017 14:30:44 +0000 (14:30 +0000)]
[TargetParser][AArch64] Add support for RDM feature in the target parser.
Differential Revision: https://reviews.llvm.org/D37081
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311659
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zuckerman [Thu, 24 Aug 2017 14:11:28 +0000 (14:11 +0000)]
Adding base lit test for x86interleaved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311658
91177308-0d34-0410-b5e6-
96231b3b80d8
Coby Tayree [Thu, 24 Aug 2017 14:10:50 +0000 (14:10 +0000)]
[fixup][rL311639]
rL311639 created X86AsmParser a dependency in X86AsmPrinter, which broke builds
this fix adds the necessary dep
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311657
91177308-0d34-0410-b5e6-
96231b3b80d8
Krasimir Georgiev [Thu, 24 Aug 2017 13:38:18 +0000 (13:38 +0000)]
[X86AsmParser] Fix msan: use-of-uninitialized-value after r311639
Summary:
CodeGen/ms-inline-asm.c test triggers msan use-of-uninitialized-value here:
llvm/lib/MC/MCParser/AsmParser.cpp:5629:7
Reviewers: bkramer, coby
Differential Revision: https://reviews.llvm.org/D37105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311653
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Thu, 24 Aug 2017 11:59:53 +0000 (11:59 +0000)]
[Hexagon] Generate correct runtime check when recognizing memmove
The check (assuming positive stride) for validity of memmove should be
(a) the destination is at a lower address than the source, or
(b) the distance between the source and destination is greater than or
equal the number of bytes copied.
For the second part it is sufficient to assume that the destination
is at a higher address, since the opposite case is covered by (a).
The distance calculation was previously done by subtracting the
pointers in the wrong order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311650
91177308-0d34-0410-b5e6-
96231b3b80d8
Evgeny Astigeevich [Thu, 24 Aug 2017 10:00:25 +0000 (10:00 +0000)]
[ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting illegal modes
ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes
for the Thumb1 target. This causes generation of redundant code and affects
performance.
This fixes PR34106: https://bugs.llvm.org/show_bug.cgi?id=34106
Differential Revision: https://reviews.llvm.org/D36467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311649
91177308-0d34-0410-b5e6-
96231b3b80d8
Tobias Grosser [Thu, 24 Aug 2017 09:46:25 +0000 (09:46 +0000)]
Model cache size and associativity in TargetTransformInfo
Summary:
We add the precise cache sizes and associativity for the following Intel
architectures:
- Penry
- Nehalem
- Westmere
- Sandy Bridge
- Ivy Bridge
- Haswell
- Broadwell
- Skylake
- Kabylake
Polly uses since several months a performance model for BLAS computations that
derives optimal cache and register tile sizes from cache and latency
information (based on ideas from "Analytical Modeling Is Enough for High-Performance BLIS", by Tze Meng Low published at TOMS 2016).
While bootstrapping this model, these target values have been kept in Polly.
However, as our implementation is now rather mature, it seems time to teach
LLVM itself about cache sizes.
Interestingly, L1 and L2 cache sizes are pretty constant across
micro-architectures, hence a set of architecture specific default values
seems like a good start. They can be expanded to more target specific values,
in case certain newer architectures require different values. For now a set
of Intel architectures are provided.
Just as a little teaser, for a simple gemm kernel this model allows us to
improve performance from 1.2s to 0.27s. For gemm kernels with less optimal
memory layouts even larger speedups can be reported.
Reviewers: Meinersbur, bollu, singam-sanjay, hfinkel, gareevroman, fhahn, sebpop, efriedma, asb
Reviewed By: fhahn, asb
Subscribers: lsaba, asb, pollydev, llvm-commits
Differential Revision: https://reviews.llvm.org/D37051
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311647
91177308-0d34-0410-b5e6-
96231b3b80d8
Sjoerd Meijer [Thu, 24 Aug 2017 09:21:10 +0000 (09:21 +0000)]
[AArch64] Custom lowering of copysign f16
This is a follow up patch of r311154 and introduces custom lowering of copysign
f16 to avoid promotions to single precision types when the subtarget supports
fullfp16.
Differential Revision: https://reviews.llvm.org/D36893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311646
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Thu, 24 Aug 2017 09:11:20 +0000 (09:11 +0000)]
Re-commit: [globalisel][tablegen] Add support for ImmLeaf without SDNodeXForm
Summary:
This patch adds support for predicates on imm nodes but only for ImmLeaf and not
for PatLeaf or PatFrag and only where the value does not need to be transformed
before being rendered into the instruction.
The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the
necessary target-supplied C++ for GlobalISel.
Depends on D36085
The previous commit was reverted for breaking the build but this appears to have
been the recurring problem on the Windows bots with tablegen not being re-run
when llvm-tblgen is changed but the .td's aren't. If it re-occurs then forcing a
build with clean=True should fix it but this string should do this in advance:
Requires a clean build.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: rovka
Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D36086
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311645
91177308-0d34-0410-b5e6-
96231b3b80d8
Coby Tayree [Thu, 24 Aug 2017 09:08:33 +0000 (09:08 +0000)]
[LLVM][x86][Inline Asm] support for GCC style inline asm - Y<x> constraints
This patch is intended to enable the use of basic double letter constraints used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}.
Supersedes D35204
Clang counterpart: D36371
Differential Revision: https://reviews.llvm.org/D36369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311644
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikael Holmen [Thu, 24 Aug 2017 09:05:00 +0000 (09:05 +0000)]
[Reassociate] Do not drop debug location if replacement is missing
Summary:
When reassociating an expression, do not drop the instruction's
original debug location in case the replacement location is
missing.
The debug location must at least not be dropped for inlinable
callsites of debug-info-bearing functions in debug-info-bearing
functions. Failing to do so would result in an "inlinable function "
"call in a function with debug info must have a !dbg location"
error in the verifier.
As preserving the original debug location is not expected
to result in overly jumpy debug line information, it is
preserved for all other cases too.
This fixes PR34231:
https://bugs.llvm.org/show_bug.cgi?id=34231
Original patch by David Stenberg
Reviewers: davide, craig.topper, mcrosier, dblaikie, aprantl
Reviewed By: davide, aprantl
Subscribers: aprantl
Differential Revision: https://reviews.llvm.org/D36865
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311642
91177308-0d34-0410-b5e6-
96231b3b80d8
Coby Tayree [Thu, 24 Aug 2017 08:46:25 +0000 (08:46 +0000)]
[X86AsmParser] Refactoring, (almost) NFC.
Some refactoring to X86AsmParser, mostly regarding the way rewrites are conducted.
Mainly, we try to concentrate all the rewrite effort under one hood, so it'll hopefully be less of a mess and easier to maintain and understand.
naturally, some frontend tests were affected: D36794
Differential Revision: https://reviews.llvm.org/D36793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311639
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Thu, 24 Aug 2017 07:55:15 +0000 (07:55 +0000)]
IPRA: Don't assume called function is first call operand
Fixes not finding the called global for AMDGPU
call pseudoinstructions, which prevented IPRA
from doing much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311637
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Thu, 24 Aug 2017 07:55:13 +0000 (07:55 +0000)]
IPRA: Exit early on functions without calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311636
91177308-0d34-0410-b5e6-
96231b3b80d8
Sjoerd Meijer [Thu, 24 Aug 2017 07:43:52 +0000 (07:43 +0000)]
[AArch64] fix for fcos and frem f16 promotion
Fix for copy-paste mistake in r311154; setOperationAction for fcos and frem f16
operands appeared twice (and it should be set to 'promote').
Differential Revision: https://reviews.llvm.org/D37071
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311635
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Thu, 24 Aug 2017 07:38:36 +0000 (07:38 +0000)]
[x86] NFC: Clean up two tests and generate precise checks for them.
Mostly this involved giving unnamed values names and running the IR
through `opt` to re-format it but merging in any important comments in
the original. I then deleted pointless comments and inlined the function
attributes for ease of reading and editting.
All of this is to make it much easier to see the instructions being
generated here and evaluate any updates to the tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311634
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Breger [Thu, 24 Aug 2017 07:06:27 +0000 (07:06 +0000)]
[GlobalISel][X86] Support G_IMPLICIT_DEF.
Summary: Support G_IMPLICIT_DEF.
Reviewers: zvi, guyblank, t.p.northover
Reviewed By: guyblank
Subscribers: rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D36733
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311633
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 24 Aug 2017 05:38:39 +0000 (05:38 +0000)]
[docs] In the CMake primer, correct the description of the ARGV/ARGN variables.
ARGN is the sublist of unnamed arguments, not the count of the arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311632
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 24 Aug 2017 05:35:27 +0000 (05:35 +0000)]
[Support] Rewrite handleAllErrors in terms of cantFail.
This just switches handleAllErrors from using custom assertions that all errors
have been handled to using cantFail. This change involves moving some of the
class and function definitions around though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311631
91177308-0d34-0410-b5e6-
96231b3b80d8
Wei Ding [Thu, 24 Aug 2017 04:18:24 +0000 (04:18 +0000)]
Add ‘llvm.experimental.constrained.fma‘ Intrinsic.
Differential Revision: http://reviews.llvm.org/D36335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311629
91177308-0d34-0410-b5e6-
96231b3b80d8
Adam Nemet [Thu, 24 Aug 2017 04:04:49 +0000 (04:04 +0000)]
Support all integer types in DiagnosticInfoOptimizationBase::Argument
We were missing size_t (unsigned long) on macOS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311628
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Thu, 24 Aug 2017 02:43:17 +0000 (02:43 +0000)]
NewGVN: We weren't properly simplifying selects with equal arguments due to a thinko.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311626
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Beckmann [Thu, 24 Aug 2017 02:36:50 +0000 (02:36 +0000)]
Fix bug 34051 by handling empty .res files gracefully.
Summary:
Previously, llvm-cvtres crashes on .res files which are empty except for
the null header. This allows the library to simply pass over them.
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D37044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311625
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Thu, 24 Aug 2017 01:08:27 +0000 (01:08 +0000)]
[DAG] Fix Node Replacement in PromoteIntBinOp
When one operand is a user of another in a promoted binary operation
we may replace and delete the returned value before returning
triggering an assertion. Reorder node replacements to prevent this.
Fixes PR34137.
Landing on behalf of Nirav.
Differential Revision: https://reviews.llvm.org/D36581
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311623
91177308-0d34-0410-b5e6-
96231b3b80d8
Dylan McKay [Thu, 24 Aug 2017 00:14:38 +0000 (00:14 +0000)]
[AVR] Use the correct register classes for 16-bit atomic operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311620
91177308-0d34-0410-b5e6-
96231b3b80d8
Dehao Chen [Wed, 23 Aug 2017 23:19:11 +0000 (23:19 +0000)]
Add test to cover accurate-sample-profile.
Summary: This patch adds test to cover the logic guarded by "accurate-sample-profile" flag.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: sanjoy, llvm-commits, eraman
Differential Revision: https://reviews.llvm.org/D37084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311618
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Wed, 23 Aug 2017 22:07:10 +0000 (22:07 +0000)]
ARM: use internal relocations for local symbols after all.
Switching to external relocations for ARM-mode branches (to allow Thumb
interworking when the offset is unencodable) causes calls to temporary symbols
to be miscompiled and instead go to the parent externally visible symbol.
Calling a temporary never happens in compiled code, but can occasionally in
hand-written assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311611
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Wed, 23 Aug 2017 22:02:36 +0000 (22:02 +0000)]
Retire the llvm.dbg.mir hack after r311594.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311610
91177308-0d34-0410-b5e6-
96231b3b80d8
Aditya Nandakumar [Wed, 23 Aug 2017 21:55:36 +0000 (21:55 +0000)]
Fix Verifier test - add REQUIRES aarch64-registered-target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311609
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Wed, 23 Aug 2017 21:52:24 +0000 (21:52 +0000)]
Add a Verifier check for DILocation's scopes.
Found via https://bugs.llvm.org/show_bug.cgi?id=33997.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311608
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Wed, 23 Aug 2017 21:36:04 +0000 (21:36 +0000)]
[WebAssembly] Fix overflow for input with missing version
Differential revision: https://reviews.llvm.org/D37070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311605
91177308-0d34-0410-b5e6-
96231b3b80d8
Rong Xu [Wed, 23 Aug 2017 21:36:02 +0000 (21:36 +0000)]
[PGO] Set edge weights for indirectbr instruction with profile counts
Current PGO only annotates the edge weight for branch and switch instructions
with profile counts. We should also annotate the indirectbr instruction as
all the information is there. This patch enables the annotating for indirectbr
instructions. Also uses this annotation in branch probability analysis.
Differential Revision: https://reviews.llvm.org/D37074
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311604
91177308-0d34-0410-b5e6-
96231b3b80d8
Geoff Berry [Wed, 23 Aug 2017 21:11:28 +0000 (21:11 +0000)]
[AArch64][Falkor] Fix bug in Falkor HWPF tag collision avoidance
LDPDi was incorrectly marked as ignoring the destination register in the
prefetcher tag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311599
91177308-0d34-0410-b5e6-
96231b3b80d8
Pete Couperus [Wed, 23 Aug 2017 20:58:22 +0000 (20:58 +0000)]
Test commit.
Fix instrinsic -> intrinsic typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311598
91177308-0d34-0410-b5e6-
96231b3b80d8
Aditya Nandakumar [Wed, 23 Aug 2017 20:45:48 +0000 (20:45 +0000)]
[GISEl]: Translate phi into G_PHI
G_PHI has the same semantics as PHI but also has types.
This lets us verify that the types in the G_PHI are consistent.
This also allows specifying legalization actions for G_PHIs.
https://reviews.llvm.org/D36990
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311596
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Wed, 23 Aug 2017 20:39:35 +0000 (20:39 +0000)]
Attempt to fix the BUILD_SHARED_LIBS build after the DIExpression change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311595
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Wed, 23 Aug 2017 20:31:27 +0000 (20:31 +0000)]
Parse and print DIExpressions inline to ease IR and MIR testing
Summary:
Most DIExpressions are empty or very simple. When they are complex, they
tend to be unique, so checking them inline is reasonable.
This also avoids the need for CodeGen passes to append to the
llvm.dbg.mir named md node.
See also PR22780, for making DIExpression not be an MDNode.
Reviewers: aprantl, dexonsmith, dblaikie
Subscribers: qcolombet, javed.absar, eraman, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D37075
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311594
91177308-0d34-0410-b5e6-
96231b3b80d8
Lei Huang [Wed, 23 Aug 2017 19:25:04 +0000 (19:25 +0000)]
Update branch coalescing to be a PowerPC specific pass
Implementing this pass as a PowerPC specific pass. Branch coalescing utilizes
the analyzeBranch method which currently does not include any implicit operands.
This is not an issue on PPC but must be handled on other targets.
Differential Revision : https: // reviews.llvm.org/D32776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311588
91177308-0d34-0410-b5e6-
96231b3b80d8
Greg Clayton [Wed, 23 Aug 2017 18:00:07 +0000 (18:00 +0000)]
Updated my email address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311581
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Wed, 23 Aug 2017 17:50:46 +0000 (17:50 +0000)]
[X86] Fix -Wenum-compare warning
lib/Target/X86/X86ISelLowering.cpp:34613:25: error: enumeral mismatch in
conditional expression: 'llvm::ISD::NodeType' vs
'llvm::X86ISD::NodeType'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311580
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 23 Aug 2017 16:41:02 +0000 (16:41 +0000)]
[AVX512] Don't create SHRUNKBLEND SDNodes for 512-bit vectors
There are no 512-bit blend instructions so we shouldn't create SHRUNKBLEND for them.
On a side note, it looks like there may be a missed opportunity for constant folding TESTM when LHS and RHS are equal.
This fixes PR34139.
Differential Revision: https://reviews.llvm.org/D36992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311572
91177308-0d34-0410-b5e6-
96231b3b80d8