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Simon Pilgrim [Thu, 7 Jun 2018 13:01:42 +0000 (13:01 +0000)]
[X86][SSE] Simplify combineVectorTruncationWithPACKSS to reduce code duplication
Simplify combineVectorTruncationWithPACKSS to just a SIGN_EXTEND_INREG followed by using the existing truncateVectorWithPACK instead of duplicating code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334193
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Hiroshi Inoue [Thu, 7 Jun 2018 12:49:12 +0000 (12:49 +0000)]
[PowerPC] fix trivial typos in comment, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334191
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Matt Arsenault [Thu, 7 Jun 2018 12:16:31 +0000 (12:16 +0000)]
AMDGPU: Fix not including v2f64 in SReg_128
Fixes assertion with calls returning v2f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334189
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Simon Pilgrim [Thu, 7 Jun 2018 11:22:52 +0000 (11:22 +0000)]
[X86][SSE] Add extra trunc(shl) test cases
The existing trunc_shl_17_v8i16_v8i32 test case should (but doesn't) fold to zero, I've added 2 new test cases:
- trunc_shl_16_v8i16_v8i32 which folds to zero (this is actually testing the target faux shuffle combine)
- trunc_shl_15_v8i16_v8i32 which should perform the full shl + truncate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334188
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Florian Hahn [Thu, 7 Jun 2018 11:09:05 +0000 (11:09 +0000)]
[Mem2Reg] Avoid replacing load with itself in promoteSingleBlockAlloca.
We do the same thing in rewriteSingleStoreAlloca.
Fixes PR37632.
Reviewers: chandlerc, davide, efriedma
Reviewed By: davide
Differential Revision: https://reviews.llvm.org/D47825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334187
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Matt Arsenault [Thu, 7 Jun 2018 10:15:20 +0000 (10:15 +0000)]
AMDGPU: Use scalar operations for f16 fabs/fneg patterns
Fixes unnecessary differences between subtargets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334184
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Simon Pilgrim [Thu, 7 Jun 2018 10:13:09 +0000 (10:13 +0000)]
[X86] Regenerate rotate tests
Add 32-bit tests to show missed SHLD/SHRD cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334183
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Paul Semel [Thu, 7 Jun 2018 10:05:25 +0000 (10:05 +0000)]
[llvm-strip] Expose --strip-unneeded option
Differential Revision: https://reviews.llvm.org/D47818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334182
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Matt Arsenault [Thu, 7 Jun 2018 09:54:49 +0000 (09:54 +0000)]
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334180
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Clement Courbet [Thu, 7 Jun 2018 09:26:33 +0000 (09:26 +0000)]
[X86][NFC] Fix harmless typo in BtVer2 model.
See D46356 for context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334178
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Tomasz Krupa [Thu, 7 Jun 2018 08:48:45 +0000 (08:48 +0000)]
[X86] Block UndefRegUpdate
Summary: Prevent folding of operations with memory loads when one of the sources has undefined register update.
Reviewers: craig.topper
Subscribers: llvm-commits, mike.dvoretsky, ashlykov
Differential Revision: https://reviews.llvm.org/D47621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334175
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Max Kazantsev [Thu, 7 Jun 2018 08:47:19 +0000 (08:47 +0000)]
[NFC] Use variable instead of accessing pair many times
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334173
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Tomasz Krupa [Thu, 7 Jun 2018 08:20:28 +0000 (08:20 +0000)]
Test commit access.
Added a bunch of periods after comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334171
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Guillaume Chatelet [Thu, 7 Jun 2018 08:11:54 +0000 (08:11 +0000)]
[llvm-exegesis] Add a Configuration object for Benchmark.
Summary: This is the first step to have the BenchmarkRunner create and measure many different configurations (different initial values for instance).
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334169
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Guillaume Chatelet [Thu, 7 Jun 2018 07:51:16 +0000 (07:51 +0000)]
[llvm-exegesis] Improve error reporting.
Summary: BenchmarkResult IO functions now return an Error or Expected so caller can deal take proper action.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47868
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334167
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Guillaume Chatelet [Thu, 7 Jun 2018 07:40:40 +0000 (07:40 +0000)]
[llvm-exegesis] Serializes instruction's operand in BenchmarkResult's key.
Summary: Follow up patch to https://reviews.llvm.org/D47764.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47785
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334165
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Clement Courbet [Thu, 7 Jun 2018 07:37:49 +0000 (07:37 +0000)]
[X86][NFC] Fix harmless typos in BDW/ZnVer1 sched models.
See D46356 for context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334164
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Karl-Johan Karlsson [Thu, 7 Jun 2018 07:20:33 +0000 (07:20 +0000)]
[BranchFolding] Fix live-in's when hoisting code
Summary:
When the branch folder hoist code into a predecessor it adjust live-in's
in the blocks it hoist code from. However it fail to handle hoisted code
that contain a defed register that originally is live-in in the block
through a super register.
This is fixed by replacing the live-in handling code with calls to
utility functions in LivePhysRegs.
Reviewers: kparzysz, gberry, MatzeB, uweigand, aprantl
Reviewed By: kparzysz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334163
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Jonas Paulsson [Thu, 7 Jun 2018 05:59:07 +0000 (05:59 +0000)]
[SystemZ] Build Load And Test from scratch in convertToLoadAndTest.
This is needed to get CC operand in right place, as expected by the
SchedModel.
Review: Ulrich Weigand
https://reviews.llvm.org/D47820
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334161
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Michael Zolotukhin [Thu, 7 Jun 2018 00:19:29 +0000 (00:19 +0000)]
SpeculativeExecution Pass: Set PreserveCFG to avoid unnecessary analyses invalidation.
The pass doesn't touch CFG in any way, only moves instructions between
blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334150
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Peter Collingbourne [Thu, 7 Jun 2018 00:06:41 +0000 (00:06 +0000)]
Add definition for ELF dynamic tag DT_SYMTAB_SHNDX.
DT_SYMTAB_SHNDX is defined in generic-abi:
http://www.sco.com/developers/gabi/latest/ch5.dynamic.html
Patch by Rahul Chaudhry!
Differential Revision: https://reviews.llvm.org/D47803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334149
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Peter Collingbourne [Thu, 7 Jun 2018 00:02:07 +0000 (00:02 +0000)]
llvm-readobj: fix printing number of relocations in Android packed format.
With '-elf-output-style=GNU -relocations', a header containing the number
of entries is printed before all the relocation entries in the section.
For Android packed format, we need to perform the unpacking first before
we can get the actual number of relocations in the section.
Patch by Rahul Chaudhry!
Differential Revision: https://reviews.llvm.org/D47800
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334147
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Stanislav Mekhanoshin [Wed, 6 Jun 2018 22:22:32 +0000 (22:22 +0000)]
[AMDGPU] Improve reciprocal handling
When denormals are supported we are producing a full division for
1.0f / x. That still can be replaced by the faster version:
bool c = fabs(x) > 0x1.0p+96f;
float s = c ? 0x1.0p-32f : 1.0f;
x *= s;
return s * v_rcp_f32(x)
in case if requested accuracy is 2.5ulp or less. The same version
is used if denormals are not supported for non 1.0 numerators, where
just v_rcp_f32 is then used for 1.0 numerator.
The optimization of 1/x is extended to the case -1/x, which is the
same except for the resulting sign bit.
OpenCL conformance passed with both enabled and disabled denorms.
Differential Revision: https://reviews.llvm.org/D47805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334142
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Teresa Johnson [Wed, 6 Jun 2018 22:22:01 +0000 (22:22 +0000)]
[ThinLTO] Rename index IsAnalysis flag to HaveGVs (NFC)
With the upcoming patch to add summary parsing support, IsAnalysis would
be true in contexts where we are not performing module summary analysis.
Rename to the more specific and approprate HaveGVs, which is essentially
what this flag is indicating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334140
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Sanjay Patel [Wed, 6 Jun 2018 21:58:12 +0000 (21:58 +0000)]
[InstCombine] fold another shifty abs pattern to cmp+sel (PR36036)
The bug report:
https://bugs.llvm.org/show_bug.cgi?id=36036
...requests a DAG change for this, but an IR canonicalization
probably handles most cases. If we still want to match this
pattern in the backend, there's a proposal for that too:
D47831
Alive proofs including nsw/nuw cases that were first noted in:
D46988
https://rise4fun.com/Alive/Kmp
This patch is largely copied from the existing code that was
initially added with:
D40984
...but I didn't see much gain from trying to share code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334137
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Petr Hosek [Wed, 6 Jun 2018 21:43:37 +0000 (21:43 +0000)]
[CMake] Pass additional CMake tools to external projects
This is needed when the external projects try to use other tools
besides just the compiler and the linker.
Differential Revision: https://reviews.llvm.org/D47833
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334136
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Sanjay Patel [Wed, 6 Jun 2018 21:32:42 +0000 (21:32 +0000)]
[InstCombine] add tests for another abs() pattern (PR36036); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334133
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Matt Arsenault [Wed, 6 Jun 2018 21:28:11 +0000 (21:28 +0000)]
AMDGPU: Custom lower v2f16 fneg/fabs with illegal f16
Fixes terrible code on targets without f16 support. The
legalization creates a mess that is difficult to recover
from. Also should avoid randomly breaking these tests
multiple times in sequence in future commits.
Some regressions in cases where it happens to be better
to pull the source modifier after the conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334132
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Alexander Shaposhnikov [Wed, 6 Jun 2018 21:23:19 +0000 (21:23 +0000)]
[llvm-strip] Expose --discard-all option
Expose objcopy's --discard-all option in llvm-strip.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D47750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334131
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Roman Lebedev [Wed, 6 Jun 2018 19:38:27 +0000 (19:38 +0000)]
[InstCombine] PR37603: low bit mask canonicalization
Summary:
This is [[ https://bugs.llvm.org/show_bug.cgi?id=37603 | PR37603 ]].
https://godbolt.org/g/VCMNpS
https://rise4fun.com/Alive/idM
When doing bit manipulations, it is quite common to calculate some bit mask,
and apply it to some value via `and`.
The typical C code looks like:
```
int mask_signed_add(int nbits) {
return (1 << nbits) - 1;
}
```
which is translated into (with `-O3`)
```
define dso_local i32 @mask_signed_add(int)(i32) local_unnamed_addr #0 {
%2 = shl i32 1, %0
%3 = add nsw i32 %2, -1
ret i32 %3
}
```
But there is a second, less readable variant:
```
int mask_signed_xor(int nbits) {
return ~(-(1 << nbits));
}
```
which is translated into (with `-O3`)
```
define dso_local i32 @mask_signed_xor(int)(i32) local_unnamed_addr #0 {
%2 = shl i32 -1, %0
%3 = xor i32 %2, -1
ret i32 %3
}
```
Since we created such a mask, it is quite likely that we will use it in `and` next.
And then we may get rid of `not` op by folding into `andn`.
But now that i have actually looked:
https://godbolt.org/g/VTUDmU
_some_ backend changes will be needed too.
We clearly loose `bzhi` recognition.
Reviewers: spatel, craig.topper, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334127
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Roman Lebedev [Wed, 6 Jun 2018 19:38:21 +0000 (19:38 +0000)]
[InstCombine][NFC] PR37603: low bit mask canonicalization tests
Differential Revision: https://reviews.llvm.org/D47427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334126
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Roman Lebedev [Wed, 6 Jun 2018 19:38:16 +0000 (19:38 +0000)]
[X86] Emit BZHI when mask is ~(-1 << nbits))
Summary:
In D47428, i propose to choose the `~(-(1 << nbits))` as the canonical form of low-bit-mask formation.
As it is seen from these tests, there is a reason for that.
AArch64 currently better handles `~(-(1 << nbits))`, but not the more traditional `(1 << nbits) - 1` (sic!).
The other way around for X86.
It would be much better to canonicalize.
This patch is completely monkey-typing.
I don't really understand how this works :)
I have based it on `// x & (-1 >> (32 - y))` pattern.
Also, when we only have `BMI`, i wonder if we could use `BEXTR` with `start=0` ?
Related links:
https://bugs.llvm.org/show_bug.cgi?id=36419
https://bugs.llvm.org/show_bug.cgi?id=37603
https://bugs.llvm.org/show_bug.cgi?id=37610
https://rise4fun.com/Alive/idM
Reviewers: craig.topper, spatel, RKSimon, javed.absar
Reviewed By: craig.topper
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D47453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334125
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Roman Lebedev [Wed, 6 Jun 2018 19:38:10 +0000 (19:38 +0000)]
[NFC][X86][AArch64] Reorganize/cleanup BZHI test patterns
Summary:
In D47428, i propose to choose the `~(-(1 << nbits))` as the canonical form of low-bit-mask formation.
As it is seen from these tests, there is a reason for that.
AArch64 currently better handles `~(-(1 << nbits))`, but not the more traditional `(1 << nbits) - 1` (sic!).
The other way around for X86.
It would be much better to canonicalize.
It would seem that there is too much tests, but this is most of all the auto-generated possible variants
of C code that one would expect for BZHI to be formed, and then manually cleaned up a bit.
So this should be pretty representable, which somewhat good coverage...
Related links:
https://bugs.llvm.org/show_bug.cgi?id=36419
https://bugs.llvm.org/show_bug.cgi?id=37603
https://bugs.llvm.org/show_bug.cgi?id=37610
https://rise4fun.com/Alive/idM
Reviewers: javed.absar, craig.topper, RKSimon, spatel
Reviewed By: RKSimon
Subscribers: kristof.beyls, llvm-commits, RKSimon, craig.topper, spatel
Differential Revision: https://reviews.llvm.org/D47452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334124
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Krzysztof Parzyszek [Wed, 6 Jun 2018 19:34:40 +0000 (19:34 +0000)]
[Hexagon] Implement vector-pair zero as V6_vsubw_dv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334123
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Craig Topper [Wed, 6 Jun 2018 19:15:15 +0000 (19:15 +0000)]
[X86] Properly disassemble gather/scatter instructions where xmm4/ymm4/zmm4 are used as the index.
These encodings correspond to the cases in the normal encoding scheme where there is no index and our modrm reading code initially decodes it as such. The VSIB handling code tried to compensate for this, but failed to add the base needed to make later code do the right thing.
Fixes PR37712.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334121
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Craig Topper [Wed, 6 Jun 2018 19:15:12 +0000 (19:15 +0000)]
[X86] Rename vy512mem->vy512xmem and vz256xmem->vz256mem.
The index size is represented by the letter after the 'v'. The number represents the memory size. If an 'x' appears after the number its means the index register can be from VR128X/VR256X instead of VR128/VR256.
As vy512mem uses a VR256X index it should have an x.
And vz256mem uses a VR512 index so it shouldn't have an x.
I admit these names kind of suck and are confusing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334120
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Simon Pilgrim [Wed, 6 Jun 2018 19:06:09 +0000 (19:06 +0000)]
[X86][BtVer2] Add support for all vector instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), all these instructions are dependency breaking and zero the destination register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334119
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Vedant Kumar [Wed, 6 Jun 2018 19:05:42 +0000 (19:05 +0000)]
[Debugify] Move debug value intrinsics closer to their operand defs
Before this patch, debugify would insert debug value intrinsics before the
terminating instruction in a block. This had the advantage of being simple,
but was a bit too simple/unrealistic.
This patch teaches debugify to insert debug values immediately after their
operand defs. This enables better testing of the compiler.
For example, with this patch, `opt -debugify-each` is able to identify a
vectorizer DI-invariance bug fixed in llvm.org/PR32761. In this bug, the
vectorizer produced different output with/without debug info present.
Reverting Davide's bugfix locally, I see:
$ ~/scripts/opt-check-dbg-invar.sh ./bin/opt \
.../SLPVectorizer/AArch64/spillcost-di.ll -slp-vectorizer
Comparing: -slp-vectorizer .../SLPVectorizer/AArch64/spillcost-di.ll
Baseline: /var/folders/j8/t4w0bp8j6x1g6fpghkcb4sjm0000gp/T/tmp.iYYeL1kf
With DI : /var/folders/j8/t4w0bp8j6x1g6fpghkcb4sjm0000gp/T/tmp.sQtQSeet
9,11c9,11
< %5 = getelementptr inbounds %0, %0* %2, i64 %0, i32 1
< %6 = bitcast i64* %4 to <2 x i64>*
< %7 = load <2 x i64>, <2 x i64>* %6, align 8, !tbaa !0
---
> %5 = load i64, i64* %4, align 8, !tbaa !0
> %6 = getelementptr inbounds %0, %0* %2, i64 %0, i32 1
> %7 = load i64, i64* %6, align 8, !tbaa !5
12a13
> store i64 %5, i64* %8, align 8, !tbaa !0
14,15c15
< %10 = bitcast i64* %8 to <2 x i64>*
< store <2 x i64> %7, <2 x i64>* %10, align 8, !tbaa !0
---
> store i64 %7, i64* %9, align 8, !tbaa !5
:: Found a test case ^
Running this over the *.ll files in tree, I found four additional examples
which compile differently with/without DI present. I plan on filing bugs for
these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334118
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Vedant Kumar [Wed, 6 Jun 2018 19:05:41 +0000 (19:05 +0000)]
[Debugify] Add a quiet mode to suppress warnings
Suppressing warning output and module dumps significantly speeds up
fuzzing with `opt -debugify-each`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334117
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Evandro Menezes [Wed, 6 Jun 2018 18:56:00 +0000 (18:56 +0000)]
[AArch64, ARM] Add support for Samsung Exynos M4
Create a separate feature set for Exynos M4 and add test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334115
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Han Shen [Wed, 6 Jun 2018 18:53:17 +0000 (18:53 +0000)]
Fix the test case that places intermediate in source directory.
This causes "permission denied" error in some controlled test environment where source tree is read-only.
Differential Revision: https://reviews.llvm.org/D47839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334114
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Michael Berg [Wed, 6 Jun 2018 18:47:55 +0000 (18:47 +0000)]
guard fsqrt with fmf sub flags
Summary:
This change uses fmf subflags to guard optimizations as well as unsafe. These changes originated from D46483.
It contains only context for fsqrt.
Reviewers: spatel, hfinkel, arsenm
Reviewed By: spatel
Subscribers: hfinkel, wdng, andrew.w.kaylor, wristow, efriedma, nemanjai
Differential Revision: https://reviews.llvm.org/D47749
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334113
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Teresa Johnson [Wed, 6 Jun 2018 18:32:16 +0000 (18:32 +0000)]
[ThinLTO] Make ValueInfo operator!= consistent with operator== (NFC)
Compare Ref pointers instead of GUID, to handle comparison with special
empty/tombstone ValueInfo. This was already done for operator==, to
support inserting ValueInfo into DenseMap, but I need the operator!=
side change for upcoming AsmParser summary parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334111
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Simon Pilgrim [Wed, 6 Jun 2018 18:20:25 +0000 (18:20 +0000)]
[llvm-mca][x86] Fix all resources-x86_64.s tests to use different registers in reg-reg cases
I noticed while working on zero-idiom + dependency-breaking support (PR36671) that most of our binary instruction tests were reusing the same src registers, which would cause the tests to fail once we enable scalar zero-idiom support on btver2. Fixed in all targets to keep them in sync.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334110
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Krzysztof Parzyszek [Wed, 6 Jun 2018 18:03:29 +0000 (18:03 +0000)]
[Hexagon] Split CTPOP of vector pairs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334109
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Sanjay Patel [Wed, 6 Jun 2018 16:53:56 +0000 (16:53 +0000)]
[ConstProp] move tests for fp <--> int; NFC
These were added for D5603 / rL219542, and there's a proposal to
change one side in D47807.
These are tests of constant propagation, so they shouldn't have
ever been tested/housed under InstCombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334107
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Petar Jovanovic [Wed, 6 Jun 2018 16:36:30 +0000 (16:36 +0000)]
Change TII isCopyInstr way of returning arguments(NFC)
Make TII isCopyInstr() return MachineOperands through pointer to pointer
instead via reference.
Patch by Nikola Prica.
Differential Revision: https://reviews.llvm.org/D47364
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334105
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Simon Pilgrim [Wed, 6 Jun 2018 16:14:37 +0000 (16:14 +0000)]
[X86][BtVer2] Add tests for all vector instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), all these instructions are dependency breaking and zero the destination register.
TODO: Scalar instructions still need to be tested (need to check EFLAGS handling).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334104
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Hans Wennborg [Wed, 6 Jun 2018 14:53:03 +0000 (14:53 +0000)]
Relax shtest-run-at-line.py
The test was failing on Windows machines which had bash.exe on PATH (but
not in the so called lit tools dir, containing cmp.exe, grep.exe etc.).
The problem was that the outer lit invocation would load LLVMConfig
from utils/lit/lit/llvm/config.py, which looks up the tools path with
getToolsPath(). That has a surprising side effect of also setting
bashPath, in our case setting it to empty.
The outer lit invocation would thus configure the pdbg0 and pdbg1
substitutions based on not running with bash.
But the inner lit invocation would not load LLVMConfig, so bash
would be found on PATH, that would be used as external shell,
and so the output wouldn't match pdbg0 and pdbg1.
It seems weird to me that getBashPath() will return different results
depending on whether getToolsPath() has been called before, but I
also don't know how to fix it properly.
This commit just relaxes the test case, because there doesn't seem
to be much point in testing for the exact syntax of the run file
as long as it works.
(See https://crbug.com/850023)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334100
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David Green [Wed, 6 Jun 2018 14:48:32 +0000 (14:48 +0000)]
[GlobalMerge] Set the alignment on merged global structs
If no alignment is set, the abi/preferred alignment of structs will be
used which may be higher than required. This can lead to extra padding
and in the end an increase in data size.
Differential Revision: https://reviews.llvm.org/D47633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334099
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Kristof Beyls [Wed, 6 Jun 2018 14:19:58 +0000 (14:19 +0000)]
Avoid UnicodeEncodeError on non-ascii reviewer names
... by using unicode instead of byte strings where non-ascii strings can be
formatted in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334098
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Simon Dardis [Wed, 6 Jun 2018 13:30:39 +0000 (13:30 +0000)]
[mips] Add testcase for i64, i128 addition for the DSP ASE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334094
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Tim Northover [Wed, 6 Jun 2018 12:46:02 +0000 (12:46 +0000)]
InstCombine: ignore debug instructions during fence combine
We should never get different CodeGen based on whether the code is being
compiled in debug mode so we must skip over @llvm.dbg.value (and similar)
calls.
Should fix at least the worst part of PR37690.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334090
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Greg Bedwell [Wed, 6 Jun 2018 11:15:54 +0000 (11:15 +0000)]
Update the project name in README.txt
Per llvm.org: "The name "LLVM" itself is not an acronym; it is the full
name of the project."
Differential Revision: https://reviews.llvm.org/D47796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334087
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Simon Pilgrim [Wed, 6 Jun 2018 11:10:11 +0000 (11:10 +0000)]
Fix MSVC '*/' found outside of comment warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334086
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Ilya Biryukov [Wed, 6 Jun 2018 10:57:50 +0000 (10:57 +0000)]
Fix compilation of WebAssembly and RISCV after r334078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334085
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Simon Dardis [Wed, 6 Jun 2018 10:54:30 +0000 (10:54 +0000)]
[mips] Partially revert r334031
The test changes in r334031 give unstable pass/fail results on the
llvm-clang-x86_64-expensive-checks-win buildbot. Revert the test changes to
turn the bot green.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334084
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Simon Pilgrim [Wed, 6 Jun 2018 10:52:10 +0000 (10:52 +0000)]
[X86][BMI][TBM] Only demand bottom 16-bits of the BEXTR control op (PR34042)
Only the bottom 16-bits of BEXTR's control op are required (0:8 INDEX, 15:8 LENGTH).
Differential Revision: https://reviews.llvm.org/D47690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334083
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Pavel Labath [Wed, 6 Jun 2018 10:07:08 +0000 (10:07 +0000)]
[cmake] fix a typo in llvm_config macro
Summary:
The macro parses out the USE_SHARED option out of the argument list, but
then ignores it and accesses the variable with the same name instead. It
seems the intention here was to check the argument value.
Technically, this is NFC, because the only in-tree usage
(add_llvm_executable) of USE_SHARED sets both the variable and the
argument when calling llvm_config, but it makes the usage of this macro
for out-of-tree users more sensible.
Reviewers: mgorny, beanz
Reviewed By: mgorny
Subscribers: foutrelis, llvm-commits
Differential Revision: https://reviews.llvm.org/D44420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334082
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Clement Courbet [Wed, 6 Jun 2018 09:42:36 +0000 (09:42 +0000)]
[llvm-exegesis] move Mode from Key to BenchmarResult.
Moves the Mode field out of the Key. The existing yaml benchmark results can be fixed with the following script:
```
readonly FILE=$1
readonly MODE=latency # Change to uops to fix a uops benchmark.
cat $FILE | \
sed "/^\ \+mode:\ \+$MODE$/d" | \
sed "/^cpu_name.*$/i mode: $MODE"
```
Differential Revision: https://reviews.llvm.org/D47813
Authored by: Guillaume Chatelet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334079
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Peter Smith [Wed, 6 Jun 2018 09:40:06 +0000 (09:40 +0000)]
[MC] Pass MCSubtargetInfo to fixupNeedsRelaxation and applyFixup
On targets like Arm some relaxations may only be performed when certain
architectural features are available. As functions can be compiled with
differing levels of architectural support we must make a judgement on
whether we can relax based on the MCSubtargetInfo for the function. This
change passes through the MCSubtargetInfo for the function to
fixupNeedsRelaxation so that the decision on whether to relax can be made
per function. In this patch, only the ARM backend makes use of this
information. We must also pass the MCSubtargetInfo to applyFixup because
some fixups skip error checking on the assumption that relaxation has
occurred, to prevent code-generation errors applyFixup must see the same
MCSubtargetInfo as fixupNeedsRelaxation.
Differential Revision: https://reviews.llvm.org/D44928
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334078
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Elena Demikhovsky [Wed, 6 Jun 2018 09:11:46 +0000 (09:11 +0000)]
Added documentation for Masked Vector Expanding Load and Compressing Store Intrinsics
Differential Revision: https://reviews.llvm.org/D26743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334075
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Petar Jovanovic [Wed, 6 Jun 2018 07:24:52 +0000 (07:24 +0000)]
[MIPS GlobalISel] Add lowerCall
Add minimal support to lower function calls.
Support only functions with arguments/return that go through registers
and have type i32.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D45627
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334071
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Petr Hosek [Wed, 6 Jun 2018 06:26:18 +0000 (06:26 +0000)]
[Support] Use zx_cache_flush on Fuchsia to flush instruction cache
Fuchsia doesn't use __clear_cache, instead it provide zx_cache_flush
system call. Use it to flush instruction cache.
Differential Revision: https://reviews.llvm.org/D47753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334068
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Vlad Tsyrklevich [Wed, 6 Jun 2018 06:25:37 +0000 (06:25 +0000)]
[Analyzer] Fix the Z3 lit test config
Summary:
The '%analyze' extra_args config argument seems to have been erroneously
deleted in r315627 disabling Z3 tests for the clang analyzer. Add the
flag back.
Reviewers: george.karpenkov, NoQ, ddcc
Reviewed By: george.karpenkov
Subscribers: xazax.hun, szepet, delcypher, a.sidorin, llvm-commits
Differential Revision: https://reviews.llvm.org/D47722
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334066
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Sanjay Patel [Tue, 5 Jun 2018 23:34:45 +0000 (23:34 +0000)]
[CodeGen] assume max/default throughput for unspecified instructions
This is a fix for the problem arising in D47374 (PR37678):
https://bugs.llvm.org/show_bug.cgi?id=37678
We may not have throughput info because it's not specified in the model
or it's not available with variant scheduling, so assume that those
instructions can execute/complete at max-issue-width.
Differential Revision: https://reviews.llvm.org/D47723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334055
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Amaury Sechet [Tue, 5 Jun 2018 22:13:56 +0000 (22:13 +0000)]
[Mips] Remove uneeded variants of ADDC/ADDE lowering
Summary: As it turns out, the lowering for the Mips16* family of target is the exact same thing as what the ops expands to, so the code handling them can be removed and the ops only enabled for the MipsSE* family of targets.
Reviewers: smaksimovic, atanasyan, abeserminji
Subscribers: sdardis, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D47703
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334052
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Guozhi Wei [Tue, 5 Jun 2018 21:03:52 +0000 (21:03 +0000)]
[CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions
CodeGenPrepare pass move extension instructions close to load instructions in different BB, so they can be combined later. But the extension instructions can't move through logical and shift instructions in current implementation. This patch enables this enhancement, so we can eliminate more extension instructions.
Differential Revision: https://reviews.llvm.org/D45537
This is re-commit of r331783, which was reverted by r333305. The performance regression was caused by some unlucky alignment, not a code generation problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334049
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Zachary Turner [Tue, 5 Jun 2018 19:58:26 +0000 (19:58 +0000)]
[FileSystem] Remove OpenFlags param from several functions.
There was only one place in the entire codebase where a non
default value was being passed, and that place was already hidden
in an implementation file. So we can delete the extra parameter
and all existing clients continue to work as they always have,
while making the interface a bit simpler.
Differential Revision: https://reviews.llvm.org/D47789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334046
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Matt Arsenault [Tue, 5 Jun 2018 19:52:56 +0000 (19:52 +0000)]
AMDGPU: Preserve metadata when widening loads
Preserves the low bound of the !range. I don't think
it's legal to do anything with the top half since it's
theoretically reading garbage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334045
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Matt Arsenault [Tue, 5 Jun 2018 19:52:46 +0000 (19:52 +0000)]
AMDGPU: Use more custom insert/extract_vector_elt lowering
Apply to i8 vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334044
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Krzysztof Parzyszek [Tue, 5 Jun 2018 19:52:39 +0000 (19:52 +0000)]
[Hexagon] Add pattern to generate 64-bit neg instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334043
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Krzysztof Parzyszek [Tue, 5 Jun 2018 19:00:50 +0000 (19:00 +0000)]
[Hexagon] Add more patterns for generating abs/absp instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334038
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Michael Berg [Tue, 5 Jun 2018 18:49:47 +0000 (18:49 +0000)]
guard fneg with fmf sub flags
Summary: This change uses fmf subflags to guard optimizations as well as unsafe. These changes originated from D46483.
Reviewers: spatel, hfinkel
Reviewed By: spatel
Subscribers: nemanjai
Differential Revision: https://reviews.llvm.org/D47389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334037
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Michael Berg [Tue, 5 Jun 2018 18:12:25 +0000 (18:12 +0000)]
NFC: adding baseline fneg case for fmf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334035
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Simon Dardis [Tue, 5 Jun 2018 17:53:22 +0000 (17:53 +0000)]
[mips] Fix the predicates for arithmetic operations
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D47635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334031
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Greg Bedwell [Tue, 5 Jun 2018 17:16:19 +0000 (17:16 +0000)]
[UpdateTestChecks] Error if --llvm-mca-binary gets an empty string
If the command line was mistyped like:
./update_mca_test_checks.py --llvm-mca-binary= /path/to/llvm-mca *.s
^-- extra whitespace
then /path/to/llvm-mca would get treated by argparse as a test-path
pattern and could actually be opened in write mode and overwritten.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334029
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Andrea Di Biagio [Tue, 5 Jun 2018 17:12:02 +0000 (17:12 +0000)]
[llvm-mca] Correctly update the CyclesLeft of a register read in the presence of partial register updates.
This patch fixe the logic in ReadState::cycleEvent(). That method was not
correctly updating field `TotalCycles`.
Added extra code comments in class ReadState to better describe each field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334028
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Fangrui Song [Tue, 5 Jun 2018 16:59:40 +0000 (16:59 +0000)]
Remove a self-referencing #include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334027
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Simon Pilgrim [Tue, 5 Jun 2018 15:17:39 +0000 (15:17 +0000)]
[X86][SSE] Use multiplication scale factors for v8i16 SHL on pre-AVX2 targets.
Similar to v4i32 SHL, convert v8i16 shift amounts to scale factors instead to improve performance and reduce instruction count. We were already doing this for constant shifts, this adds variable shift support.
Reduces the serial nature of the codegen, which relies on chains of plendvb/pand+pandn+por shifts.
This is a step towards adding support for vXi16 vector rotates.
Differential Revision: https://reviews.llvm.org/D47546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334023
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Nirav Dave [Tue, 5 Jun 2018 15:13:39 +0000 (15:13 +0000)]
[MC][X86] Allow assembler variable assignment to register name.
Summary:
Allow extended parsing of variable assembler assignment syntax and modify X86 to permit
VAR = register assignment. As we emit these as .set directives when possible, we inline
such expressions in output assembly.
Fixes PR37425.
Reviewers: rnk, void, echristo
Reviewed By: rnk
Subscribers: nickdesaulniers, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D47545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334022
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Matt Arsenault [Tue, 5 Jun 2018 14:52:24 +0000 (14:52 +0000)]
DAG: Stop dropping invariant/dereferencable
When legalizing illegal FP load results, this was
for some reason dropping the invariant and dereferencable
memory flags. There doesn't seem to be any reason for this,
and the equivalent isn't done for integer loads.
Fixes an issue in a future AMDGPU commit where some identical
loads fail to merge because one of the loads ends up
dropping the flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334020
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John Brawn [Tue, 5 Jun 2018 14:10:55 +0000 (14:10 +0000)]
[InstCombine] Correct the cmp operand type used when canonicalizing abs/nabs
When adjusting a cmp in order to canonicalize an abs/nabs select pattern we need
to use the type of the existing operand when creating a new operand not the
type of a select operand, as the two may be different.
This fixes PR37686.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334019
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Gabor Buella [Tue, 5 Jun 2018 12:55:12 +0000 (12:55 +0000)]
[X86] NFC Fix typo introduced in r328016 HSI->HDI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334016
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Krzysztof Parzyszek [Tue, 5 Jun 2018 12:49:19 +0000 (12:49 +0000)]
[Hexagon] Minor cleanups in isel lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334015
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Hiroshi Inoue [Tue, 5 Jun 2018 11:58:01 +0000 (11:58 +0000)]
[PowerPC] reduce rotate in BitPermutationSelector
BitPermutationSelector builds the output value by repeating rotate-and-mask instructions with input registers.
Here, we may avoid one rotate instruction if we start building from an input register that does not require rotation.
For example of the test case bitfieldinsert.ll, it first rotates left r4 by 8 bits and then inserts some bits from r5 without rotation.
This can be executed by one rlwimi instruction, which rotates r4 by 8 bits and inserts its bits into r5.
This patch adds a check for rotation amounts in the comparator used in sorting to process the input without rotation first.
Differential Revision: https://reviews.llvm.org/D47765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334011
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Simon Pilgrim [Tue, 5 Jun 2018 11:38:11 +0000 (11:38 +0000)]
[X86][SSE] Fix line endings for shuffle-vs-trunc tests. NFCI.
Strip native eol property which we don't use in this folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334010
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Clement Courbet [Tue, 5 Jun 2018 10:56:19 +0000 (10:56 +0000)]
[llvm-exegesis] Add instructions to BenchmarkResult Key.
We want llvm-exegesis to explore instructions (effect of initial register values, effect of operand selection). To enable this a BenchmarkResult muststore all the relevant data in its key. This patch starts adding such data. Here we simply allow to store the generated instructions, following patches will add operands and initial values for registers.
https://reviews.llvm.org/D47764
Authored by: Guilluame Chatelet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334008
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Simon Pilgrim [Tue, 5 Jun 2018 10:52:29 +0000 (10:52 +0000)]
[X86][SSE] Add target shuffle support to X86TargetLowering::computeKnownBitsForTargetNode
Ideally we'd use resolveTargetShuffleInputs to handle faux shuffles as well but:
(a) that code path doesn't handle general/pre-legalized ops/types very well.
(b) I'm concerned about the compute time as they recurse to calls to computeKnownBits/ComputeNumSignBits which would need depth limiting somehow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334007
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Gabor Buella [Tue, 5 Jun 2018 10:41:39 +0000 (10:41 +0000)]
[X86] NFC Refactor some code in InstPrinters
Summary:
Bringing some come duplicated in the AT&T and the Intel printers
into a common parent class.
Reviewers: craig.topper
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D47682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334005
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Peter Smith [Tue, 5 Jun 2018 10:00:56 +0000 (10:00 +0000)]
[MC][ARM] Add range checking for Thumb2 resolved fixups.
When the branch target of a Thumb2 unconditional or conditonal branch is
resolved at assembly time, no range checking is performed on the result
leading to incorrect immediates. This change adds a range check:
+- 16 Megabytes for unconditional branches, +- 1 Megabyte for the
conditional branch.
Differential Revision: https://reviews.llvm.org/D46306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333997
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Simon Pilgrim [Tue, 5 Jun 2018 09:45:03 +0000 (09:45 +0000)]
[X86][SSE] Add basic PACKUS support to X86TargetLowering::computeKnownBitsForTargetNode
Helps improve analysis of saturation ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333995
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Peter Smith [Tue, 5 Jun 2018 09:32:28 +0000 (09:32 +0000)]
[MC][ARM] Correct Thumb BL instruction range
The Thumb BL range is + or - either 16 Megabytes or 4 Megabytes depending
on whether the CPU supports Thumb2 or the v8-m baseline ops. The existing
check for BL range is incorrectly set at +- 32 Megabytes. This change
corrects the higher range and uses the lower range if the featurebits
don't have the necessary support for it.
Differential Revision: https://reviews.llvm.org/D46305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333991
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Alexander Ivchenko [Tue, 5 Jun 2018 09:22:30 +0000 (09:22 +0000)]
[X86][CET] Shadow stack fix for setjmp/longjmp
This is the new version of D46181, allowing setjmp/longjmp
to work correctly with the Intel CET shadow stack by storing
SSP on setjmp and fixing it on longjmp. The patch has been
updated to use the cf-protection-return module flag instead
of HasSHSTK, and the bug that caused D46181 to be reverted
has been fixed with the test expanded to track that fix.
patch by mike.dvoretsky
Differential Revision: https://reviews.llvm.org/D47311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333990
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Craig Topper [Tue, 5 Jun 2018 06:20:06 +0000 (06:20 +0000)]
[X86] Make all instructions that operate on MMX types, but were added after the initial MMX support via one of the SSE features flags make them require the MMX feature as well.
Passing -mattr=-mmx needs to disable these instructions since the MMX register class won't have been set up. But we don't want -mattr=-mmx to disable SSE so we have to do it separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333984
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Nirav Dave [Tue, 5 Jun 2018 03:16:28 +0000 (03:16 +0000)]
[RegAllocGreedy] Use simpler map class for EvicteeInfo. NFCI.
RegAlloc keeps a insertion-time ordered map of evictee information,
but we only use membership. Replace MapVector with contextually
equivalent DenseMap which is smaller and faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333981
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Vedant Kumar [Tue, 5 Jun 2018 00:56:08 +0000 (00:56 +0000)]
[opt] Introduce -strip-named-metadata
This renames and generalizes -strip-module-flags to erase all named
metadata from a module. This makes it easier to diff IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333977
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Vedant Kumar [Tue, 5 Jun 2018 00:56:07 +0000 (00:56 +0000)]
[Debugify] Don't insert debug values after terminating deopts
As is the case with musttail calls, the IR does not allow for
instructions inserted after a terminating deopt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333976
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Vedant Kumar [Tue, 5 Jun 2018 00:56:07 +0000 (00:56 +0000)]
Apply clang-format on a file, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333975
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Francis Visoiu Mistrih [Tue, 5 Jun 2018 00:27:28 +0000 (00:27 +0000)]
Use MF instead of Fn for MachineFunction references. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333973
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