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Eric Engestrom [Thu, 16 Aug 2018 14:47:13 +0000 (15:47 +0100)]
anv: drop cast-to-void of used variable
`device` is used 2 lines below, even visible in the diff context printed.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Eric Engestrom [Thu, 16 Aug 2018 14:46:31 +0000 (15:46 +0100)]
anv: use safer snprintf() to ensure NULL string-terminator
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Eric Engestrom [Thu, 16 Aug 2018 14:37:22 +0000 (15:37 +0100)]
intel/batch-decoder: replace local ARRAY_LENGTH() macro with global ARRAY_SIZE()
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Eric Engestrom [Thu, 16 Aug 2018 14:41:53 +0000 (15:41 +0100)]
intel: various python cleanups
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Thu, 16 Aug 2018 14:31:55 +0000 (15:31 +0100)]
egl: check for buffer overflow *before* corrupting our memory
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Thu, 16 Aug 2018 14:26:10 +0000 (15:26 +0100)]
egl/wayland: remove sign from bitfield `formats`
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Thu, 16 Aug 2018 15:07:12 +0000 (16:07 +0100)]
mailmap: add various typos of Emil's address from the log
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Fri, 10 Aug 2018 11:37:17 +0000 (12:37 +0100)]
egl: some spelling fixes
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Samuel Pitoiset [Thu, 16 Aug 2018 10:33:13 +0000 (12:33 +0200)]
radv: initialize the DCC predicate correctly when it's compressed
We have to do a fast-clear eliminate when clearing DCC
metadata with 0x20202020. I don't know if that fixes anything
but that seems correct to me.
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 16 Aug 2018 09:22:37 +0000 (11:22 +0200)]
radv: fix missing initialization of the conditional rendering state
This was missing when VK_EXT_conditional_rendering has been
implemented. The predication type should be -1 to avoid
restoring previous state when performing a decompression pass
with DCC enabled.
Note that we don't have to handle secondary command buffers
because we don't support this feature currently.
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Engestrom [Tue, 14 Aug 2018 17:02:04 +0000 (18:02 +0100)]
bin: split `write_if_different()` out
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Tue, 14 Aug 2018 17:05:55 +0000 (18:05 +0100)]
bin: whitespace cleanup
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Bas Nieuwenhuizen [Wed, 15 Aug 2018 14:28:24 +0000 (16:28 +0200)]
radv: Revert divisor = 0 case for vertex attribute extension.
Seems like DXVK depends on that and it might get reverted
upstream. Since apps are not supposed to use 0 in v2 anyway,
we should be safe implementing the old behavior there.
Fixes:
66e12451ac4 "radv: Update to new VK_EXT_vertex_attribute_divisor to version 2."
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Wed, 15 Aug 2018 14:00:02 +0000 (16:00 +0200)]
radv: Possible on-demand compilation fix.
Seems that in a single case we use the renderpass before checking
the pipeline, so check the renderpass before we use it.
Fixes:
fbcd1673144 "radv: Add on-demand compilation of built-in shaders."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Gert Wollny [Wed, 15 Aug 2018 17:30:59 +0000 (19:30 +0200)]
mesa/st: fix array indices off-by-one error in remapping
When moving the array sizes from the old list to the new one it was
not taken into account that the array indices start with one, but the
array_size array started at index zero, which resulted in incorrect array
sizes when arrays were merged. Correct this by copying the array_size
values of the retained arrays with an offset of -1.
Also fix whitespaces for the replaced lines.
Fixes:
d8c2119f9b0b257a23ceb398f6d0d78da916417e
mesa/st/glsl_to_tgsi: Expose array live range tracking and merging
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Alexander Tsoy [Wed, 15 Aug 2018 20:54:46 +0000 (23:54 +0300)]
meson: fix build for egl platform_x11 without dri3 and gbm
Compiling EGL's platform_x11 without dri3 and gbm yields this compile
failure:
platform_x11 needs inc_loader:
../mesa-18.2.0-rc2/src/egl/drivers/dri2/platform_x11.c:48:10: fatal
error: loader.h: No such file or directory
#include "loader.h"
^~~~~~~~~~
Fixes:
108d257a1685 ("meson: build libEGL")
Bugzilla: https://bugs.gentoo.org/663534
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Wed, 8 Aug 2018 19:00:55 +0000 (12:00 -0700)]
Revert "intel/nir: Call nir_lower_io_to_scalar_early"
Commit
4434591bf56a6b0 caused substantially more URB messages in
geometry and tessellation shaders. Before we can really enable this
sort of optimization, We either need some way of combining them back
together into vectors or we need to do cross-stage vector element
elimination without splitting everything into scalars.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107510
Fixes:
4434591bf56a6 "intel/nir: Call nir_lower_io_to_scalar_early"
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Erik Faye-Lund [Tue, 7 Aug 2018 19:31:20 +0000 (21:31 +0200)]
i965: do not emit empty surface state
If called with an empty size, brw_emit_buffer_surface_state asserts.
We already have a dedicated helper for uploading nothing, so let's use
that instead.
Avoids an assert in
dEQP-GLES31.functional.shaders.opaque_type_indexing.ssbo.const_literal_vertex
when running a debug build of i965.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Sergii Romantsov [Wed, 15 Aug 2018 11:23:43 +0000 (14:23 +0300)]
intel/ppgtt: 4096 replaced by PAGE_SIZE
Usage of number 4096 replaced by PAGE_SIZE.
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Sergii Romantsov [Wed, 15 Aug 2018 11:23:42 +0000 (14:23 +0300)]
intel/ppgtt: memory address alignment
Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).
-v2: added marking that also fixes initial commit
01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris Wilson).
-v4: changes related to PAGE_SIZE moved to separate commit
-v5: restored alignment to page-size for 0-size.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
Fixes:
a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.)
Fixes:
01058a552294 (i965: Add virtual memory allocator infrastructure to brw_bufmgr.)
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Wed, 15 Aug 2018 11:12:13 +0000 (21:12 +1000)]
radv: add Doom workaround
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Sergii Romantsov [Wed, 15 Aug 2018 12:21:47 +0000 (15:21 +0300)]
i965: Emitting 3DSTATE_SO_BUFFER of 0-size.
Avoided filling of whole structure and bo-allocation if
size of surface is 0.
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Erik Faye-Lund [Tue, 14 Aug 2018 12:06:02 +0000 (13:06 +0100)]
virgl: report actual max-texture sizes
Instead of doing conservative guesses, we should report the max levels
based on the max sizes we get from GL on the host.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>
Erik Faye-Lund [Tue, 14 Aug 2018 12:10:23 +0000 (13:10 +0100)]
virgl: do not use SP_MAX_TEXTURE_*_LEVELS defines
These macro-names are also used for softpipe, so let's avoid confusion
by avoiding them. Besides, they are just used in one place in virgl, so
let's just inline them into the place they are used instead.
While we're at it, fixup an error in the comment for the 3D version.
Mesa subtracts computes max-size by doing by 2^(n-1), which means this
should be 256 cubed, not 512 cubed. The other comments are correct.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>
Dylan Baker [Wed, 15 Aug 2018 16:09:59 +0000 (09:09 -0700)]
docs: Add news item for 18.1.6
Samuel Pitoiset [Wed, 15 Aug 2018 13:09:52 +0000 (15:09 +0200)]
radv: disable the auto-waitcnt-before-barrier LLVM option
This option allows us to remove additional s_waitcnt instructions
because s_barrier internally does s_waitcnt 0.
Though, apparently there is a problem with LDS accesses that
causes rendering issues with FFXV and DXVK. Disable this
optimization for now (RadeonSI still uses it).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 15 Aug 2018 13:28:43 +0000 (15:28 +0200)]
radv: fix memory leaks in radv_load_meta_pipeline()
Reported by Coverity.
Fixes:
fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 14 Aug 2018 16:11:48 +0000 (18:11 +0200)]
radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITS
The last parameter of radeon_set_sh_reg_seq() is the number of
dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but
it was initialized to 0.
COMPUTE_RESOURCE_LIMITS is correctly set when generating
compute pipelines, so we don't need to initialize it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Andres Gomez [Wed, 15 Aug 2018 12:48:18 +0000 (15:48 +0300)]
docs: update calendar 18.2.0-rc3 is out
Signed-off-by: Andres Gomez <agomez@igalia.com>
Mauro Rossi [Tue, 14 Aug 2018 19:10:54 +0000 (21:10 +0200)]
radv/meta_decompress: fix pointer to integer conversion
VK_NULL_HANDLE replaces NULL to avoid following building error:
external/mesa/src/amd/vulkan/radv_meta_decompress.c:365:54: error:
incompatible pointer to integer conversion passing 'void *' to parameter
of type 'VkShaderModule' (aka 'unsigned long long') [-Werror,-Wint-conversion]
VkResult ret = create_pipeline(cmd_buffer->device, NULL, samples,
^~~~
prebuilts/clang/host/linux-x86/clang-
4053586/lib64/clang/5.0.300080/include/stddef.h:105:16:
note: expanded from macro 'NULL'
# define NULL ((void*)0)
^~~~~~~~~~
external/mesa/src/amd/vulkan/radv_meta_decompress.c:97:32:
note: passing argument to parameter 'vs_module_h' here
VkShaderModule vs_module_h,
^
1 error generated.
Fixes:
fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Mauro Rossi [Tue, 14 Aug 2018 13:10:54 +0000 (15:10 +0200)]
egl/android: fix regression in drm_gralloc path (v2)
This patch fixes a regression in mesa 18.2 and mesa-dev branches
for HAVE_DRM_GRALLOC code path which is causing black screen on Android
and prevents boot due to SIGSEGV MAPERR crash related to unproper handling
of drm_gralloc drm FD in new droid_open_device() path.
Problem is due to
c7bb82136b ("egl/android: Add DRM node probing and filtering")
To avoid the crash the former existing working droid_open_device() is restored,
renamed droid_open_device_drm_gralloc() and kept within HAVE_DRM_GRALLOC braces.
Tested with mesa-dev and mesa 18.2 branch and oreo-x86 bootanimation
and Androdi GUI booting is fixed with i965, nouveau, radeon.
The changes are compatible with gbm_gralloc, I've tested build with hwc too.
(v2) remove indentation from HAVE_DRM_GRALLOC pre-processor directive
NOTE: Definition of enum{} for GRALLOC_MODULE_PERFORM_GET_DRM_FD
is not necessary and it's actually causing a redefinition building error,
because in HAVE_DRM_GRALLOC path gralloc_drm.h is already exported
by libgralloc_drm which is currently still a dependency.
Fixes:
c7bb82136b ("egl/android: Add DRM node probing and filtering")
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Tapani Pälli [Tue, 24 Jul 2018 07:41:46 +0000 (10:41 +0300)]
mesa: shader dump/read support for ARB programs
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106283
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Danylo Piliaiev [Mon, 13 Aug 2018 15:57:38 +0000 (18:57 +0300)]
glsl: Avoid calling get_array_element for scalar constants
Accessing scalar constant as an array in function call or
initializer list triggered assert in get_array_element.
Examples:
func(0[0]);
vec2 t = { 0[0], 0 };
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107550
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Marek Olšák [Fri, 10 Aug 2018 03:46:38 +0000 (23:46 -0400)]
radeonsi: enable 1 missing PS_SU perf counter on Polaris
Marek Olšák [Fri, 10 Aug 2018 18:31:15 +0000 (14:31 -0400)]
radeonsi: use radeon_info::name
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Fri, 3 Aug 2018 02:21:02 +0000 (22:21 -0400)]
ac: add radeon_info::name
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Fri, 3 Aug 2018 00:32:30 +0000 (20:32 -0400)]
radeonsi: split si_clear_buffer to remove enum si_method
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Fri, 3 Aug 2018 00:25:11 +0000 (20:25 -0400)]
radeonsi: replace CP_DMA_USE_L2 with enum si_cache_policy
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Fri, 3 Aug 2018 00:03:03 +0000 (20:03 -0400)]
radeonsi: declare coher in si_copy_buffer
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Thu, 2 Aug 2018 23:56:18 +0000 (19:56 -0400)]
radeonsi: make PFP_SYNC_ME an explicit CP DMA flag
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 06:36:17 +0000 (02:36 -0400)]
radeonsi: don't use emit_data->args in load_emit
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 06:06:54 +0000 (02:06 -0400)]
radeonsi: don't use emit_data->args in store_emit
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 04:15:18 +0000 (00:15 -0400)]
radeonsi: don't use emit_data->args in atomic_emit
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 03:24:06 +0000 (23:24 -0400)]
radeonsi: don't use emit_data->args in build_interp_intrinsic
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 03:19:48 +0000 (23:19 -0400)]
radeonsi: inline atomic_fetch_args
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 03:12:13 +0000 (23:12 -0400)]
radeonsi: inline store_fetch_args
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 02:36:58 +0000 (22:36 -0400)]
radeonsi: inline load_fetch_args
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 01:25:43 +0000 (21:25 -0400)]
radeonsi: merge txq_emit and resq_emit
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 01:11:06 +0000 (21:11 -0400)]
radeonsi: inline resq_fetch_args
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 00:54:26 +0000 (20:54 -0400)]
radeonsi: inline txq_fetch_args
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 02:25:06 +0000 (22:25 -0400)]
radeonsi: use get_resinfo directly in lower_gather4_integer
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 00:39:50 +0000 (20:39 -0400)]
radeonsi: inline tex_fetch_args into build_tex_intrinsic
The diff looks like it moves code that I didn't touch.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 4 Aug 2018 00:22:34 +0000 (20:22 -0400)]
radeonsi: remove fetch_args callbacks for ALU instructions
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Thu, 2 Aug 2018 21:40:05 +0000 (17:40 -0400)]
radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.c
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Mon, 6 Aug 2018 08:20:30 +0000 (04:20 -0400)]
radeonsi: implement EXT_window_rectangles
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Mon, 6 Aug 2018 08:16:47 +0000 (04:16 -0400)]
gallium/u_blitter: save/restore window rectangles
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Mon, 6 Aug 2018 08:16:18 +0000 (04:16 -0400)]
noop: implement set_window_rectangles
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Mon, 6 Aug 2018 08:15:47 +0000 (04:15 -0400)]
ddebug: implement set_window_rectangles
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Rodrigo Vivi [Thu, 9 Aug 2018 05:43:00 +0000 (22:43 -0700)]
i965: Add a new CFL PCI ID.
One more CFL ID added to spec.
Align with kernel commit
d0e062ebb3a4 ("drm/i915/cfl:
Add a new CFL PCI ID.")
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Rob Clark [Sat, 11 Aug 2018 14:30:38 +0000 (10:30 -0400)]
freedreno/ir3: add support for a6xx 'merged' register set
Starting with a6xx, half and full precision registers conflict. Which
makes things a bit more efficient, ie. if some parts of the shader are
heavy on half-precision and others on full precision, you don't have to
allocate the worst case for both. But it means we need to setup some
additional conflicts.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 10 Aug 2018 18:16:54 +0000 (14:16 -0400)]
freedreno/ir3: small RA cleanup
Collapse is_temp() into it's only callsite, and pass compiler object as
struct rather than void. Just cleanups to reduce noise in next patch.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 10 Aug 2018 15:57:26 +0000 (11:57 -0400)]
freedreno/ir3: stop hard-coding FS input regs
We originally did this because at the time we didn't know all the
bitfields to configure where various frag shader sysval's went. But
we do.
So switch to using sysvals for all the frag shader inputs.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 10 Aug 2018 16:23:47 +0000 (12:23 -0400)]
freedreno/ir3: use r63.x for unused inputs
This way, unused sysval inputs, like frag_vcoord, get the correct regid
value to disable the input.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 10 Aug 2018 14:39:08 +0000 (10:39 -0400)]
freedreno/ir3: create all inputs in first block
create_input()/create_input_compmask() should take the ctx as arg,
rather than block, to enforce that all inputs are created in the first
block, so that RA sees them as live at the start of the shader.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 10 Aug 2018 13:50:14 +0000 (09:50 -0400)]
freedreno/ir3: rename s/frag_pos/frag_vcoord/g
Make it more clear that this is varying fetch related. Also fixup some
comments. Just cleanup for next patches.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 10 Aug 2018 13:13:47 +0000 (09:13 -0400)]
compiler: add SYSTEM_VALUE_VARYING_COORD
Used internally in freedreno/ir3 for the vec2 value that hw passes to
shader to use as coordinate for bary.f (varying fetch) instruction.
This is not the same as SYSTEM_VALUE_FRAG_COORD.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 10 Aug 2018 12:48:25 +0000 (08:48 -0400)]
freedreno/ir3: move per-generation compiler config
Move it from the compile ctx to the compiler object, before adding
new things for a6xx.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Bas Nieuwenhuizen [Mon, 23 Jul 2018 14:24:02 +0000 (16:24 +0200)]
radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.
Behavior wrt firstInstance got changed, and a divisor of 0 has been
disallowed.
The new version of the ext got published in specification 1.1.81.
Sending to stable since the only known user is DXVK, which needs
this for correctness.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Bas Nieuwenhuizen [Sat, 28 Jul 2018 12:01:42 +0000 (14:01 +0200)]
radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9.
Follow radeonsi.
Fixes:
3665f66ef26 "radv: Add support for ETC2 textures."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Fri, 10 Aug 2018 00:26:19 +0000 (02:26 +0200)]
radv: Fix missing Android platform define.
CC: <mesa-stable@lists.freedesktop.org>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Rob Clark [Mon, 30 Jul 2018 12:38:28 +0000 (08:38 -0400)]
freedreno: move free() into fdN_context_destroy()
Following patches will be doing further cleanup after calling
fd_context_destroy() so it is easier if we move the free() into
the per-gen backend code.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Jonathan Marek [Tue, 24 Jul 2018 12:58:24 +0000 (08:58 -0400)]
freedreno: a2xx: ir2 update
this patch brings a number of changes to ir2:
-ir2 now generates CF clauses as necessary during assembly. this simplifies
fd2_program/fd2_compiler and is necessary to implement optimization passes
-ir2 now has separate vector/scalar instructions. this will make it easier
to implementing scheduling of scalar+vector instructions together. dst_reg
is also now seperate from src registers instead of a single list
-ir2 now implements register allocation. this makes it possible to compile
shaders which have more than 64 TGSI registers
-ir2 now implements the following optimizations: removal of IN/OUT MOV
instructions generated by TGSI and removal of unused instructions when
some exports are disabled
-ir2 now allows full 8-bit index for constants
-ir2_alloc no longer allocates 4 times too many bytes
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Andres Gomez [Tue, 14 Aug 2018 14:06:42 +0000 (17:06 +0300)]
docs: update calendar 18.2.0-rc1 and 18.2.0-rc2 are out
Signed-off-by: Andres Gomez <agomez@igalia.com>
Bas Nieuwenhuizen [Mon, 13 Aug 2018 22:07:57 +0000 (00:07 +0200)]
radv: Add on-demand compilation of built-in shaders.
In environments where we cannot cache, e.g. Android (no homedir),
ChromeOS (readonly rootfs) or sandboxes (cannot open cache), the
startup cost of creating a device in radv is rather high, due
to compiling all possible built-in pipelines up front. This meant
depending on the CPU a 1-4 sec cost of creating a Device.
For CTS this cost is unacceptable, and likely for starting random
apps too.
So if there is no cache, with this patch radv will compile shaders
on demand. Once there is a cache from the first run, even if
incomplete, the driver knows that it can likely write the cache
and precompiles everything.
Note that I did not switch the buffer and itob/btoi compute pipelines
to on-demand, since you cannot really do anything in Vulkan without
them and there are only a few.
This reduces the CTS runtime for the no caches scenario on my
threadripper from 32 minutes to 8 minutes.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sun, 12 Aug 2018 23:29:09 +0000 (01:29 +0200)]
radv: Refactor blit pipeline creation.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 11 Aug 2018 21:26:26 +0000 (23:26 +0200)]
radv: Make fs key exemplars ordered to be a reverse fs_key lookup.
While at it, share the exemplars and account for a non-occurring
fs key.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Aug 2018 05:19:41 +0000 (15:19 +1000)]
virgl: ARB_texture_barrier support
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Dylan Baker [Mon, 13 Aug 2018 17:06:45 +0000 (10:06 -0700)]
docs: update calendar, add news item and link release notes for 18.1.6
Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Dylan Baker [Mon, 13 Aug 2018 16:56:25 +0000 (09:56 -0700)]
docs: Add sha256 sums for 18.1.6
Dylan Baker [Mon, 13 Aug 2018 15:36:16 +0000 (08:36 -0700)]
docs: Add release notes for 18.1.6
Alejandro Piñeiro [Mon, 13 Aug 2018 14:47:11 +0000 (16:47 +0200)]
mesa/glspirv: fix compilation with MSVC
From AppVeyor #8582, it seems that MSVC doesn't like uint, so this
patch replaces it with unsigned.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Eric Engestrom [Mon, 13 Aug 2018 11:10:38 +0000 (12:10 +0100)]
travis: install correct version of mako for each build system
Meson now uses python3, so let's add a block for Autotools, move that
line into the buildsys-specific blocks, and set the correct version for
Meson.
Fixes:
2ee1c86d71bee5ddca2c "meson: Build with Python 3"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Erik Faye-Lund [Sun, 12 Aug 2018 13:24:38 +0000 (15:24 +0200)]
mesa/st/glsl_to_tgsi: fixup copy-paste mistake
This is clearly a copy-paste error; if we validate the reladdr2-pointer,
we don't want to traverse to the reladdr-pointer. Especially since the
check above shows that reladdr could be NULL here.
Noticed by Coverity.
CID:
1438389,
1438390
Fixes:
568bda2f2d3 ("mesa/st/glsl_to_tgsi: Split arrays whose elements are only accessed directly")
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gert Wollny <gw.fossdev@gmail.com>
Neil Roberts [Tue, 31 Jul 2018 13:44:24 +0000 (15:44 +0200)]
i965/nir: Use the nir copy of shader_info to handle gl_PatchVerticesIn
Instead of using the copy of shader_info stored in gl_program, it now
uses the one in nir_shader. This is needed for SPIR-V because the
info.tess.tcs_vertices_out is filled in via _mesa_spirv_to_nir which
happens much later than with a GLSL shader. The copy of shader_data in
gl_program is only updated later via brw_shader_gather_info but that
is too late.
For GLSL this shouldn't create any problems because the nir copy of
the shader_info is immediately copied from the gl_program in
glsl_to_nir.
v2: updated after commit "i965: Combine both gl_PatchVerticesIn
lowering passes." (488972) (Alejandro Piñeiro)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Neil Roberts [Mon, 26 Mar 2018 15:12:41 +0000 (17:12 +0200)]
mesa/glspirv: Set separate_shader on shader_info
The value is copied from the gl_program. If we don’t do this then it
will get reset back to zero in brw_shader_gather_info. This isn’t a
problem for GLSL because in that case the nir_shader is initialised
with a copy of the shader_info from the gl_program.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Iago Toral Quiroga [Tue, 31 Jul 2018 13:37:59 +0000 (15:37 +0200)]
mesa/glspirv: pick off the only entry point we need
This is the same we do for vulkan drivers
This is needed to pass the following CTS test:
KHR-GL45.gl_spirv.spirv_modules_shader_binary_multiple_shader_objects_test
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Alejandro Piñeiro [Wed, 21 Mar 2018 08:05:51 +0000 (09:05 +0100)]
mesa/glspirv: compute double inputs and remap attributes
input locations used by input attributes are not handled in the same
way in OpenGL vs Vulkan. There is a detailed explanation of such
differences on the following commit:
c2acf97fcc9b32eaa9778771282758e5652a8ad4
So with this commit, the same adjustment that is done after
glsl_to_nir, is being done after spirv_to_nir, when it is used on
OpenGL (ARB_gl_spirv).
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Alejandro Piñeiro [Wed, 21 Mar 2018 08:39:32 +0000 (09:39 +0100)]
nir/glsl: make nir_remap_attributes public
As we plan to reuse it for ARB_gl_spirv implementation.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Alejandro Piñeiro [Fri, 13 Jul 2018 10:39:41 +0000 (12:39 +0200)]
nir/lower_samplers: don't assume a deref for both texture and sampler srcs
After commit "nir: Use derefs in nir_lower_samplers"
(
75286c2d083cdbdfb202a93349e567df0441d5f7) assumes one deref for both
the texture and the sampler. However there are cases (on OpenGL, using
ARB_gl_spirv) where SPIR-V is not providing a sampler, like for
texture query levels ops. Although we could make spirv_to_nir to
provide a sampler deref for those cases, it is not really needed, and
wrong from the Vulkan point of view.
This patch fixes the following (borrowed) tests run on SPIR-V mode:
arb_compute_shader/execution/basic-texelFetch.shader_test
arb_gpu_shader5/execution/sampler_array_indexing/fs-simple-texture-size.shader_test
arb_texture_query_levels/execution/fs-baselevel.shader_test
arb_texture_query_levels/execution/fs-maxlevel.shader_test
arb_texture_query_levels/execution/fs-miptree.shader_test
arb_texture_query_levels/execution/fs-nomips.shader_test
arb_texture_query_levels/execution/vs-baselevel.shader_test
arb_texture_query_levels/execution/vs-maxlevel.shader_test
arb_texture_query_levels/execution/vs-miptree.shader_test
arb_texture_query_levels/execution/vs-nomips.shader_test
glsl-1.30/execution/fs-textureSize-compare.shader_test
v2: merge lower_tex_src_to_offset and calc_sampler_offsets together,
update texture/sampler index and texture_array_size directly on
lower_tex_src_to_offset (Jason)
v3: clarify one comment (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Wed, 8 Aug 2018 11:41:58 +0000 (13:41 +0200)]
nir/linker: take into account hidden uniforms
So they are not exposed through the introspection API.
It is worth to note that the number of hidden uniforms of GLSL linking
vs SPIR-V linking would be somewhat different due the differen order
of the nir lowerings/optimizations.
For example: gl_FbWposYTransform. This is introduced as part of
nir_lower_wpos_ytransform. On GLSL that is executed after the IR-based
linking. So that means that on GLSL the UniformStorage will not
include this uniform. With the SPIR-V linking, that uniform is already
present, but marked as hidden. So it will be included on the
UniformStorage, but as hidden.
One alternative would create a special how_declared for that case, but
seemed an overkill. Using hidden should be ok as far as it is used
properly.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Alejandro Piñeiro [Tue, 8 May 2018 06:58:59 +0000 (08:58 +0200)]
nir: add how_declared to nir_variable.data
Equivalent to the already existing how_declared at GLSL IR. The only
difference is that we are not adding all the declaration_type
available on GLSL, only the one that we will use on the short term. We
would add more mode if needed on the future.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Neil Roberts [Thu, 19 Apr 2018 15:17:41 +0000 (17:17 +0200)]
spirv: Make VertexIndex and VertexId both non-zero-based
GLSL has gl_VertexID which is supposed to be non-zero-based.
SPIR-V has both VertexIndex and VertexId builtins whose meanings are
defined by the APIs.
Vulkan defines VertexIndex as being non-zero-based. In Vulkan VertexId
and InstanceId have no meaning and are pretty much just reserved for
OpenGL at this point.
GL_ARB_spirv removes VertexIndex and defines VertexId to be the same
as gl_VertexId (which is also non-zero-based).
Previously in Mesa it was treating VertexIndex as non-zero-based and
VertexId as zero-based, so it was breaking for GL. This behaviour was
apparently based on Khronos bug 14255. However that bug doesn’t seem
to have made a final decision for VertexId.
Assuming there really is no other definition for VertexId for Vulkan
it seems better to just make them both have the same value.
v2: update comment and commit descriptions, based on Jason Ekstrand
explanation of the meaning/rationale behind all those builtins
(Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Mon, 23 Oct 2017 15:19:34 +0000 (17:19 +0200)]
spirv: fill info.gs.input_primitive too
info.gs.output_primitive was already being filled. Not sure why this
is not needed on Vulkan, but we found to be needed for
ARB_gl_spirv. Specifically, this is needed to get the following test
passing:
KHR-GL45.gl_spirv.spirv_validation_builtin_variable_decorations_test
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tapani Pälli [Mon, 13 Aug 2018 10:08:22 +0000 (13:08 +0300)]
docs/features: mark GL_EXT_render_snorm as done for i965
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Tapani Pälli [Thu, 14 Jun 2018 10:06:33 +0000 (13:06 +0300)]
i965: enable EXT_render_snorm
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tapani Pälli [Thu, 24 May 2018 11:05:27 +0000 (14:05 +0300)]
mesa: enable EXT_render_snorm extension
Patch sets additional formats renderable and enables the extension
when OpenGL ES 3.1 is supported.
v2: instead of dummy_true, have a separate toggle for extension
(Eric Anholt)
v3: add missing checks, simplify some existing checks and fix
glCopyTexImage2D check (Nanley Chery)
add SHORT and BYTE support in read_pixels_es3_error_check
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Kenneth Graunke [Fri, 10 Aug 2018 06:28:24 +0000 (23:28 -0700)]
blorp: Properly handle Z24X8 blits.
One of the reasons we didn't notice that R24_UNORM_X8_TYPELESS
destinations were broken was that an earlier layer was swapping it
out for B8G8R8A8_UNORM. That made Z24X8 -> Z24X8 blits work.
However, R32_FLOAT -> R24_UNORM_X8_TYPELESS was still totally broken.
The old code only considered one format at a time, without thinking
that format conversion may need to occur.
This patch moves the translation out to a place where it can consider
both formats. If both are Z24X8, we continue using B8G8R8A8_UNORM to
avoid having to do shader math workarounds. If we have a Z24X8
destination, but a non-matching source, we use our shader hacks to
actually render to it properly.
Fixes:
804856fa5735164cc0733ad0ea62adad39b00ae2 (intel/blorp: Handle more exotic destination formats)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Fri, 10 Aug 2018 06:11:07 +0000 (23:11 -0700)]
blorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.
The hardware doesn't support rendering to R24_UNORM_X8_TYPELESS, so
Jason decided to fake it with a bit of shader math and R32_UNORM RTs.
The only problem is that R32_UNORM isn't renderable either...so we've
just traded one bad format for another.
This patch makes us use R32_UINT instead.
Fixes:
804856fa5735164cc0733ad0ea62adad39b00ae2 (intel/blorp: Handle more exotic destination formats)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Mon, 23 Jul 2018 15:02:46 +0000 (08:02 -0700)]
intel: Switch the order of the 2x MSAA sample positions
The Vulkan 1.1.82 spec flipped the order to better match D3D.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Gert Wollny [Tue, 5 Jun 2018 20:26:49 +0000 (22:26 +0200)]
mesa/st/tests: Add array life range estimation and renumbering tests
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>