OSDN Git Service
Simon Pilgrim [Wed, 7 Dec 2016 17:21:13 +0000 (17:21 +0000)]
[X86] Add knownbits vector UMAX test
In preparation for demandedelts support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288920
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Simon Pilgrim [Wed, 7 Dec 2016 17:02:41 +0000 (17:02 +0000)]
[X86][SSE] Remove AND -> VZEXT combine
This is now performed more generally by the target shuffle combine code.
Already covered by tests that were originally added in D7666/rL229480 to support combineVectorZext (or VectorZextCombine as it was known then....).
Differential Revision: https://reviews.llvm.org/D27510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288918
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Simon Pilgrim [Wed, 7 Dec 2016 16:28:21 +0000 (16:28 +0000)]
[SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288916
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Simon Pilgrim [Wed, 7 Dec 2016 15:31:12 +0000 (15:31 +0000)]
[SelectionDAG] Removed old knownbits TODO comment. NFCI.
EXTRACT_VECTOR_ELT does support demanded elts if the element index is known and in range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288913
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Simon Pilgrim [Wed, 7 Dec 2016 15:27:18 +0000 (15:27 +0000)]
[X86] Add test to show missed opportunities to calculate knownbits in INSERT_VECTOR_ELT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288912
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Simon Pilgrim [Wed, 7 Dec 2016 15:10:05 +0000 (15:10 +0000)]
[X86][SSE] Fix vpextrd/vpextrq checks
They were testing for the pre-vex versions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288911
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Simon Pilgrim [Wed, 7 Dec 2016 15:06:14 +0000 (15:06 +0000)]
[X86][SSE] Force execution domain of 32-bit extractps/pextrd in the stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288910
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Matthew Simpson [Wed, 7 Dec 2016 15:03:32 +0000 (15:03 +0000)]
[LV] Scalarize operands of predicated instructions
This patch attempts to scalarize the operand expressions of predicated
instructions if they were conditionally executed in the original loop. After
scalarization, the expressions will be sunk inside the blocks created for the
predicated instructions. The transformation essentially performs
un-if-conversion on the operands.
The cost model has been updated to determine if scalarization is profitable. It
compares the cost of a vectorized instruction, assuming it will be
if-converted, to the cost of the scalarized instruction, assuming that the
instructions corresponding to each vector lane will be sunk inside a predicated
block, possibly avoiding execution. If it's more profitable to scalarize the
entire expression tree feeding the predicated instruction, the expression will
be scalarized; otherwise, it will be vectorized. We only consider the cost of
the entire expression to accurately estimate the cost of the required
insertelement and extractelement instructions.
Differential Revision: https://reviews.llvm.org/D26083
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288909
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Benjamin Kramer [Wed, 7 Dec 2016 13:35:11 +0000 (13:35 +0000)]
Try unbreaking the MSVC build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288907
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Simon Pilgrim [Wed, 7 Dec 2016 13:05:04 +0000 (13:05 +0000)]
[X86][SSE] Regenerate test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288906
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Dylan McKay [Wed, 7 Dec 2016 12:34:47 +0000 (12:34 +0000)]
[AVR] Expand 'SELECT_CC' nodes whereever possible
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288905
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Benjamin Kramer [Wed, 7 Dec 2016 12:31:45 +0000 (12:31 +0000)]
[LowerTypeTests] Use the TrailingObjects infrastructure for trailing objects.
Also avoid allocating ~3x as much memory as needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288904
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Andrea Di Biagio [Wed, 7 Dec 2016 12:31:36 +0000 (12:31 +0000)]
When GVN removes a redundant load, it should not modify the debug location of the dominating load.
In the case of a fully redundant load LI dominated by an equivalent load V, GVN
should always preserve the original debug location of V. Otherwise, we risk to
introduce an incorrect stepping.
If V has debug info, then clearly it should not be modified. If V has a null
debugloc, then it is still potentially incorrect to propagate LI's debugloc
because LI may not post-dominate V.
Differential Revision: https://reviews.llvm.org/D27468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288903
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Simon Pilgrim [Wed, 7 Dec 2016 12:10:49 +0000 (12:10 +0000)]
[X86][SSE] Consistently set MOVD/MOVQ load/store/move instructions to integer domain
We are being inconsistent with these instructions (and all their variants.....) with a random mix of them using the default float domain.
Differential Revision: https://reviews.llvm.org/D27419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288902
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Andrea Di Biagio [Wed, 7 Dec 2016 12:01:45 +0000 (12:01 +0000)]
[InlineFunction] Refactor code in function `fixupLineNumbers' as suggested by David in D27462. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288901
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Simon Dardis [Wed, 7 Dec 2016 11:41:23 +0000 (11:41 +0000)]
[mips][rtdyld] Merge code to write relocated values to the section. NFC
Preparation work for implementing N32 support.
Patch By: Daniel Sanders
Reviewers: vkalintiris, atanasyan
Differential Revision: https://reviews.llvm.org/D27460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288900
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Dylan McKay [Wed, 7 Dec 2016 11:21:45 +0000 (11:21 +0000)]
[AVR] Move a pseudo expansion test into a folder
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288899
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Simon Pilgrim [Wed, 7 Dec 2016 11:19:00 +0000 (11:19 +0000)]
[X86][XOP] Fix VPERMIL2 non-constant pool shuffle decoding (PR31296)
The non-constant pool version of DecodeVPERMIL2PMask was not offsetting correctly for the second input. I've updated the code to match the implementation in the constant-pool version.
Annoyingly this bug was hidden for so long as it's tricky to combine to useful variable shuffle masks that don't become constant-pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288898
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Dylan McKay [Wed, 7 Dec 2016 11:08:56 +0000 (11:08 +0000)]
[AVR] Allow loading from stack slots where src and dest registers are identical
Fixes PR 31256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288897
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Andrea Di Biagio [Wed, 7 Dec 2016 10:37:26 +0000 (10:37 +0000)]
[InlineFunction] Do not propagate the callsite debug location to instructions inlined from functions with debug info.
When a function F is inlined, InlineFunction extends the debug location of every
instruction inlined from F by adding an InlinedAt.
However, if an instruction has a 'null' debug location, InlineFunction would
propagate the callsite debug location to it. This behavior existed since
revision 210459.
Revision 210459 was originally committed specifically to workaround the lack of
debug information for instructions inlined from intrinsic functions (which are
usually declared with attributes `__always_inline__, __nodebug__`).
The problem with revision 210459 is that it doesn't make any sort of distinction
between instructions inlined from a 'nodebug' function and instructions which
are inlined from a function built with debug info. This issue may lead to
incorrect stepping in the debugger.
This patch works under the assumption that a nodebug function does not have a
DISubprogram. When a function F is inlined into another function G,
InlineFunction checks if F has debug info associated with it.
For nodebug functions, the InlineFunction logic is unchanged (i.e. it would
still propagate the callsite debugloc to the inlined instructions). Otherwise,
InlineFunction no longer propagates the callsite debug location.
Differential Revision: https://reviews.llvm.org/D27462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288895
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Chandler Carruth [Wed, 7 Dec 2016 10:33:15 +0000 (10:33 +0000)]
[PM] Add some more logging to make it more clear when the CGSCC
infrastrucutre is skipping SCCs and RefSCCs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288894
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Philip Reames [Wed, 7 Dec 2016 04:48:50 +0000 (04:48 +0000)]
Reintroduce a check accidentally removed in 288873 to fix clang bots
I believe this is the cause of the failure, but have not been able to confirm. Note that this is a speculative fix; I'm still waiting for a full build to finish as I synced and ended up doing a clean build which takes 20+ minutes on my machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288886
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Philip Reames [Wed, 7 Dec 2016 04:11:22 +0000 (04:11 +0000)]
Fix a warning introduced in r288874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288884
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Peter Collingbourne [Wed, 7 Dec 2016 03:04:34 +0000 (03:04 +0000)]
LowerTypeTests: Add a test that covers "unsatisfiable" type metadata.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288881
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Tom Stellard [Wed, 7 Dec 2016 02:42:15 +0000 (02:42 +0000)]
AMDGPU : Add S_SETREG instructions to fix fdiv precision issues.
Patch By: Wei Ding
Summary: This patch fixes the fdiv precision issues.
Reviewers: b-sumner, cfang, wdng, arsenm
Subscribers: kzhuravl, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D26424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288879
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Haicheng Wu [Wed, 7 Dec 2016 01:45:04 +0000 (01:45 +0000)]
[AArch64] Correct the check of signed 9-bit imm in isLegalAddressingMode()
In the addressing mode, signed 9-bit imm is [-256, 255], not [-512, 511].
Differential Revision: https://reviews.llvm.org/D27480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288876
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Chandler Carruth [Wed, 7 Dec 2016 01:42:40 +0000 (01:42 +0000)]
[LCG] Add basic verification of the parent set and fix bugs it uncovers.
The existing unittests actually cover this now that we verify things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288875
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Philip Reames [Wed, 7 Dec 2016 01:03:56 +0000 (01:03 +0000)]
[LVI] Remove used return value from markX functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288874
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Philip Reames [Wed, 7 Dec 2016 00:54:21 +0000 (00:54 +0000)]
[LVI] Simplify mergeIn code
Remove the unused return type, use early return, use assignment operator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288873
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Philip Reames [Wed, 7 Dec 2016 00:28:28 +0000 (00:28 +0000)]
[LVI] Simplify obfuscated code
It doesn't matter why something is overdefined if it is...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288871
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Peter Collingbourne [Tue, 6 Dec 2016 23:53:01 +0000 (23:53 +0000)]
IR: Reduce the amount of boilerplate required for a metadata kind. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288867
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Tom Stellard [Tue, 6 Dec 2016 23:52:13 +0000 (23:52 +0000)]
AMDGPU: Add llvm.amdgcn.interp.mov intrinsic
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D26725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288865
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Davide Italiano [Tue, 6 Dec 2016 23:49:58 +0000 (23:49 +0000)]
[llc] Fix -stop-after=consthoist initializing the pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288864
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Matt Arsenault [Tue, 6 Dec 2016 23:18:06 +0000 (23:18 +0000)]
AMDGPU: Fix crash on i16 constant expression
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288861
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Peter Collingbourne [Tue, 6 Dec 2016 23:02:13 +0000 (23:02 +0000)]
LowerTypeTests: Improve performance by optimising type metadata queries.
Requesting metadata for a global is a relatively expensive operation as it
involves a map lookup, but it's one that we need to do relatively frequently in
this pass to collect the list of type metadata nodes associated with a global.
This change improves the performance of type metadata queries by prebuilding
data structures that keep the global together with its list of type metadata,
and changing the pass to use that data structure wherever we were previously
passing global references around.
This change also eliminates some O(N^2) behavior by collecting the list of
globals associated with each type identifier during the first pass over the
list of globals rather than visiting each global to compute that list every
time we add a new type identifier.
Reduces pass runtime on a module containing Chrome's vtables from over 60s
to 0.9s.
Differential Revision: https://reviews.llvm.org/D27484
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288859
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Simon Pilgrim [Tue, 6 Dec 2016 22:50:13 +0000 (22:50 +0000)]
[X86][XOP] Add test case for PR31296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288858
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Eli Friedman [Tue, 6 Dec 2016 22:49:36 +0000 (22:49 +0000)]
[CodeGen] Fix result type for SMULO/UMULO legalization
On some platforms (like MSP430) the second element of the result
structure for SMULO/UMULO may have a shorter type than the one
returned by SetCC. We need to truncate it to the right type, or
else some incorrect code may be generated later on.
This fixes issue https://github.com/rust-lang/rust/issues/37829
Patch by Vadzim Dambrouski!
Differential Revision: https://reviews.llvm.org/D27154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288857
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Matt Arsenault [Tue, 6 Dec 2016 22:29:43 +0000 (22:29 +0000)]
AMDGPU: Fix operand name for v_interp_*
Other VOP instructions call the output vdst
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288856
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Sanjay Patel [Tue, 6 Dec 2016 22:09:52 +0000 (22:09 +0000)]
[InstSimplify] fixed (?) to not mutate icmps
As Eli noted in the post-commit thread for r288833, the use of
swapOperands() may not be allowed in InstSimplify, so I'm
removing those calls here pending further review.
The swap mutates the icmp, and there doesn't appear to be precedent
for instruction mutation in InstSimplify.
I didn't actually have any tests for those cases, so I'm adding
a few here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288855
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Eugene Zelenko [Tue, 6 Dec 2016 22:00:57 +0000 (22:00 +0000)]
[IR] Fix some Clang-tidy modernize-use-equals-delete and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288853
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Tom Stellard [Tue, 6 Dec 2016 21:53:10 +0000 (21:53 +0000)]
AMDGPU/SI: Set correct value for amd_kernel_code_t::kernarg_segment_alignment
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D27416
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288852
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Davide Italiano [Tue, 6 Dec 2016 21:52:47 +0000 (21:52 +0000)]
[BDCE/DebugInfo] Preserve llvm.dbg.value's argument.
BDCE has two phases:
1. It asks SimplifyDemandedBits if all the bits of an instruction are dead, and if so,
replaces all its uses with the constant zero.
2. Then, it asks SimplifyDemandedBits again if the instruction is really dead
(no side effects etc..) and if so, eliminates it.
Now, in 1) if all the bits of an instruction are dead, we may end up replacing a dbg use:
%call = tail call i32 (...) @g() #4, !dbg !15
tail call void @llvm.dbg.value(metadata i32 %call, i64 0, metadata !8, metadata !16), !dbg !17
->
%call = tail call i32 (...) @g() #4, !dbg !15
tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !8, metadata !16), !dbg !17
but not eliminating the call because it may have arbitrary side effects.
In other words, we lose some debug informations.
This patch fixes the problem making sure that BDCE does nothing with the instruction if
it has side effects and no non-dbg uses.
Differential Revision: https://reviews.llvm.org/D27471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288851
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Tom Stellard [Tue, 6 Dec 2016 21:13:30 +0000 (21:13 +0000)]
AMDGPU/SI: Don't move copies of immediates to the VALU
Summary:
If we write an immediate to a VGPR and then copy the VGPR to an
SGPR, we can replace the copy with a S_MOV_B32 sgpr, imm, rather than
moving the copy to the SALU.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D27272
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288849
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Tim Northover [Tue, 6 Dec 2016 21:02:19 +0000 (21:02 +0000)]
GlobalISel: correctly handle small args via memory.
We were rounding size in bits down rather than up, leading to 0-sized slots for
i1 (assert!) and bugs for other types not byte-aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288848
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Zvi Rackover [Tue, 6 Dec 2016 19:35:20 +0000 (19:35 +0000)]
[X86] Prefer reduced width multiplication over pmulld on Silvermont
Summary:
Prefer expansions such as: pmullw,pmulhw,unpacklwd,unpackhwd over pmulld.
On Silvermont [source: Optimization Reference Manual]:
PMULLD has a throughput of 1/11 [instruction/cycles].
PMULHUW/PMULHW/PMULLW have a throughput of 1/2 [instruction/cycles].
Fixes pr31202.
Analysis of this issue was done by Fahana Aleen.
Reviewers: wmi, delena, mkuper
Subscribers: RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D27203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288844
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Simon Pilgrim [Tue, 6 Dec 2016 19:09:37 +0000 (19:09 +0000)]
[DAGCombine] Add (sext_in_reg (zext x)) -> (sext x) combine
Handle the case where a sign extension has ended up being split into separate stages (typically to get around vector legal ops) and a zext + sext_in_reg gets inserted.
Differential Revision: https://reviews.llvm.org/D27461
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288842
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Sanjay Patel [Tue, 6 Dec 2016 19:05:46 +0000 (19:05 +0000)]
[InstSimplify] add folds for and-of-icmps with same operands
All of these (and a few more) are already handled by InstCombine,
but we shouldn't have to wait until then to simplify these because
they're cheap to deal with here in InstSimplify.
This is the 'and' sibling of the earlier 'or' patch:
https://reviews.llvm.org/rL288833
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288841
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Tim Northover [Tue, 6 Dec 2016 19:02:15 +0000 (19:02 +0000)]
GlobalISel: fall back gracefully when we hit unhandled legalizer default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288840
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Simon Pilgrim [Tue, 6 Dec 2016 18:58:25 +0000 (18:58 +0000)]
[SelectionDAG] We can ignore knownbits from an undef shuffle vector index if we don't actually demand that element
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288839
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Sanjay Patel [Tue, 6 Dec 2016 18:46:54 +0000 (18:46 +0000)]
[InstSimplify] add tests for and-of-icmps; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288837
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Tim Northover [Tue, 6 Dec 2016 18:38:38 +0000 (18:38 +0000)]
GlobalISel: handle G_SEQUENCE fallbacks gracefully.
There were two problems:
+ AArch64 was reusing random data from its binary op tables, which is
complete nonsense for G_SEQUENCE.
+ Even when AArch64 gave up and said it couldn't handle G_SEQUENCE,
the generic code asserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288836
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Tim Northover [Tue, 6 Dec 2016 18:38:34 +0000 (18:38 +0000)]
GlobalISel: allow G_SELECT instructions for pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288835
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Tim Northover [Tue, 6 Dec 2016 18:38:29 +0000 (18:38 +0000)]
GlobalISel: stop the legalizer from trying to handle oddly-sized types.
It'll almost immediately fail because it always tries to half/double the size
until it finds a legal one. Unfortunately, this triggers an assertion
preventing the DAG fallback from being possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288834
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Sanjay Patel [Tue, 6 Dec 2016 18:09:37 +0000 (18:09 +0000)]
[InstSimplify] add folds for or-of-icmps with same operands
All of these (and a few more) are already handled by InstCombine,
but we shouldn't have to wait until then to simplify these because
they're cheap to deal with here in InstSimplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288833
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George Rimar [Tue, 6 Dec 2016 17:55:52 +0000 (17:55 +0000)]
[llvm-readobj] - Teach readobj to print PT_OPENBSD_BOOTDATA header
These are OpenBSD specific program headers.
OpenBSD commit:
https://github.com/openbsd/src/commit/
d39116912b9536bd77326260dc5c6e593fd4ee24
It is required for fixing PR31288.
Differential revision: https://reviews.llvm.org/D27456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288831
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Sanjay Patel [Tue, 6 Dec 2016 17:49:10 +0000 (17:49 +0000)]
[InstSimplify] add tests for or-of-icmps; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288830
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Chris Bieneman [Tue, 6 Dec 2016 17:09:29 +0000 (17:09 +0000)]
[CMake] Fixing clang standalone build
I broke this in r288770.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288829
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Simon Pilgrim [Tue, 6 Dec 2016 17:00:47 +0000 (17:00 +0000)]
[X86][SSE] Add knownbits test demonstrating demandedelts not ignoring undef shuffle elements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288825
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Simon Pilgrim [Tue, 6 Dec 2016 15:57:26 +0000 (15:57 +0000)]
[X86][SSE] Added vector sext_in_reg combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288819
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George Rimar [Tue, 6 Dec 2016 15:40:02 +0000 (15:40 +0000)]
Removed trailing whitespaces. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288817
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George Rimar [Tue, 6 Dec 2016 15:38:15 +0000 (15:38 +0000)]
[Support/ELF] - Add OpenBSD PT_OPENBSD_BOOTDATA constant.
OpenBSD commit for reference:
https://github.com/openbsd/src/commit/
d39116912b9536bd77326260dc5c6e593fd4ee24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288816
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Simon Pilgrim [Tue, 6 Dec 2016 15:17:50 +0000 (15:17 +0000)]
[X86] Improve UMAX/UMIN knownbits test
Test the sequential effect of each op
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288815
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Simon Pilgrim [Tue, 6 Dec 2016 14:50:09 +0000 (14:50 +0000)]
Avoid repeated calls to Op.getOpcode(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288814
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Daniel Sanders [Tue, 6 Dec 2016 14:39:57 +0000 (14:39 +0000)]
[globalisel][aarch64] Fix unintended assumptions about PartialMappingIdx. NFC.
Summary:
This is NFC but prevents assertions when PartialMappingIdx is tablegen-erated.
The assumptions were:
1) FirstGPR is 0
2) FirstGPR is the first of the First* enumerators.
GPR32 is changed to 1 to demonstrate that assumption #1 is fixed. #2 will
be covered by a subsequent patch that tablegen-erates information and swaps
the order of GPR and FPR as a side effect.
Depends on D27336
Reviewers: ab, t.p.northover, qcolombet
Subscribers: aemerson, rengolin, vkalintiris, dberris, rovka, llvm-commits
Differential Revision: https://reviews.llvm.org/D27337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288812
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Daniel Sanders [Tue, 6 Dec 2016 13:55:01 +0000 (13:55 +0000)]
[globalisel][aarch64] Replace magic numbers with corresponding enumerators in ValMappings. NFC
Reviewers: ab, t.p.northover, qcolombet
Subscribers: aemerson, rengolin, vkalintiris, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288810
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Daniel Sanders [Tue, 6 Dec 2016 13:48:58 +0000 (13:48 +0000)]
[globalisel][aarch64] Correct argument names in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288809
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Simon Pilgrim [Tue, 6 Dec 2016 13:29:55 +0000 (13:29 +0000)]
[SLPVectorizer][X86] Tests to show missed buildvector sitofp/fptosi vectorizations
e.g.
buildvector(sitofp(i32), sitofp(i32), sitofp(i32), sitofp(i32)) --> sitofp(buildvector(i32, i32, i32, i32))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288807
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Oliver Stannard [Tue, 6 Dec 2016 12:59:08 +0000 (12:59 +0000)]
[ARM] Better error message for invalid flag-preserving Thumb1 insts
When we see a non flag-setting instruction for which only the flag-setting
version is available in Thumb1, we should give a better error message than
"invalid instruction".
Differential Revision: https://reviews.llvm.org/D27414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288805
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Ayman Musa [Tue, 6 Dec 2016 12:24:14 +0000 (12:24 +0000)]
[X86][AVX512] Detect repeated constant patterns in BUILD_VECTOR suitable for broadcasting.
Check if a build_vector node includes a repeated constant pattern and replace it with a broadcast of that pattern.
For example:
"build_vector <0, 1, 2, 3, 0, 1, 2, 3>" would be replaced by "broadcast <0, 1, 2, 3>"
Differential Revision: https://reviews.llvm.org/D26802
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288804
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Simon Pilgrim [Tue, 6 Dec 2016 12:12:20 +0000 (12:12 +0000)]
[X86] Add tests to show missed opportunities to calculate knownbits in SMAX/SMIN/UMAX/UMIN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288801
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Nemanja Ivanovic [Tue, 6 Dec 2016 11:47:14 +0000 (11:47 +0000)]
[PowerPC] Improvements for BUILD_VECTOR Vol. 4
This is the final patch in the series of patches that improves
BUILD_VECTOR handling on PowerPC. This adds a few peephole optimizations
to remove redundant instructions. It also adds a large test case which
encompasses a large set of code patterns that build vectors - this test
case was the motivator for this series of patches.
Differential Revision: https://reviews.llvm.org/D26066
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288800
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Daniel Sanders [Tue, 6 Dec 2016 11:33:04 +0000 (11:33 +0000)]
[globalisel][aarch64] Prefix PartialMappingIdx enumerators with 'PMI_' to fit coding standards.
This also stops things like 'None' polluting the llvm::AArch64 namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288799
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Simon Pilgrim [Tue, 6 Dec 2016 11:27:19 +0000 (11:27 +0000)]
Fix MSVC -Wmicrosoft-enum-value 'enumerator value is not representable' warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288798
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Simon Pilgrim [Tue, 6 Dec 2016 11:12:53 +0000 (11:12 +0000)]
Fix MSVC bool to uint64_t promotion warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288796
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Chandler Carruth [Tue, 6 Dec 2016 10:29:23 +0000 (10:29 +0000)]
[LCG] Add some much needed asserts and verify runs to uncover
a hilarious bug and fix it.
We somehow were never verifying the RefSCCs newly formed when
splitting an existing one apart, and when verifying them we weren't
really checking the SCC indices mapping effectively.
If we had been, it would have been blindingly obvious that right after
putting something int `RC.SCCs` we should update `RC.SCCIndices` instead
of `SCCIndices` which we were about to clear and rebuild anyways. =[
Anyways, this is thoroughly covered by existing tests now that we
actually verify things properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288795
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Florian Hahn [Tue, 6 Dec 2016 10:24:55 +0000 (10:24 +0000)]
[framelowering] Improve tracking of first CS pop instruction.
Summary: This patch makes sure FirstCSPop and MBBI never point to DBG_VALUE instructions, which affected the code generated.
Reviewers: mkuper, aprantl, MatzeB
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288794
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Sam McCall [Tue, 6 Dec 2016 10:14:36 +0000 (10:14 +0000)]
Add missing parens in assert.
Summary: Add missing parens in assert, which warn in GCC.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288792
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Chandler Carruth [Tue, 6 Dec 2016 10:06:06 +0000 (10:06 +0000)]
[PM] Basic cleanups to CGSCC update code, NFC.
Just using InstIterator, simpler loop structures, and making better use
of the visit callback infrastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288790
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Craig Topper [Tue, 6 Dec 2016 08:08:12 +0000 (08:08 +0000)]
[X86] Remove another weird scalar sqrt/rcp/rsqrt pattern.
This pattern turned a vector sqrt/rcp/rsqrt operation of sse_load_f32/f64 into the the scalar instruction for the operation and put undef into the upper bits. For correctness, the resulting code should still perform the sqrt/rcp/rsqrt on the upper bits after the load is extended since that's what the operation asked for. Particularly in the case where the upper bits are 0, in that case we need calculate the sqrt/rcp/rsqrt of the zeroes and keep the result in the upper-bits. This implies we should be using the packed instruction still.
The only test case for this pattern is one I just added so there was no coverage of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288784
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Craig Topper [Tue, 6 Dec 2016 08:08:09 +0000 (08:08 +0000)]
[X86] Add test case demonstrating a case where a vector sqrt being passed (scalar_to_vector loadf64) uses a scalar sqrt instruction.
This occurs due to a pattern that uses sse_load_f32/f64 with vector sqrt/rcp/rsqrt operations and turns them into scalar instructions. Perhaps for the case were the upper bits come from undef this is ok. I believe a (vzmovl load64) would do the same thing but those seems to become vzload instead and selectScalarSSELoad doesn't handle that today. In that case we should be performing the vector operation on the zeros in the upper bits which is not equivalent to using a scalar instruction.
I will remove this pattern in a follow up patch. There appears to be no other test content for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288783
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Craig Topper [Tue, 6 Dec 2016 08:08:07 +0000 (08:08 +0000)]
[X86] Regenerate a test using update_llc_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288782
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Craig Topper [Tue, 6 Dec 2016 08:08:04 +0000 (08:08 +0000)]
[X86] Remove bad pattern that caused 128-bit loads being used by scalar sqrt/rcp/rsqrt intrinsics to select the memory form of the corresponding instruction and violate the semantics of the intrinsic.
The intrinsics are supposed to pass the upper bits straight through to their output register. This means we need to make sure we still perform the 128-bit load to get those upper bits to pass to give to the instruction since the memory form of the instruction only reads 32 or 64 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288781
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Craig Topper [Tue, 6 Dec 2016 08:08:01 +0000 (08:08 +0000)]
[X86] Add test case that shows a scalar sqrtsd intrinsic of a 128-bit vector load using the load form of the sqrtsd instruction which violates the intrinsic semantics.
The sqrtsd instruction only loads 64-bits and writes bits 63:0 with the sqrt result. Bits 127:64 are preserved in the destination register. The semantics of the intrinsic indicate bits 127:64 should come from the intrinsic argument which in this case is a 128-bit load. So the generated code should have a 128-bit load and use a register form of sqrtsd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288780
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Craig Topper [Tue, 6 Dec 2016 08:07:58 +0000 (08:07 +0000)]
[X86] Correct pattern for VSQRTSSr_Int, VSQRTSDr_Int, VRCPSSr_Int, and VRSQRTSSr_Int to not have an IMPLICIT_DEF on the first input. The semantics of the intrinsic are clear and not undefined.
The intrinsic takes one argument, the lower bits are affected by the operation and the upper bits should be passed through. The instruction itself takes two operands, the high bits of the first operand are passed through and the low bits of the second operand are modified by the operation. To match this to the intrinsic we should pass the single intrinsic input to both operands.
I had to remove the stack folding test for these instructions since they depended on the incorrect behavior. The same register is now used for both inputs so the load can't be folded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288779
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Chris Bieneman [Tue, 6 Dec 2016 06:00:49 +0000 (06:00 +0000)]
[ObjectYAML] First bit of support for encoding DWARF in MachO
This patch adds the starting support for encoding data from the MachO __DWARF segment. The first section supported is the __debug_str section because it is the simplest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288774
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Craig Topper [Tue, 6 Dec 2016 04:58:39 +0000 (04:58 +0000)]
[X86] Remove scalar logical op alias instructions. Just use COPY_FROM/TO_REGCLASS and the normal packed instructions instead
Summary:
This patch removes the scalar logical operation alias instructions. We can just use reg class copies and use the normal packed instructions instead. This removes the need for putting these instructions in the execution domain fixing tables as was done recently.
I removed the loadf64_128 and loadf32_128 patterns as DAG combine creates a narrower load for (extractelt (loadv4f32)) before we ever get to isel.
I plan to add similar patterns for AVX512DQ in a future commit to allow use of the larger register class when available.
Reviewers: spatel, delena, zvi, RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27401
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288771
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Chris Bieneman [Tue, 6 Dec 2016 04:45:11 +0000 (04:45 +0000)]
[CMake] Cleanup TableGen include flags
It is kinda crazy to have llvm/include and llvm/lib/Target in the include path for every tablegen invocation for every tablegen-like tool.
This patch removes those flags from the tablgen function that is called everywhere by instead creating a variable LLVM_TABLEGEN_FLAGS which is setup in the LLVM source directories.
This removes TableGen.cmake's dependency on LLVM_MAIN_SRC_DIR, and LLVM_MAIN_INCLUDE_DIR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288770
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Philip Reames [Tue, 6 Dec 2016 03:34:33 +0000 (03:34 +0000)]
[LVI] Remove dead code in mergeIn
Integers are expressed in the lattice via constant ranges. They can never be represented by constants or not-constants; those are reserved for non-integer types. This code has been dead for literaly years.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288767
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Philip Reames [Tue, 6 Dec 2016 03:22:03 +0000 (03:22 +0000)]
[LVI] Extract a helper function
Extracting a helper function out of solveBlockValue makes the contract around the cache much easier to understand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288766
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Philip Reames [Tue, 6 Dec 2016 03:01:08 +0000 (03:01 +0000)]
[LVI] Hide the last markX function on LVILatticeVal
This completes a small series of patches to hide the stateful updates of LVILatticeVal from the consuming code. The only remaining stateful API is mergeIn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288765
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Philip Reames [Tue, 6 Dec 2016 02:54:16 +0000 (02:54 +0000)]
[LVI] Hide a confusing internal interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288764
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Mandeep Singh Grang [Tue, 6 Dec 2016 02:49:17 +0000 (02:49 +0000)]
[llvm] Fix D26214: Move error handling out of MC and to the callers.
Summary: Related clang patch; https://reviews.llvm.org/D27360
Reviewers: t.p.northover, grosbach, compnerd, echristo
Subscribers: compnerd, mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D27359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288763
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Philip Reames [Tue, 6 Dec 2016 02:36:58 +0000 (02:36 +0000)]
[LVI] Remove duplicate code using existing helper function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288761
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Davide Italiano [Tue, 6 Dec 2016 02:26:50 +0000 (02:26 +0000)]
Revert "[SCCP] Remove manual folding of terminator instructions."
This reverts commit r288725 as it broke a bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288759
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Zijiao Ma [Tue, 6 Dec 2016 02:22:08 +0000 (02:22 +0000)]
Refactor TargetParserTests.
The TargetParser tests are a bit redundant. Refactor them in a more
repeatable way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288758
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Mehdi Amini [Tue, 6 Dec 2016 01:23:04 +0000 (01:23 +0000)]
Introduces cmake option `LLVM_DISABLE_ABI_BREAKING_CHECKS_ENFORCING`
Summary:
We recently introduced a feature that enforce at link-time that the
LLVM headers used by a clients are matching the ABI setting of the
LLVM library linked to.
However for clients that are using only headers from ADT and promise
they won't call into LLVM, this is forcing to link libSupport. This
new flag is intended to provide a way to configure LLVM with this
promise for such client.
Reviewers: bob.wilson, compnerd
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D27432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288754
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Matt Arsenault [Tue, 6 Dec 2016 01:02:51 +0000 (01:02 +0000)]
AMDGPU: Don't required structured CFG
The structured CFG is just an aid to inserting exec
mask modification instructions, once that is done
we don't really need it anymore. We also
do not analyze blocks with terminators that
modify exec, so this should only be impacting
true branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288744
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Bob Haarman [Tue, 6 Dec 2016 00:55:55 +0000 (00:55 +0000)]
revert inadvertedly introduced build break
Summary:
r288722 introduced a build break due some code that should
not have been part of the commit. This change removes the offending
code.
Reviewers: davide, ruiu
Differential Revision: https://reviews.llvm.org/D27435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288742
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Weiming Zhao [Mon, 5 Dec 2016 23:55:13 +0000 (23:55 +0000)]
Summary: Currently there is no way to disable deprecated warning from asm like this
clang -target arm deprecated-asm.s -c
deprecated-asm.s:30:9: warning: use of SP or PC in the list is deprecated
stmia r4!, {r12-r14}
We have to have an option what can disable it.
Patched by Yin Ma!
Reviewers: joey, echristo, weimingz
Subscribers: llvm-commits, aemerson
Differential Revision: https://reviews.llvm.org/D27219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288734
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Kostya Serebryany [Mon, 5 Dec 2016 23:35:22 +0000 (23:35 +0000)]
[libFuzzer] refactor the code to allow collecting features in different ways. Also initialize a couple of Fuzzer:: members that might have been used uninitialized :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288731
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