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Simon Pilgrim [Mon, 16 Oct 2017 21:55:09 +0000 (21:55 +0000)]
[X86][3DNow] Add scheduling latency/throughput tests for 3DNow! instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315942
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Craig Topper [Mon, 16 Oct 2017 21:54:13 +0000 (21:54 +0000)]
[JumpThreading] Move two PredValueInfoTy vectors to a scope closer to their usage. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315941
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Eugene Zelenko [Mon, 16 Oct 2017 21:34:24 +0000 (21:34 +0000)]
[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315940
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Simon Pilgrim [Mon, 16 Oct 2017 21:29:29 +0000 (21:29 +0000)]
[X86][MMX] Add scheduling latency/throughput tests for MMX instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315939
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Krzysztof Parzyszek [Mon, 16 Oct 2017 21:19:40 +0000 (21:19 +0000)]
Replace make_range in MachineRegisterInfo with ArrayRef, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315938
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Vitaly Buka [Mon, 16 Oct 2017 20:48:19 +0000 (20:48 +0000)]
[libFuzzer] Delete llvm/lib/Fuzzer
Summary: Code is already in compiler-rt
Reviewers: kcc
Subscribers: krytarowski, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D38912
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315937
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Tony Tye [Mon, 16 Oct 2017 20:44:29 +0000 (20:44 +0000)]
Add base relative relocation record that can be used for the following case (OpenCL example):
static __global int Var = 0;
__global int* Ptr[] = {&Var};
...
In this case Var is a non premptable symbol and so its address can be used as the value of Ptr, with a base relative relocation that will add the delta between the ELF address and the actual load address. Such relocations do not require a symbol.
Differential Revision: https://reviews.llvm.org/D38909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315935
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Kostya Serebryany [Mon, 16 Oct 2017 20:36:57 +0000 (20:36 +0000)]
fix llvm-isel-fuzzer: LLVMFuzzerTestOneInput should never return non-zero (according to the contract)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315933
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Reid Kleckner [Mon, 16 Oct 2017 20:31:16 +0000 (20:31 +0000)]
Revert MSVC 2017 build fix and fix it by moving the method that implicitly instantiates addPredicate out of line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315932
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Reid Kleckner [Mon, 16 Oct 2017 20:23:16 +0000 (20:23 +0000)]
Fix the build of GlobalISelEmitter with MSVC 2017 by specializing earlier
MSVC doesn't seem to like implicitly instantiating addPredicate and then
explicitly specializing it later. It causes an internal compiler error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315930
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Krzysztof Parzyszek [Mon, 16 Oct 2017 19:08:41 +0000 (19:08 +0000)]
Add iterator range MachineRegisterInfo::liveins(), adopt users, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315927
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Krzysztof Parzyszek [Mon, 16 Oct 2017 18:43:08 +0000 (18:43 +0000)]
[Hexagon] Rangify some loops, NFC
Recommit r315763 with a fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315925
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Anna Thomas [Mon, 16 Oct 2017 17:47:17 +0000 (17:47 +0000)]
[SCEV] Rename getMaxBECount and update comments. NFC
Post commit review comments at D38825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315920
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Matthew Simpson [Mon, 16 Oct 2017 17:44:17 +0000 (17:44 +0000)]
[SparsePropagation] Enable interprocedural analysis
This patch adds the ability to perform IPSCCP-like interprocedural analysis to
the generic sparse propagation solver. The patch gives clients the ability to
define their own custom LatticeKey types that the generic solver maps to custom
LatticeVal types. The custom lattice keys can be used, for example, to
distinguish among mappings for regular values, values returned from functions,
and values stored in global variables. Clients are responsible for defining how
to convert between LatticeKeys and LLVM Values by providing a specialization of
the LatticeKeyInfo template.
The added unit tests demonstrate how the generic solver can be used to perform
a simplified version of interprocedural constant propagation.
Differential Revision: https://reviews.llvm.org/D37353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315919
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Alexander Timofeev [Mon, 16 Oct 2017 16:57:37 +0000 (16:57 +0000)]
[AMDGPU] : revert r315908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315916
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Akira Hatanaka [Mon, 16 Oct 2017 16:46:59 +0000 (16:46 +0000)]
[ObjCARC] Do not move a release that has the clang.imprecise_release tag
above PHI instructions.
ARC optimizer has an optimization that moves a call to an ObjC runtime
function above a phi instruction when the phi has a null operand and is
an argument passed to the function call. This optimization should not
kick in when the runtime function is an objc_release that releases an
object with precise lifetime semantics.
rdar://problem/
34959669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315914
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Sanjay Patel [Mon, 16 Oct 2017 15:20:00 +0000 (15:20 +0000)]
[x86] add minmax tests with more predicate coverage; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315913
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Javed Absar [Mon, 16 Oct 2017 14:52:26 +0000 (14:52 +0000)]
[TableGen] Simplify CallingConvEmitter.cpp. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315911
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Sanjay Patel [Mon, 16 Oct 2017 14:47:24 +0000 (14:47 +0000)]
[InstCombine] don't unnecessarily generate a constant; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315910
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Sanjay Patel [Mon, 16 Oct 2017 14:46:37 +0000 (14:46 +0000)]
[ValueTracking] fix typos, formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315909
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Alexander Timofeev [Mon, 16 Oct 2017 14:35:29 +0000 (14:35 +0000)]
[AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the dead one
Differential revision: https://reviews.llvm.org/D38754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315908
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Simon Pilgrim [Mon, 16 Oct 2017 14:33:51 +0000 (14:33 +0000)]
Fix test name typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315907
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Simon Pilgrim [Mon, 16 Oct 2017 14:32:41 +0000 (14:32 +0000)]
[X86][SSE] Added additional PACKUS shuffle tests
Mainly inspired by PR34773
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315906
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Simon Dardis [Mon, 16 Oct 2017 14:20:22 +0000 (14:20 +0000)]
[mips][micromips] Fix (dis)assembly of bc1(t|f)
Previously these instructions were marked codegen only and had
an under-specified instruction description that did not record the
fcc register.
Reviewers: atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D38847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315905
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Sjoerd Meijer [Mon, 16 Oct 2017 14:07:30 +0000 (14:07 +0000)]
ISel type legalizer: debug messages. NFC.
Minor addition and follow up of r314773 and r311533: this adds more
debug messages to the type legalizer. For each node, it dumps
legalization info for results and operands nodes, rather than just the
final legalized node.
Differential Revision: https://reviews.llvm.org/D38726
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315904
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Simon Pilgrim [Mon, 16 Oct 2017 14:01:59 +0000 (14:01 +0000)]
Fix or vs || typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315903
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Stefan Maksimovic [Mon, 16 Oct 2017 13:18:21 +0000 (13:18 +0000)]
[mips] Provide alternate predicates for constant synthesis
Ordering of patterns should not be of importance anymore
since the predicates used are mutually exclusive now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315901
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Hiroshi Inoue [Mon, 16 Oct 2017 12:11:15 +0000 (12:11 +0000)]
[PowerPC] fix up in sign-/zero-extension elimination
This patch fixes a potential problem in my previous commit (https://reviews.llvm.org/rL315888) by adding a null check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315900
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Andrew V. Tischenko [Mon, 16 Oct 2017 11:14:29 +0000 (11:14 +0000)]
This patch is a result of D37262: The issues with X86 prefixes. It closes PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315899
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George Rimar [Mon, 16 Oct 2017 10:26:17 +0000 (10:26 +0000)]
[llvm-dwarfdump] - Teach tool to parse DW_CFA_GNU_args_size.
Currently llvm-dwarfdump runs into llvm_unreachable when
faces DW_CFA_GNU_args_size. Patch implements the support.
Differential revision: https://reviews.llvm.org/D38879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315897
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NAKAMURA Takumi [Mon, 16 Oct 2017 09:50:01 +0000 (09:50 +0000)]
Revert rL315894, "SLPVectorizer.cpp: Try to appease stage2-3 difference. (D38586)"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315896
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Nikolai Bozhenov [Mon, 16 Oct 2017 09:19:21 +0000 (09:19 +0000)]
Move folding of icmp with zero after checking for min/max idioms.
Summary:
The following transformation for cmp instruction:
icmp smin(x, PositiveValue), 0 -> icmp x, 0
should only be done after checking for min/max to prevent infinite
looping caused by a reverse canonicalization. That is why this
transformation was moved to place after the mentioned check.
Reviewers: spatel, efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38934
Patch by: Artur Gainullin <artur.gainullin@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315895
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NAKAMURA Takumi [Mon, 16 Oct 2017 09:15:23 +0000 (09:15 +0000)]
SLPVectorizer.cpp: Try to appease stage2-3 difference. (D38586)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315894
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Javed Absar [Mon, 16 Oct 2017 06:43:54 +0000 (06:43 +0000)]
[TableGen] Range loopify DAGISelMatcher. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315891
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Daniel Sanders [Mon, 16 Oct 2017 05:39:30 +0000 (05:39 +0000)]
[aarch64][globalisel] Fix a crash in selectAddrModeIndexed() caused by incorrect G_FRAME_INDEX handling
The wrong operand was being rendered to the result instruction.
The crash was detected by Bitcode/simd_ops/AArch64_halide_runtime.bc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315890
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Yonghong Song [Mon, 16 Oct 2017 04:14:53 +0000 (04:14 +0000)]
bpf: fix bug on silently truncating 64-bit immediate
We came across an llvm bug when compiling some testcases that 64-bit
immediates are silently truncated into 32-bit and then packed into
BPF_JMP | BPF_K encoding. This caused comparison with wrong value.
This bug looks to be introduced by r308080. The Select_Ri pattern is
supposed to be lowered into J*_Ri while the latter only support 32-bit
immediate encoding, therefore Select_Ri should have similar immediate
predicate check as what J*_Ri are doing.
Reported-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315889
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Hiroshi Inoue [Mon, 16 Oct 2017 04:12:57 +0000 (04:12 +0000)]
[PowerPC] Eliminate sign- and zero-extensions if already sign- or zero-extended
This patch enables redundant sign- and zero-extension elimination in PowerPC MI Peephole pass.
If the input value of a sign- or zero-extension is known to be already sign- or zero-extended, the operation is redundant and can be eliminated.
One common case is sign-extensions for a method parameter or for a method return value; they must be sign- or zero-extended as defined in PPC ELF ABI.
For example of the following simple code, two extsw instructions are generated before the invocation of int_func and before the return. With this patch, both extsw are eliminated.
void int_func(int);
void ii_test(int a) {
if (a & 1) return int_func(a);
}
Such redundant sign- or zero-extensions are quite common in many programs; e.g. I observed about 60,000 occurrences of the elimination while compiling the LLVM+CLANG.
Differential Revision: https://reviews.llvm.org/D31319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315888
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Daniel Sanders [Mon, 16 Oct 2017 03:36:29 +0000 (03:36 +0000)]
Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and am_indexed*
Summary:
iPTR is a pointer of subtarget-specific size to any address space. Therefore
type checks on this size derive the SizeInBits from a subtarget hook.
At this point, we can import the simplests G_LOAD rules and select load
instructions using them. Further patches will support for the predicates to
enable additional loads as well as the stores.
The previous commit failed on MSVC due to a failure to convert an
initializer_list to a std::vector. Hopefully, MSVC will accept this version.
Depends on D37457
Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D37458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315887
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Daniel Sanders [Mon, 16 Oct 2017 02:15:39 +0000 (02:15 +0000)]
Revert r315885: [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and am_indexed*
MSVC doesn't like one of the constructors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315886
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Daniel Sanders [Mon, 16 Oct 2017 01:16:35 +0000 (01:16 +0000)]
[globalisel][tblgen] Add support for iPTR and implement am_unscaled* and am_indexed*
Summary:
iPTR is a pointer of subtarget-specific size to any address space. Therefore
type checks on this size derive the SizeInBits from a subtarget hook.
At this point, we can import the simplests G_LOAD rules and select load
instructions using them. Further patches will support for the predicates to
enable additional loads as well as the stores.
Depends on D37457
Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D37458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315885
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Daniel Sanders [Mon, 16 Oct 2017 00:56:30 +0000 (00:56 +0000)]
[globalisel][tablegen] Implement unindexed load, non-extending load, and MemVT checks
Summary:
This includes some context-sensitivity in the MVT to LLT conversion so that
pointer types are tested correctly.
FIXME: I'm not happy with the way this is done since everything is a
special-case. I've yet to find a reasonable way to implement it.
select-load.mir fails because <1 x s64> loads in tablegen get priority over s64
loads. This is fixed in the next patch and as such they should be committed
together, I've posted them separately to help with the review.
Depends on D37456
Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar
Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D37457
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315884
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Krzysztof Parzyszek [Mon, 16 Oct 2017 00:29:47 +0000 (00:29 +0000)]
[Hexagon] Add LLVM_ATTRIBUTE_UNUSED to operator<<, NFC
This should silence "unused function" warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315883
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Nico Weber [Sun, 15 Oct 2017 19:13:57 +0000 (19:13 +0000)]
Search for libxml2 on macOS too.
This allows lld-link to process /manifestinput: flags on macOS too.
Also makes the `REQUIRES: manifesttool` lld tests run on macOS.
Setting LLVM_ENABLE_LIBXML2 to off can suppress this behavior, like on Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315873
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Daniel Sanders [Sun, 15 Oct 2017 19:01:32 +0000 (19:01 +0000)]
[tablegen] Use hasPredCode()/hasImmCode() instead of getPredCode().empty()/getImmCode().empty(). NFC
These are cheaper ways of testing for the presence of code than generating the C++ code and testing it's empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315872
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Krzysztof Parzyszek [Sun, 15 Oct 2017 18:23:16 +0000 (18:23 +0000)]
Phony change to CMakeLists.txt to (hopefully) trigger regeneration
Ninja doesn't seem to recognize a change in a CMakeLists.txt in a
subdirectory, so r315861 is not having any effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315870
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Daniel Sanders [Sun, 15 Oct 2017 18:22:54 +0000 (18:22 +0000)]
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator
Summary:
It's possible for a ComplexPattern to be used as an operator in a match
pattern. This is used by the load/store patterns in AArch64 to name the
suboperands returned by ComplexPattern predicate so that they can be broken
apart and referenced independently in the result pattern.
This patch adds support for this in order to enable the import of load/store
patterns.
Depends on D37445
Hopefully fixed the ambiguous constructor that a large number of bots reported.
Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D37456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315869
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Daniel Sanders [Sun, 15 Oct 2017 17:51:07 +0000 (17:51 +0000)]
Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator
A large number of bots are failing on an ambiguous constructor call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315866
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Daniel Sanders [Sun, 15 Oct 2017 17:03:36 +0000 (17:03 +0000)]
[globalisel][tablegen] Import ComplexPattern when used as an operator
Summary:
It's possible for a ComplexPattern to be used as an operator in a match
pattern. This is used by the load/store patterns in AArch64 to name the
suboperands returned by ComplexPattern predicate so that they can be broken
apart and referenced independently in the result pattern.
This patch adds support for this in order to enable the import of load/store
patterns.
Depends on D37445
Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D37456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315863
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Craig Topper [Sun, 15 Oct 2017 16:57:33 +0000 (16:57 +0000)]
[X86] Remove the SlowBTMem feature flag entirely
Turns out we have no patterns on the instructions that were using this feature flag for other reasons. These instructions are slow on all modern CPUs so it seems unlikely that we will spend any effort supporting these instructions going forward. So we might as well just kill of the feature flag and just fix up the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315862
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Krzysztof Parzyszek [Sun, 15 Oct 2017 16:55:23 +0000 (16:55 +0000)]
[unittests] Only build llvm-cfi-verify if X86 is in LLVM_TARGETS_TO_BUILD
The test requires a target for triple x86-64, and it fails in builds that
do not have the X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315861
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Craig Topper [Sun, 15 Oct 2017 16:41:17 +0000 (16:41 +0000)]
[AVX512] Don't mark EXTLOAD as legal with AVX512. Continue using custom lowering.
Summary:
This was impeding our ability to combine the extending shuffles with other shuffles as you can see from the test changes.
There's one special case that needed to be added to use VZEXT directly for v8i8->v8i64 since the custom lowering requires v64i8.
Reviewers: RKSimon, zvi, delena
Reviewed By: delena
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38714
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315860
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Craig Topper [Sun, 15 Oct 2017 16:41:15 +0000 (16:41 +0000)]
[X86] Add FeatureSlowBTMem to Haswell, Broadwell, Skylake, Cannonlake, and Knights Landing CPUs.
Summary: I see nothing in Agner Fog's tables to indicate that this improved between Ivy Bridge and Haswell. It's also set for all Atom CPUs so I assume KNL should have it too.
Reviewers: RKSimon, zvi, gadi.haber
Reviewed By: gadi.haber
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315859
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Krzysztof Parzyszek [Sun, 15 Oct 2017 15:39:56 +0000 (15:39 +0000)]
[TableGen] Remove error checks incorrectly failing on non-error conditions
In type inference, an empty type set for a specific hw mode is not an
error. In earlier stages of the design it was, but having to use non-
parameterized types with target intrinsics necessarily led to type
contradictions: since the intrinsics used specific types, they were
only valid for a specific hw mode, and the resulting type set for other
modes ended up empty. To accommodate the existence of such intrinsics
individual type sets were allowed to be empty as long as not all sets
were empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315858
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Sanjay Patel [Sun, 15 Oct 2017 15:39:15 +0000 (15:39 +0000)]
revert r314984: revert r314698 - [InstCombine] remove one-use restriction for icmp (shr exact X, C1), C2 --> icmp X, (C2<<C1)
Recommitting r314698. The bug exposed by this change should be fixed with:
https://reviews.llvm.org/rL315579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315857
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Sanjay Patel [Sun, 15 Oct 2017 14:43:39 +0000 (14:43 +0000)]
[SimplifyCFG] use range-for-loops, tidy; NFCI
There seems to be something missing here as shown in PR34471:
https://bugs.llvm.org/show_bug.cgi?id=34471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315855
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Aaron Ballman [Sun, 15 Oct 2017 14:32:27 +0000 (14:32 +0000)]
Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people.
Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315854
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whitequark [Sun, 15 Oct 2017 12:29:09 +0000 (12:29 +0000)]
[MergeFunctions] Merge small functions if possible without a thunk.
This can result in significant code size savings in some cases,
e.g. an interrupt table all filled with the same assembly stub
in a certain Cortex-M BSP results in code blowup by a factor of 2.5.
Differential Revision: https://reviews.llvm.org/D34806
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315853
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whitequark [Sun, 15 Oct 2017 12:29:01 +0000 (12:29 +0000)]
[MergeFunctions] Replace all uses of unnamed_addr functions.
This reduces code size for constructs like vtables or interrupt
tables that refer to functions in global initializers.
Differential Revision: https://reviews.llvm.org/D34805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315852
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Amjad Aboud [Sun, 15 Oct 2017 11:00:56 +0000 (11:00 +0000)]
[X86] Ignore DBG instructions in X86CmovConversion optimization to resolve PR34565
Differential Revision: https://reviews.llvm.org/D38359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315851
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Hongbin Zheng [Sun, 15 Oct 2017 07:31:02 +0000 (07:31 +0000)]
[LoopInfo][Refactor] Make SetLoopAlreadyUnrolled a member function of the Loop Pass, NFC.
This avoid code duplication and allow us to add the disable unroll metadata elsewhere.
Differential Revision: https://reviews.llvm.org/D38928
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315850
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Craig Topper [Sun, 15 Oct 2017 06:39:07 +0000 (06:39 +0000)]
[X86] Lower vselect with constant condition to vector_shuffle even with AVX512 instructions.
Summary:
It's better to use our shuffle lowering code to handle these than loading an immediate into a k-register.
It really feels like this should be a DAG combine optimization rather than a lowering operation, but that's a problem for another day.
Reviewers: RKSimon, delena, zvi
Reviewed By: delena
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38932
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315849
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Craig Topper [Sun, 15 Oct 2017 06:05:50 +0000 (06:05 +0000)]
[X86] Don't use constant condition for select instruction when testing masking ops.
We should be able to fold constant conditions by converting to shuffles, but fixing that would break these tests in their current form. Since they are really trying to test masking ops, add a non-constant mask to the selects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315848
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Vitaly Buka [Sun, 15 Oct 2017 05:35:02 +0000 (05:35 +0000)]
Remove unused variables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315847
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Daniel Sanders [Sun, 15 Oct 2017 02:41:12 +0000 (02:41 +0000)]
[globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFC
Summary:
There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for
ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load
and atomic loads are handled by a separate node. However, this is not true of
GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity
of the operation. As a result, this mapping must also add a predicate that
checks for non-atomic MachineMemOperands.
This is NFC since these nodes always have predicates in practice and are
therefore always rejected at the moment.
Depends on D37443
Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: kristof.beyls, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D37445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315843
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Daniel Sanders [Sun, 15 Oct 2017 02:06:44 +0000 (02:06 +0000)]
[tablegen] Handle common load/store predicates inside tablegen. NFC.
Summary:
GlobalISel and SelectionDAG require different code for the common
load/store predicates due to differences in the representation.
For example:
SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG
GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr))
Even without that, differences in the IR (SDNode vs MachineInstr) require
differences in the C++ predicate.
This patch moves the implementation of the common load/store predicates
into tablegen so that it can handle these differences.
It's NFC for SelectionDAG since it emits equivalent code and it's NFC for
GlobalISel since the rules involving the relevant predicates are still
rejected by the importer.
Depends on D36618
Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar
Subscribers: llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D37443
Includes a partial revert of r315826 since this patch makes it necessary for
getPredCode() to return a std::string and getImmCode() should have the same
interface as getPredCode().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315841
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Davide Italiano [Sat, 14 Oct 2017 23:46:01 +0000 (23:46 +0000)]
[Hexagon] Mark RangeTree::dump() with LLVM_DUMP_METHOD.
GCC otherwise emits a "defined but not used" warning on the
member function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315838
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Konstantin Zhuravlyov [Sat, 14 Oct 2017 23:42:11 +0000 (23:42 +0000)]
AMDGPU: Temporary disable pal metadata check line in llvm-readobj test
It fails on mips
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315837
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Konstantin Zhuravlyov [Sat, 14 Oct 2017 22:16:26 +0000 (22:16 +0000)]
AMDGPU: Don't use TargetStreamer if it has not been initialized
Fixes cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl
test after r315808
We may hit few other similar issues, but I want to discuss good
solution offline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315830
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Craig Topper [Sat, 14 Oct 2017 21:46:55 +0000 (21:46 +0000)]
[X86] Remove a bunch of dead FileCheck lines with the wrong prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315828
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Simon Pilgrim [Sat, 14 Oct 2017 21:27:53 +0000 (21:27 +0000)]
[TableGen] Avoid unnecessary std::string creations
Avoid unnecessary std::string creations in the TreePredicateFn getters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315826
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Simon Pilgrim [Sat, 14 Oct 2017 19:57:19 +0000 (19:57 +0000)]
[X86][SSE] Don't attempt to reduce the imul vector width of odd sized vectors (PR34947)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315825
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Simon Pilgrim [Sat, 14 Oct 2017 19:46:08 +0000 (19:46 +0000)]
[X86][SSE] Test vector imul reduction on 32 and 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315824
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Bruno Cardoso Lopes [Sat, 14 Oct 2017 19:31:03 +0000 (19:31 +0000)]
Revert "[AArch64][RegisterBankInfo] Use the statically computed mappings for COPY"
This reverts commit r315781, breaks:
http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/9882
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315823
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Konstantin Zhuravlyov [Sat, 14 Oct 2017 19:17:08 +0000 (19:17 +0000)]
AMDGPU: Add AMDGPU HSA Kernel Descriptor
- Update docs to match llvm coding style
- Add missing FP16_OVFL bit for gfx9
- Fix the size of the kernel descriptor in the docs
Differential Revision: https://reviews.llvm.org/D38902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315822
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Konstantin Zhuravlyov [Sat, 14 Oct 2017 19:03:51 +0000 (19:03 +0000)]
AMDGPU: Bring HSA metadata on par with the specification
Differential Revision: https://reviews.llvm.org/D38753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315821
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Konstantin Zhuravlyov [Sat, 14 Oct 2017 18:21:42 +0000 (18:21 +0000)]
llvm-readobj: Print AMDGPU note contents
Differential Revision: https://reviews.llvm.org/D38752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315819
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Simon Pilgrim [Sat, 14 Oct 2017 17:37:42 +0000 (17:37 +0000)]
Pull out repeated calls to VT.getVectorNumElements(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315818
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Simon Pilgrim [Sat, 14 Oct 2017 17:37:03 +0000 (17:37 +0000)]
Cleanup update_llc_test_checks.py notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315817
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Konstantin Zhuravlyov [Sat, 14 Oct 2017 17:36:53 +0000 (17:36 +0000)]
AMDGPU: Cleanup elf-notes.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315816
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Simon Pilgrim [Sat, 14 Oct 2017 17:14:42 +0000 (17:14 +0000)]
Use DAG::getBitcast() helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315815
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Konstantin Zhuravlyov [Sat, 14 Oct 2017 16:43:46 +0000 (16:43 +0000)]
llvm-readobj: Print AMDGPU note type names
Differential Revision: https://reviews.llvm.org/D38751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315813
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Konstantin Zhuravlyov [Sat, 14 Oct 2017 16:15:28 +0000 (16:15 +0000)]
AMDGPU: Improve note directive verification in assembler
- Do not allow amd_amdgpu_isa directives on non-amdgcn architectures
- Do not allow amd_amdgpu_hsa_metadata on non-amdhsa OSes
- Do not allow amd_amdgpu_pal_metadata on non-amdpal OSes
Differential Revision: https://reviews.llvm.org/D38750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315812
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Konstantin Zhuravlyov [Sat, 14 Oct 2017 15:59:07 +0000 (15:59 +0000)]
AMDGPU: Do not emit deprecated notes for code object v3
Differential Revision: https://reviews.llvm.org/D38749
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315810
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Konstantin Zhuravlyov [Sat, 14 Oct 2017 15:40:33 +0000 (15:40 +0000)]
AMDGPU: Add support for isa version note
- Emit NT_AMD_AMDGPU_ISA
- Add assembler parsing for isa version directive
- If isa version directive does not match command line arguments, then return error
Differential Revision: https://reviews.llvm.org/D38748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315808
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Simon Pilgrim [Sat, 14 Oct 2017 15:01:36 +0000 (15:01 +0000)]
[X86][SSE] Support combining AND(EXTRACT(SHUF(X)), C) -> EXTRACT(SHUF(X))
If we are applying a byte mask to a value extracted from a shuffle, see if we can combine the mask into shuffle.
Fixes the last issue with PR22415
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315807
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Craig Topper [Sat, 14 Oct 2017 07:04:48 +0000 (07:04 +0000)]
[X86] Add patterns for vzmovl+cvtpd2dq/cvttpd2dq with a load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315802
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Craig Topper [Sat, 14 Oct 2017 05:55:43 +0000 (05:55 +0000)]
[X86] Add AVX512 versions of VCVTPD2PS to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315801
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Craig Topper [Sat, 14 Oct 2017 05:55:42 +0000 (05:55 +0000)]
[X86] Add patterns for vzmovl+cvtpd2ps with a load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315800
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Craig Topper [Sat, 14 Oct 2017 04:18:11 +0000 (04:18 +0000)]
[X86] Remove some patterns for bitcasted alignednonedtemporalloads.
These select the same instruction as the non-bitcasted pattern. So this provides no additional value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315799
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Craig Topper [Sat, 14 Oct 2017 04:18:10 +0000 (04:18 +0000)]
[X86] Remove unnecessary bitconverts as the root of patterns for zero extended VCVTPD2UDQZ128rr and VCVTTPD2UDQZ128rr.
We don't need a bitconvert as a root pattern in these cases. The types in the other parts of the pattern are sufficient to express the behavior of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315798
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Craig Topper [Sat, 14 Oct 2017 04:18:09 +0000 (04:18 +0000)]
[X86] Add additional patterns for folding loads with 128-bit VCVTDQ2PD and VCVTUDQ2PD.
This matches the patterns we have for the SSE/AVX version.
This is a prerequisite for D38714.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315797
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Craig Topper [Sat, 14 Oct 2017 04:18:08 +0000 (04:18 +0000)]
[X86] Add AVX512 flavors of VCVTDQ2PD plus VCVTUDQ2PD to the load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315796
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Craig Topper [Sat, 14 Oct 2017 04:18:07 +0000 (04:18 +0000)]
[X86] Remove TB_NO_REVERSE from VCVTDQ2PDYrr and VCVTPS2PDYrr in the load folding tables.
I believe these were added incorrectly under the belief that the load size was smaller than the input register size, but that's not true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315795
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Craig Topper [Sat, 14 Oct 2017 04:18:06 +0000 (04:18 +0000)]
[X86] Add an additional isel pattern to CVTDQ2PDrm/VCVTDQ2PDrm to enable load folding without the peephole pass.
This pattern is already used in AVX512VL version of these instructions. Though AVX512VL version is missing other patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315794
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Jordan Rose [Sat, 14 Oct 2017 04:01:27 +0000 (04:01 +0000)]
Revert "lit.py: Add new %{shared_output(LABEL)} substitution"
This reverts r315697 and my ill-fated attempts to fix it on Windows.
I'll try again when I get access to a Windows machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315793
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Jordan Rose [Sat, 14 Oct 2017 03:33:46 +0000 (03:33 +0000)]
lit.py: Give up and disable the new shared-output.py test on Windows
"No such file or directory: C:\\...\\tests\\Output\\shared-output.py.tmp/Output/Shared/SHARED.tmp"
And yet other forward-slashes don't seem to be causing the same
problem. I'll see if I can get ahold of a Windows machine to poke at
this directly later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315792
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Yaxun Liu [Sat, 14 Oct 2017 03:23:18 +0000 (03:23 +0000)]
Fix assembler for alloca of multiple elements in non-zero addr space
Currently llvm assembler emits parsing error for valid IR assembly
alloca i32, i32 9, addrspace(5)
when alloca addr space is 5.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D38713
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315791
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Jakub Kuderski [Sat, 14 Oct 2017 03:00:56 +0000 (03:00 +0000)]
[Dominators] Remove the NCA check
Summary:
This patch removes the `verifyNCD` check.
The reason for this is that the other checks are sufficient to prove or disprove correctness of any DominatorTree, and that `verifyNCD` doesn't provide (in my option) better error messages then the other ones.
Additionally, this should give a (small) improvement to the total verification time, as the check is O(n), and checking the sibling property takes O(n^3).
Reviewers: dberlin, grosser, davide, brzycki
Reviewed By: brzycki
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38802
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315790
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Vedant Kumar [Sat, 14 Oct 2017 02:27:29 +0000 (02:27 +0000)]
[llvm-cov] Factor out logic to iterate over line coverage stats (NFC)
There were two copies of the logic needed to construct a line stats
object for each line in a range: this patch brings it down to one. In
the future, this will make it easier for IDE clients to display coverage
in-line in source editors. To do that, we just need to move the new
LineCoverageIterator class to libCoverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315789
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Daniel Sanders [Sat, 14 Oct 2017 01:51:46 +0000 (01:51 +0000)]
[globalisel][tablegen] Fix an unused variable warning caused by a typo (corrected OtherInsnID->OtherOpIdx).
The tests were passing by luck since the instruction ID and operand index happened to be the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315788
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