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Nicolai Hähnle [Tue, 15 Dec 2015 01:41:15 +0000 (20:41 -0500)]
radeonsi: add RADEON_REPLACE_SHADERS debug option
This option allows replacing a single shader by a pre-compiled ELF object
as generated by LLVM's llc, for example. This can be useful for debugging a
deterministically occuring error in shaders (and has in fact helped find
the causes of https://bugs.freedesktop.org/show_bug.cgi?id=93264).
v2: drop the debug flag, use DEBUG_GET_ONCE_OPTION instead
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 15 Dec 2015 00:34:45 +0000 (19:34 -0500)]
radeonsi: count compilations in si_compile_llvm
This changes the count slightly (because of si_generate_gs_copy_shader), but
this is only relevant for the driver-specific num-compilations query. It sets
the stage for the next commit.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 21 Dec 2015 21:11:37 +0000 (16:11 -0500)]
gallium/util: add DEBUG_GET_ONCE_OPTION
This is analogous to the alreading existing macros for BOOL, NUM, and FLAGS.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Tue, 22 Dec 2015 02:12:07 +0000 (04:12 +0200)]
r600: fix constant buffer size programming
When buffer size is less than 16, zero ends up being programmed as
size, which prevents the hardware from fetching the correct values.
Fix it by combining shift and align so that the value is always
rounded up.
Cc: "11.1 11.0 10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92229
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Kenneth Graunke [Fri, 25 Dec 2015 01:19:14 +0000 (17:19 -0800)]
docs: Mark ARB_tessellation_shader as done on all i965 platforms.
We now support all Intel GPUs which can do tessellation.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 26 Nov 2015 01:56:33 +0000 (17:56 -0800)]
i965: Enable ARB_tessellation_shader on Gen7-7.5.
We've resolved all the GPU hangs, and everything seems to be working.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 24 Dec 2015 21:09:26 +0000 (13:09 -0800)]
i965: Don't set interleave or complete on TCS EOT message.
Setting interleave on the TCS EOT message causes Ivybridge hardware to
GPU hang like crazy. Individual tests would pass, but running even a
simple test like nop.shader_test in a loop would hang within 1-3 runs.
Adding sleep delays worked around the problem, somehow.
Interleave doesn't make much sense given that we only have one patch
URB handle, not two. Complete doesn't seem useful either.
There's no reason to actually set those bits. We were just being lazy.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 26 Nov 2015 01:54:22 +0000 (17:54 -0800)]
i965: Relase input URB Handles on Gen7/7.5 when TCS threads finish.
Pre-Broadwell hardware requires us to manually release the ICP Handles
by issuing URB read messages with the "Complete" bit set. We can do
this in pairs to use fewer URB read messages.
Based heavily on work from Chris Forbes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 24 Dec 2015 23:26:55 +0000 (15:26 -0800)]
i965: Use proper TCS barrier ID bits for Ivybridge/Baytrail.
Gen7 uses bits 15:12 while Gen7+ uses bits 16:13.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 26 Nov 2015 07:27:02 +0000 (23:27 -0800)]
i965: Use proper TCS Instance ID bits for Ivybridge/Baytrail.
Gen7 uses 22:16 while Gen7.5+ uses 23:17.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Tue, 17 Nov 2015 09:30:35 +0000 (01:30 -0800)]
i965: Port tessellation evaluation shaders to vec4 mode.
This can be used on Broadwell by setting INTEL_SCALAR_TES=0.
More importantly, it will be used for Ivybridge and Haswell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 26 Nov 2015 01:18:50 +0000 (17:18 -0800)]
i965: Emit a real 3DSTATE_DS on Gen7.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 26 Nov 2015 01:12:17 +0000 (17:12 -0800)]
i965: Emit a real 3DSTATE_HS on Gen7.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Wed, 2 Dec 2015 06:41:32 +0000 (22:41 -0800)]
i965: Add the TCS/TES state upload atoms to the gen7_atoms list.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 26 Dec 2015 18:00:47 +0000 (10:00 -0800)]
nir: Get rid of function overloads
When Connor originally drafted NIR, he copied the same function+overload
system that GLSL IR had with a few names changed. However, this
double-indirection is not really needed and has only served to confuse
people. Instead, let's just have functions which may not have unique names
and may or may not have an implementation. If someone wants to do overload
resolving, they can hav a hash table based function+overload system in the
overload resolving pass. There's no good reason to keep it in core NIR.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
ir3 bits are
Reviewed-by: Rob Clark <robclark@gmail.com>
Ilia Mirkin [Mon, 28 Dec 2015 01:44:01 +0000 (20:44 -0500)]
nvc0: don't forget to reset VTX_TMP bufctx slot after blit completion
Also release the scratch allocation if any.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Sun, 27 Dec 2015 20:13:21 +0000 (15:13 -0500)]
nv50,nvc0: add a note when converting vertex elements using CPU
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Connor Abbott [Sun, 20 Dec 2015 16:42:56 +0000 (11:42 -0500)]
gallium/auxiliary: don't build NIR sources with MSVC2008 flags
NIR has never been built with MSVC2008, so we shouldn't add
MSVC2008_COMPAT_CFLAGS to anything that uses it. This allows us to get
rid of the pragma in tgsi_to_nir.c.
Build tested with freedreno.
v2: Use MSVC2013_COMPAT_CLFAGS instead.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Anuj Phogat [Wed, 23 Dec 2015 19:14:20 +0000 (11:14 -0800)]
i965: Add tr_mode and mip tail information in surface state dump
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Jordan Justen [Wed, 23 Dec 2015 07:42:52 +0000 (23:42 -0800)]
i965/gen8/cs: Gen8 requires 64 byte alignment for push constant data
The BDW PRM Vol2a: Command Reference: Instructions, section MEDIA_CURBE_LOAD,
says that 'CURBE Total Data Length' and 'CURBE Data Start Address' are
64-byte aligned. This is different from previous gens, that were 32-byte
aligned.
v2 (Jordan):
- CURBE Data Start Address is also 64-byte aligned.
- The call to brw_state_batch should also use 64-byte alignment.
- Improve PRM reference.
v3:
* New patch from Jordan. Always align base and size to 64 bytes.
Fixes the following SSBO CTS tests on BDW:
ES31-CTS.shader_storage_buffer_object.basic-atomic-case1-cs
ES31-CTS.shader_storage_buffer_object.basic-operations-case1-cs
ES31-CTS.shader_storage_buffer_object.basic-operations-case2-cs
ES31-CTS.shader_storage_buffer_object.basic-stdLayout_UBO_SSBO-case2-cs
ES31-CTS.shader_storage_buffer_object.advanced-write-fragment-cs
ES31-CTS.shader_storage_buffer_object.advanced-indirectAddressing-case2-cs
ES31-CTS.shader_storage_buffer_object.advanced-matrix-cs
And many other CS CTS tests as reported by Marta Lofstedt.
(Commit message is from Iago, but in v3, code is from Jordan.)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rob Clark [Wed, 23 Dec 2015 05:06:00 +0000 (00:06 -0500)]
freedreno/ir3: spelling..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 22 Dec 2015 21:50:23 +0000 (16:50 -0500)]
nir/print: print variable constant-initializers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 23 Dec 2015 04:14:35 +0000 (20:14 -0800)]
docs: Clarify that ARB_tessellation_shader is only done on i965/gen8+.
Requested by kisak on IRC.
Kenneth Graunke [Wed, 23 Dec 2015 02:50:18 +0000 (18:50 -0800)]
docs: Mark ARB_tessellation_shader as done on i965/gen8+.
Kenneth Graunke [Mon, 27 Jul 2015 21:19:31 +0000 (14:19 -0700)]
i965: Enable ARB_tessellation_shader on Gen8+.
Everything is in place and I'm not aware of any further issues.
Tested with:
- Piglit
- Tessmark
- Unigine Heaven
- Shadow of Mordor
- GRID Autosport
I have patches to backport this to Haswell, Ivybridge, and Baytrail as
well (the first Intel hardware to support tessellation), but there are
still a lot of GPU hangs left to debug. So that will come later.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Tue, 8 Dec 2015 04:18:42 +0000 (20:18 -0800)]
i965: Handle mix-and-match TCS/TES with separate shader objects.
GL_ARB_separate_shader_objects allows the application to mix-and-match
TCS and TES programs separately. This means that the interface between
the two stages isn't known until the final SSO pipeline is in place.
This isn't a great match for our hardware: the TCS and TES have to agree
on the Patch URB entry layout. Since we store data as per-patch slots
followed by per-vertex slots, changing the number of per-patch slots can
significantly alter the layout. This can easily happen with SSO.
To handle this, we store the [Patch]OutputsWritten and [Patch]InputsRead
bitfields in the TCS/TES program keys, introducing program recompiles.
brw_upload_programs() decides the layout for both TCS and TES, and
passes it to brw_upload_tcs/tes(), which store it in the key.
When creating the NIR for a shader specialization, we override
nir->info.inputs_read (and friends) to the program key's values.
Since everything uses those, no further compiler changes are needed.
This also replaces the hack in brw_create_nir().
To avoid recompiles, brw_precompile_tes() looks to see if there's a
TCS in the linked shader. If so, it accounts for the TCS outputs,
just as brw_upload_programs() would. This eliminates all recompiles
in the non-SSO case. In the SSO case, there should only be recompiles
when using a TCS and TES that have different input/output interfaces.
Fixes Piglit's mix-and-match-tcs-tes test.
v2: Pull the brw_upload_programs code into a brw_upload_tess_programs()
helper function (requested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Tue, 8 Dec 2015 01:58:35 +0000 (17:58 -0800)]
i965: Defer input lowering for tessellation stages until specialization.
With tessellation shaders and SSO, we won't be able to always decide on
VUE map layouts at LinkProgram time. Unfortunately, we have to delay it
until shader specialization time.
However, uniform lowering cannot be deferred - brw_codegen_*_prog()
reads nir->num_uniforms. Fortunately, we don't need to defer it -
uniform, system value, atomic, and sampler lowering can safely stay
where it is. This patch moves those to brw_lower_nir()'s only caller,
renames brw_lower_nir() to brw_nir_lower_io(), and introduces calls
to that.
For non-tessellation stages, I chose to call brw_nir_lower_io() from
brw_create_nir(), so it's still done at the same time. There's no
need to defer it, and doing it at LinkProgram time is nice.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Fri, 18 Dec 2015 10:23:39 +0000 (02:23 -0800)]
i965: Automatically create a passthrough TCS when needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Fri, 18 Dec 2015 11:18:11 +0000 (03:18 -0800)]
i965: Start program_string_id from 1, not 0.
This way, I can safely use brw_tcs_prog_key::program_string_id == 0
to mean "not filled out because no program exists", which avoids the
need for adding an extra boolean to that struct.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Fri, 18 Dec 2015 05:39:28 +0000 (21:39 -0800)]
i965: Create and set a new brw_tcs_prog_data::outputs_written field.
When the application hasn't supplied a TCS, and we have to create one,
we need to know what VS outputs to copy to TES inputs.
To do this, we create a new program key field, and set it to the TES
InputsRead bitfield.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Fri, 18 Dec 2015 11:13:07 +0000 (03:13 -0800)]
i965: Upload HS push constants whenever default tess. levels change.
When using tessellation on OpenGL without a TCS, default values for
gl_TessLevelOuter/gl_TessLevelInner are provided via the API.
Core Mesa will flag ctx->DriverFlags.NewDefaultTessLevels whenever those
values change. We add a corresponding BRW_NEW_DEFAULT_TESS_LEVELS flag
and hook it up to HS push constants (which will be used to upload these
default values to the autogenerated TCS).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Fri, 18 Dec 2015 10:57:05 +0000 (02:57 -0800)]
i965: Only call _mesa_load_state_parameters if prog exists.
With the automatic-TCS creation, we won't have a prog, but still need to
upload push constants.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Fri, 18 Dec 2015 05:24:32 +0000 (21:24 -0800)]
i965: Switch TCS gl_program/gl_shader_program checks over to TES.
Tessellation control shaders are optional, but evaluation shaders will
always be present when using tessellation. However, we'll always enable
the TCS (HS) hardware stage when using tessellation - we'll just create
a program on the fly.
That program, however, won't have a gl_program or gl_shader_program.
So we shouldn't check brw->tess_ctrl_program or
shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] - if we want to know
whether tessellation is enabled, we should look for a TES.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Fri, 18 Dec 2015 05:17:07 +0000 (21:17 -0800)]
i965: Remove unnecessary brw->tess_ctrl_program assertions.
This is trying to enforce the fact that the hardware requires HS, TE,
and DS to be enabled or disabled together. But it's kind of an ad-hoc
attempt, and not too useful.
More importantly, we aren't going to have a gl_shader_program for the
TCS which is automatically generated when none is present. (We'll just
handle it in the driver backend.) So, these will trip for no reason.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Fri, 18 Dec 2015 05:02:40 +0000 (21:02 -0800)]
i965: Consolidate BRW_NEW_TESS_{CTRL,EVAL}_PROGRAM flags.
For several reasons, I don't think it's particularly useful to have
separate flags:
1. Most of the time, tessellation shaders are paired, so both will be
replaced at the same time.
2. The data layout is tightly coupled. Both need to agree on the number
of per-patch slots in the VUE map. Even adding extra TCS outputs
that aren't read by the TES will trigger the need for recompiles.
3. The TCS is optional from an API perspective, but required by the
hardware whenever tessellation is enabled. So, atoms that deal with
the TCS must check brw->tess_eval_program (BRW_NEW_TESS_EVAL_PROGRAM?)
rather than brw->tess_ctrl_program to tell whether tessellation is
enabled.
So, not only is it unlikely to be useful, it's a bit confusing to get
right. Simply using one flag for both simplifies this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Tue, 15 Dec 2015 11:04:50 +0000 (03:04 -0800)]
i965: Only call brw_upload_tcs/tes_prog when using tessellation.
If there's no evaluation shader, tessellation is disabled. The upload
functions would just bail. Instead, don't bother calling them.
This will simplify the optional-TCS case a bit, as brw_upload_tcs can
assume that we're doing tessellation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Fri, 18 Dec 2015 08:42:03 +0000 (00:42 -0800)]
nir: Add a glsl_vec_type() helper.
I need access to glsl_type::vec2_type from C. Wrapping vec() also gives
us access to vec3 if we need it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Mon, 30 Nov 2015 07:23:44 +0000 (23:23 -0800)]
nir: Use writemasked store_vars in glsl_to_nir.
Instead of performing the read-modify-write cycle in glsl->nir, we can
simply emit a partial writemask. For locals, nir_lower_vars_to_ssa will
do the equivalent read-modify-write cycle for us, so we continue to get
the same SSA values we had before.
Because glsl_to_nir calls nir_lower_outputs_to_temporaries, all outputs
are shadowed with temporary values, and written out as whole vectors at
the end of the shader. So, most consumers will still not see partial
writemasks.
However, nir_lower_outputs_to_temporaries bails for tessellation control
shader outputs. So those remain actual variables, and stores to those
variables now get a writemask. nir_lower_io passes that through. This
means that TCS outputs should actually work now.
This is a functional change for tessellation control shaders.
v2: Relax the nir_validate assert to allow partial writemasks.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Tue, 17 Nov 2015 08:26:37 +0000 (00:26 -0800)]
nir: Add a writemask to store intrinsics.
Tessellation control shaders need to be careful when writing outputs.
Because multiple threads can concurrently write the same output
variables, we need to only write the exact components we were told.
Traditionally, for sub-vector writes, we've read the whole vector,
updated the temporary, and written the whole vector back. This breaks
down with concurrent access.
This patch prepares the way for a solution by adding a writemask field
to store_var intrinsics, as well as the other store intrinsics. It then
updates all produces to emit a writemask of "all channels enabled". It
updates nir_lower_io to copy the writemask to output store intrinsics.
Finally, it updates nir_lower_vars_to_ssa to handle partial writemasks
by doing a read-modify-write cycle (which is safe, because local
variables are specific to a single thread).
This should have no functional change, since no one actually emits
partial writemasks yet.
v2: Make nir_validate momentarily assert that writemasks cover the
complete value - we shouldn't have partial writemasks yet
(requested by Jason Ekstrand).
v3: Fix accidental SSBO change that arose from merge conflicts.
v4: Don't try to handle writemasks in ir3_compiler_nir - my code
for indirects was likely wrong, and TTN doesn't generate partial
writemasks today anyway. Change them to asserts as requested by
Rob Clark.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3]
Tapani Pälli [Wed, 16 Dec 2015 06:42:25 +0000 (08:42 +0200)]
mesa: update gl_HelperInvocation support status in docs
Was enabled for i965 and nvc0 by following commits:
c875e3cdd21811ad6669160d59fa39a4526ef872
39f51ec96f00f601b9c4d4e321dacb3af9dc866f
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Tapani Pälli [Wed, 16 Dec 2015 06:24:52 +0000 (08:24 +0200)]
mesa: fix interface matching done in validate_io
Patch makes following changes for interface matching:
- do not try to match builtin variables
- handle swizzle in input name, as example 'a.z' should
match with 'a'
- add matching by location
- check that amount of inputs and outputs matches
These changes make interface matching tests to work in:
ES31-CTS.sepshaderobjs.StateInteraction
The test still does not pass completely due to errors in rendering
output. IMO this is unrelated to interface matching.
Note that type matching is not done due to varying packing which
changes type of variable, this can be added later on. Preferably
when we have quicker way to iterate resources and have a complete
list of all existed varyings (before packing) available.
v2: add spec reference, return true on desktop since we do not
have failing cases for it, inputs and outputs amount do not
need to match on desktop.
v3: add some more spec reference, remove desktop specifics since
not used for now on desktop, add match by location qualifier,
rename input_stage and output_stage as producer and consumer
as suggested by Timothy.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Iago Toral Quiroga [Fri, 18 Dec 2015 09:18:01 +0000 (10:18 +0100)]
mesa: add SSBOs to the list of fragment shader side effects
The i965 driver uses this function to decide if it can disable the
FS unit in the absence of color/depth writes. We don't want to disable
the unit in the presence of SSBOs, since the fragment shader could
be writing to it.
We could go a step further and check not just for the presence of SSBOs
but also if the shader code writes to them. Does not look worth the trouble
though and we are not doing this for atomic buffers either anyway.
v2: put this into a generic _mesa_active_fragment_shader_has_side_effects
function instead of having one specific for SSBOs (Jason).
Fixes the following CTS test:
ES31-CTS.shader_storage_buffer_object.advanced-usage-sync-vsfs
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Fri, 18 Dec 2015 09:18:00 +0000 (10:18 +0100)]
i965: Ensure FS execution in presence of atomic buffers
On Haswell we need to set the UAV_ONLY WM state bit when there are no colour
or depth buffer writes and on all hardware we should set the early
depth/stencil control field to PSEXEC unless early fragment tests are enabled
to make sure that the fragment shader is executed regardless of whether
per-fragment tests pass or not as the spec requires.
So far we have been doing this for images only, but we should apply the same
treatment to all side effectful scenarios. Suggested by Curro.
This is not strictly required for compliance with the original
ARB_shader_atomic_counters extension, it's only necessary to get the execution
semantics specified in GL4.2+ right.
v2:
- Mark active_fs_has_side_effects as constant. (Curro)
- Mention that this is only only necessary to get the execution semantics
specified in GL4.2+ right. (Curro)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Fri, 18 Dec 2015 09:17:59 +0000 (10:17 +0100)]
mesa: Add a _mesa_active_fragment_shader_has_side_effects helper
Some drivers can disable the FS unit if there is nothing in the shader code
that writes to an output (i.e. color, depth, etc). Right now, mesa has
a function to check for atomic buffers and the i965 driver also checks for
images. Refactor this logic into a generic function that we can use for
any source of side effects in a fragment shader. Suggested by Jason.
v2:
- Use '_Shader', as suggested by Tapani, to fix the following CTS test:
ES31-CTS.shader_atomic_counters.advanced-usage-many-draw-calls2
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Kenneth Graunke [Thu, 26 Nov 2015 07:35:29 +0000 (23:35 -0800)]
i965: Implement gl_PatchVerticesIn by baking it into brw_tcs_prog_key.
The hardware provides us no decent way of getting at the number of input
vertices in the patch topology from the tessellation control shader.
It's actually very surprising - normally this sort of information would
be available in the thread payload.
For the precompile, we guess that the number of vertices will be the
same for both the input and output patches. This usually seems to be
the case.
On Gen8+, we could pass in an extra push constant containing this value.
We may be able to do that on Haswell too. It's quite a bit trickier on
Ivybridge, however.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Tue, 17 Nov 2015 09:07:39 +0000 (01:07 -0800)]
i965: Add tessellation control shaders.
The TCS is the first tessellation shader stage, and the most
complicated. It has access to each of the control points in the input
patch, and computes a new output patch. There is one logical invocation
per output control point; all invocations run in parallel, and can
communicate by reading and writing output variables.
One of the main responsibilities of the TCS is to write the special
gl_TessLevelOuter[] and gl_TessLevelInner[] output variables which
control how much new geometry the hardware tessellation engine will
produce. Otherwise, it simply writes outputs that are passed along
to the TES.
We run in SIMD4x2 mode, handling two logical invocations per EU thread.
The hardware doesn't properly manage the dispatch mask for us; it always
initializes it to 0xFF. We wrap the whole program in an IF..ENDIF block
to handle an odd number of invocations, essentially falling back to
SIMD4x1 on the last thread.
v2: Update comments (requested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Tue, 10 Nov 2015 22:35:27 +0000 (14:35 -0800)]
i965: Add tessellation evaluation shaders
The TES is essentially a post-tessellator VS, which has access to the
entire TCS output patch, and a special gl_TessCoord input. Otherwise,
they're very straightforward.
This patch implements SIMD8 tessellation evaluation shaders for Gen8+.
The tessellator can generate a lot of geometry, so operating in SIMD8
mode (8 vertices per thread) is more efficient than SIMD4x2 mode (only
2 vertices per thread). I have another patch which implements SIMD4x2
mode for older hardware (or via an environment variable override).
We currently handle all inputs via the pull model.
v2: Improve comments (suggested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Timothy Arceri [Mon, 21 Dec 2015 22:44:38 +0000 (09:44 +1100)]
nir: remove field only used in GLSL IR when assigning varying locations
This field is used as a flag to optimise out any varyings that don't have
a matching varying on the other side of the interface.
The value should be the same for all varyings (except for SSO but we can't
optimise those) by the time they reach nir and are no longer be needed.
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Ben Skeggs [Thu, 26 Nov 2015 05:17:53 +0000 (15:17 +1000)]
nouveau: enable use of new kernel interfaces
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ben Skeggs [Wed, 16 Dec 2015 23:03:49 +0000 (09:03 +1000)]
nvc0: remove use of deprecated sw class identifier
Also emits a method to properly bind the class to a subchannel, which
was missing previously. The kernel currently doesn't care, but this
will break if it ever decides to (ie. to support multiple sw classes).
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ben Skeggs [Tue, 24 Nov 2015 23:01:32 +0000 (09:01 +1000)]
nv50: fix g98+ vdec class allocation
The kernel previously exposed incorrect classes for some of the chipsets
that this code supports. It no longer does, but the older object ioctls
have compatibility to avoid breaking userspace.
This needs to be fixed before switching over to the newer interfaces.
Rather than hardcoding chipset->class like the rest of the driver does,
this makes use of (new) sclass queries to determine what's available.
v2.
- update to use symbolic class identifier from <nvif/class.h>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ben Skeggs [Thu, 26 Nov 2015 02:59:13 +0000 (12:59 +1000)]
nouveau: remove use of deprecated nouveau_device_wrap()
Switching to the newer libdrm entry-points tells libdrm that it's OK to
make use of newer kernel interfaces.
We want to be able to isolate any bugs to either the interfaces changes,
or the use of NVIF itself. As such, this commit has a slight hack which
forces libdrm to continue using the older kernel interfaces.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ben Skeggs [Thu, 26 Nov 2015 04:34:43 +0000 (14:34 +1000)]
nouveau: fix screen creation failure paths
The winsys layer would attempt to cleanup the nouveau_device if screen
init failed, however, in most paths the pipe driver would have already
destroyed it, resulting in accesses to freed memory etc.
This commit fixes the problem by allowing the winsys to detect whether
the pipe driver's destroy function needs to be called or not.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ben Skeggs [Thu, 26 Nov 2015 04:24:42 +0000 (14:24 +1000)]
nouveau: return nouveau_screen from hw-specific creation functions
Kills off a void cast.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ben Skeggs [Wed, 25 Nov 2015 23:57:30 +0000 (09:57 +1000)]
nouveau: remove use of deprecated nouveau_device::drm_version
v2. update for libdrm nouveau_drm::lib_version removal
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ben Skeggs [Wed, 25 Nov 2015 23:38:35 +0000 (09:38 +1000)]
nouveau: remove use of deprecated nouveau_device::fd
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ben Skeggs [Tue, 3 Nov 2015 05:55:55 +0000 (15:55 +1000)]
nouveau: bump required libdrm version to 2.4.66
v2. forgot bump for non-gallium driver
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Sat, 19 Dec 2015 23:01:22 +0000 (23:01 +0000)]
r600: fix viewport clipping handling (v2)
If oViewport is written, vertex reuse need to be turned off.
If oViewport is constant, vertex reuse is fine, and VPORT_PROVOKE_DISABLE
need to be set. (we don't have enough info to program VPORT_PROVOKE).
Fixes: arb_viewport_array-render-viewport-2 and some CTS tests.
v2: drop vport provoke write, drop initial state writing this
on evergreen, only program it on evergreen.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Sat, 19 Dec 2015 23:01:21 +0000 (23:01 +0000)]
radeonsi: fix viewport clipping handling. (v2)
If oViewport is written, vertex reuse need to be turned off.
If oViewport is constant, vertex reuse is fine, and VPORT_PROVOKE_DISABLE
need to be set. (We don't know if oViewport is constant so we
skip this.)
Fixes: arb_viewport_array-render-viewport-2 and some CTS tests.
v2: drop writing to provoke disable, drop write in initial
state.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sat, 19 Dec 2015 23:01:20 +0000 (23:01 +0000)]
r600: drop VTX_CNT_EN write from initial state
we always program this in shader stages atom now.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Sat, 19 Dec 2015 04:25:16 +0000 (23:25 -0500)]
gallium/radeon: fix regression in a number of driver queries
This rather silly mistake was introduced by commit
01910676.
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ben Widawsky [Thu, 17 Dec 2015 18:53:25 +0000 (10:53 -0800)]
i965: Only apply CS stall workaround pre-SKL
As per the docs.
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Sat, 19 Dec 2015 20:29:14 +0000 (15:29 -0500)]
glx/dri3: a drawable might not be bound at wait time
A trace of Alien Isolation hit this on nouveau.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Emil Velikov [Mon, 21 Dec 2015 10:13:17 +0000 (10:13 +0000)]
docs: add news item and link release notes for 11.0.8
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 21 Dec 2015 10:08:14 +0000 (10:08 +0000)]
docs: add sha256 checksums for 11.0.8
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
b9b19162ee3f8d68be76b71adf2a290cbb675660)
Emil Velikov [Mon, 21 Dec 2015 09:22:06 +0000 (09:22 +0000)]
docs: add release notes for 11.0.8
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
261daab6b4f7a1cff143bebcd632ad5a2cdafa74)
Dave Airlie [Mon, 12 Oct 2015 03:23:29 +0000 (13:23 +1000)]
glsl: count attributes for vertex inputs properly.
This function deals with vertex inputs and fragment
outputs, so we should count the attribute locations
correctly for the vertex inputs.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Fri, 18 Dec 2015 10:48:34 +0000 (02:48 -0800)]
ralloc: Fix ralloc_adopt() to the old context's last child's parent.
I was cleverly using one iteration to obtain a pointer to the last item
in ralloc's singly list child list, while also setting parents.
Unfortunately, I forgot to set the parent on that last item.
Cc: "11.1 11.0 10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Dave Airlie [Mon, 12 Oct 2015 04:15:19 +0000 (14:15 +1000)]
glsl: fix transform feedback for 64-bit outupts.
This fixes the calculations for transform feedback for doubles.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 12 Oct 2015 03:55:00 +0000 (13:55 +1000)]
glsl: fix partial marking for fp64 types.
This doubles the element width for the types that are greater
than 2 elements wide.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 12 Oct 2015 03:47:40 +0000 (13:47 +1000)]
glsl: only update doubles inputs for vertex inputs.
This doesn't apply to other stages. This is only
used in the mesa/st code, which needs further fixes.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Anholt [Fri, 19 Sep 2014 19:26:27 +0000 (12:26 -0700)]
vc4: Do instruction scheduling on the QIR to hide texture fetch latency.
This is a rewrite of vc4_opt_qpu_schedule.c to operate on QIR. Texture
fetch can probably take as much as the rest of the cycles of the program,
so it's important to hide our other cycles during it (which is hard to do
after register allocation). Also, we can queue up multiple texture
requests before collecting the resulting samples, so that we keep the
texture unit busy more of the time.
High-settings openarena performance +2.35849% +/- 0.221154% (n=7). Also
about 2-3% on the multiarb demo. 8 piglit tests
(ext_framebuffer_multisample accuracy depthstencil) go from failing in
rendering to failing in register allocation, but hopefully I can fix that
up with some better register pressure handling here.
total instructions in shared programs: 87723 -> 88448 (0.83%)
instructions in affected programs: 78411 -> 79136 (0.92%)
total estimated cycles in shared programs: 276583 -> 246306 (-10.95%)
estimated cycles in affected programs: 265691 -> 235414 (-11.40%)
Eric Anholt [Fri, 18 Dec 2015 19:30:30 +0000 (11:30 -0800)]
vc4: Fix latency handling for QPU texture scheduling.
There's only high latency between a complete texture fetch setup and
collecting its result, not between each step of setting up the texture
fetch request.
Eric Anholt [Fri, 18 Dec 2015 19:41:38 +0000 (11:41 -0800)]
vc4: Keep sample mask writes from being reordered after TLB writes
Fixes a regression I noticed after introducing scheduling on the QIR.
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Dave Airlie [Wed, 9 Dec 2015 06:06:48 +0000 (16:06 +1000)]
glsl: fix count_attribute_slots to allow for different 64-bit handling
So vertex shader input attributes are handled different than internal
varyings between shader stages, dvec3 and dvec4 only count as
one slot for vertex attributes, but for internal varyings, they
count as 2.
This patch comments all the uses of this API to clarify what we
pass in, except one which needs further investigation
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Dave Airlie [Wed, 9 Dec 2015 06:06:47 +0000 (16:06 +1000)]
glsl: use dual slot helper in the linker code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Dave Airlie [Wed, 9 Dec 2015 06:06:46 +0000 (16:06 +1000)]
glsl/fp64: add helper for dual slot double detection.
The old function didn't work for matrices, and we need this
in other places to fix some other problems, so move to a helper
in glsl type and fix the one user so far.
A dual slot double is one that has 3 or 4 components in it's
base type.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Dave Airlie [Wed, 9 Dec 2015 06:06:45 +0000 (16:06 +1000)]
glsl: pass stage into mark function
Don't use a bool here, as for some 64-bit fixes we need
the stage.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Rob Herring [Thu, 17 Dec 2015 15:42:40 +0000 (09:42 -0600)]
freedreno/ir3: fix 32-bit builds with pointer-to-int-cast error enabled
Android builds with -Werror=pointer-to-int-cast causing an error on 32-bit
builds.
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Matt Turner [Thu, 26 Nov 2015 05:54:30 +0000 (21:54 -0800)]
i965/vec4: Optimize predicate handling for any/all.
For a select whose condition is any(v), instead of emitting
cmp.nz.f0(8) null<1>D g1<0,4,1>D 0D
mov(8) g7<1>.xUD 0x00000000UD
(+f0.any4h) mov(8) g7<1>.xUD 0xffffffffUD
cmp.nz.f0(8) null<1>D g7<4,4,1>.xD 0D
(+f0) sel(8) g8<1>UD g4<4,4,1>UD g3<4,4,1>UD
we now emit
cmp.nz.f0(8) null<1>D g1<0,4,1>D 0D
(+f0.any4h) sel(8) g9<1>UD g4<4,4,1>UD g3<4,4,1>UD
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 30 Nov 2015 22:35:08 +0000 (14:35 -0800)]
nir: Delete bany, ball, fany, fall.
As in the previous patches, these can be implemented as
any(v) -> any_nequal(v, false)
all(v) -> all_equal(v, true)
and their removal simplifies the code in the next patch.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Mon, 30 Nov 2015 20:18:27 +0000 (12:18 -0800)]
glsl: Implement all(v) as all_equal(v, true).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Mon, 30 Nov 2015 19:56:31 +0000 (11:56 -0800)]
glsl: Remove ir_unop_any.
The GLSL IR to TGSI/Mesa IR paths for any_nequal have the same
optimizations the ir_unop_any paths had.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Mon, 30 Nov 2015 18:50:05 +0000 (10:50 -0800)]
glsl: Implement any(v) as any_nequal(v, false).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Nicolai Hähnle [Mon, 14 Dec 2015 21:10:31 +0000 (16:10 -0500)]
gallium/radeon: only dispose locally created target machine in radeon_llvm_compile
Unify the cleanup paths of the function rather than duplicating code.
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Roland Scheidegger [Fri, 18 Dec 2015 00:02:16 +0000 (01:02 +0100)]
gallium/util: (trivial) include p_shader_tokens.h in u_simple_shaders.h
as it uses definition from it (enum tgsi_return_type).
Roland Scheidegger [Thu, 17 Dec 2015 16:54:12 +0000 (17:54 +0100)]
draw: fix clip test with NaNs
NaNs mean it should be clipped, otherwise the NaNs might get passed to the
next stages (if clipping didn't happen for another reason already), which
might cause all kind of problems.
The llvm path got this right already (possibly by luck), but this isn't used
when there's a gs active.
Found by code inspection, verified with some hacked piglit test and some more
hacked debug output.
(Note the clipper can still itself incorrectly generate NaN and INF position
values in its output prims (at least after w divide / viewport transform) even
if the inputs weren't NaNs, if the position data of the vertices is
"sufficiently bad".)
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Thu, 17 Dec 2015 04:58:58 +0000 (05:58 +0100)]
draw: fix pstipple and aaline stages wrt sampler_views/samplers
Those stages only really work for OGL-style texturing (so number of samplers
and views mostly the same, certainly for the max values).
These get often set up all at once, thus there might be max number of both
even if all of them are just NULL. We must not set the max number of samplers
and views to the same value since that will lead to terrible things if a driver
supports more views than samplers (and the state tracker set up all the views).
(This will not make these stages magically work if a shader uses dx10-style
texturing, they might still replace an actually used sview in that case.)
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Miklós Máté [Tue, 15 Dec 2015 23:05:42 +0000 (00:05 +0100)]
swrast: move two global defines to the only place where they are used
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Miklós Máté [Tue, 15 Dec 2015 23:05:41 +0000 (00:05 +0100)]
mesa: improve debug log in atifragshader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Miklós Máté [Tue, 15 Dec 2015 23:05:40 +0000 (00:05 +0100)]
program: fix comment about the fog formula
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Miklós Máté [Tue, 15 Dec 2015 23:05:34 +0000 (00:05 +0100)]
mesa: Don't leak ATIfs instructions in DeleteFragmentShader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Oded Gabbay [Tue, 15 Dec 2015 10:05:22 +0000 (12:05 +0200)]
configura.ac: fix test for SSE4.1 assembler support
This patch modifies the SSE4.1 test in configure.ac to use a global
variable to initialize vector variables. In addition, we now return the
value of the computation instead of 0.
This is done so gcc 4.9 (and lower) won't optimize the SSE4.1 assembly
instructions (when using -O1 and higher), because then the configure test
might incorrectly pass even though the assembler doesn't support the
SSE4.1 instructions (the test will pass because the compiler does support the intrinsics).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91806
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Jonathan Gray [Sun, 6 Dec 2015 05:11:05 +0000 (16:11 +1100)]
configure: check for python2.7 for PYTHON2
Check for a 'python2.7' binary, 'python' and 'python2' are not
provided by the OpenBSD python 2.7.x packages.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Jonathan Gray [Wed, 9 Dec 2015 05:55:01 +0000 (16:55 +1100)]
configure.ac: use pkg-config for libelf
Use PKG_CHECK_MODULES to get the flags to link libelf
v2: keep AC_CHECK_LIB as a fallback for elfutils provided
libelf that doesn't install a pkg-config file.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Jordan Justen [Tue, 15 Dec 2015 23:53:20 +0000 (15:53 -0800)]
i965/screen: Allow OpenGLES 3.1 for gen8+
OpenGLES 3.1 cannot be enabled for gen 7 (Ivy Bridge, Haswell) since
they are still missing ARB_stencil_texturing.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
Jordan Justen [Tue, 15 Dec 2015 23:51:25 +0000 (15:51 -0800)]
i965: Enable compute shaders in more cases for OpenGLES 3.1
Previously we were checking the desktop OpenGL ARB_compute_shader
requirements, but for OpenGLES 3.1, the requirements are lower.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
Jordan Justen [Tue, 15 Dec 2015 23:47:30 +0000 (15:47 -0800)]
main/version: Don't require ARB_compute_shader for OpenGLES 3.1
The OpenGL ARB_compute_shader extension specfication requires at least
1024 for GL_MAX_COMPUTE_WORK_GROUP_INVOCATIONS, whereas OpenGLES 3.1
only required 128.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jordan Justen [Tue, 15 Dec 2015 23:44:11 +0000 (15:44 -0800)]
main: Allow compute shaders to be compiled with OpenGLES 3.1
Previous OpenGLES 3.1 testing had been done when ARB_compute_shader
was overridden to enabled.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
Jordan Justen [Tue, 15 Dec 2015 23:43:17 +0000 (15:43 -0800)]
main: Add MESA_VERBOSE=api for LinkProgram & UseProgram
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>