OSDN Git Service
Evandro Menezes [Fri, 9 Feb 2018 16:14:41 +0000 (16:14 +0000)]
[AArch64] Refactor stand alone methods (NFC)
Make stand alone methods in AArch64InstrInfo static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324745
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David Blaikie [Fri, 9 Feb 2018 15:39:04 +0000 (15:39 +0000)]
Pre-emptively fix test case for windows path separators
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324740
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David Blaikie [Fri, 9 Feb 2018 15:33:39 +0000 (15:33 +0000)]
Remove some unnecessary REQUIRES: shell from a couple of llvm-symbolizer tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324738
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Krzysztof Parzyszek [Fri, 9 Feb 2018 15:30:02 +0000 (15:30 +0000)]
[Hexagon] Express calling conventions via .td file instead of hand-coding
Additionally, simplify the rest of the argument/parameter lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324737
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Stefan Maksimovic [Fri, 9 Feb 2018 14:03:26 +0000 (14:03 +0000)]
[DebugInfo] Don't insert DEBUG_VALUE after terminators
r314974 introduced insertion of DEBUG_VALUEs after
each redefinition of debug value register in the slot index range.
In case the instruction redefining the debug value register
was a terminator, machine verifier would complain since it
enforces the rule of no non-terminator instructions
following the first terminator.
Differential Revision: https://reviews.llvm.org/D42801
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324734
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Stefan Maksimovic [Fri, 9 Feb 2018 13:55:25 +0000 (13:55 +0000)]
[SelectionDAG] Provide adequate register class for RegisterSDNode
When adding operands to machine instructions in case of
RegisterSDNodes, generate a COPY node in case the register class
does not match the one in the instruction definition.
Differental Revision: https://reviews.llvm.org/D35561
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324733
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Oliver Stannard [Fri, 9 Feb 2018 13:34:39 +0000 (13:34 +0000)]
[ELF] Print the .type assembly directive correctly for STT_NOTYPE
The llvm assembly parser and gas both accept "@notype" in the .type
assembly directive, but we were printing it as "@no_type", which isn't
accepted by either assembler.
Differential revision: https://reviews.llvm.org/D43116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324731
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Simon Dardis [Fri, 9 Feb 2018 10:46:16 +0000 (10:46 +0000)]
[mips] UnXFAIL gprestore.ll test.
Repurpose this previously XFAIL'd test to check that jalr uses $25
as per ABI requirements for PIC code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324729
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Simon Pilgrim [Fri, 9 Feb 2018 10:43:59 +0000 (10:43 +0000)]
[InstCombine] Add constant vector support for X udiv C, where C >= signbit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324728
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Clement Courbet [Fri, 9 Feb 2018 10:28:46 +0000 (10:28 +0000)]
[TargetSchedule] Fix r324582.
Increment was using the wrong NumUnits (the one from the ProcResGroup
and not the subunit).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324727
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Pavel Labath [Fri, 9 Feb 2018 10:06:56 +0000 (10:06 +0000)]
[CodeGen] Optimize AccelTable
Summary:
The class contained arrays of two structures (DataArray and HashData).
These structures were in 1:1 correspondence, and one of them contained
pointers to the other (and *both* contained a "Name" field). By merging
these two structures into one, we can save a bit of space without
negatively impacting much of anything.
Reviewers: JDevlieghere, aprantl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43073
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324724
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Jonas Paulsson [Fri, 9 Feb 2018 09:22:20 +0000 (09:22 +0000)]
[AArch64] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation.
Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.
Review: Martin Storsjö
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324720
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Serguei Katkov [Fri, 9 Feb 2018 07:59:07 +0000 (07:59 +0000)]
Rename and move utility function getLatchPredicateForGuard. NFC.
Rename getLatchPredicateForGuard to more common name
getFlippedStrictnessPredicate and move it to ICmpInst class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324717
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Vedant Kumar [Fri, 9 Feb 2018 06:09:15 +0000 (06:09 +0000)]
[bugpoint] Report non-existent opt binary
Bugpoint will keep going even if the opt binary it's given doesn't
exist. It should at least alert the user, so it's clear why reductions
are failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324713
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Stanislav Mekhanoshin [Fri, 9 Feb 2018 06:05:33 +0000 (06:05 +0000)]
[AMDGPU] More descriptive names in the memory legalizer
NFC.
Differential Revision: https://reviews.llvm.org/D43054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324712
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Peter Collingbourne [Fri, 9 Feb 2018 05:58:55 +0000 (05:58 +0000)]
LTO: Include live bit in ThinLTO cache key.
As of r323633, this bit started controlling whether symbol definitions
appear in object files, and it also became sensitive to the prevailing
bit, so it needs to be included in the key.
Differential Revision: https://reviews.llvm.org/D43109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324711
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Craig Topper [Fri, 9 Feb 2018 05:54:36 +0000 (05:54 +0000)]
[X86] Simplify some code in lowerV4X128VectorShuffle and lowerV2X128VectorShuffle
Previously we extracted two subvectors and concatenate. But the concatenate will be lowered to two insert subvectors. Then DAG combine will merge once of the inserts and one of the extracts back into the original vector. We might as well just directly use one extract and one insert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324710
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Craig Topper [Fri, 9 Feb 2018 05:54:34 +0000 (05:54 +0000)]
[X86] Teach shuffle lowering to recognize 128/256 bit insertions into a zero vector.
This regresses a couple cases in the shuffle combining test. But those cases use intrinsics that InstCombine knows how to turn into a generic shuffle earlier. This should give opportunities to fold this earlier in InstCombine or DAG combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324709
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Craig Topper [Fri, 9 Feb 2018 05:54:31 +0000 (05:54 +0000)]
[X86] Add 512-bit shuffle test cases for concatenating 128/256-bits with zeros in the upper portion.
We should recognize this and just use a mov that will zero the upper bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324708
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Victor Leschuk [Fri, 9 Feb 2018 05:28:38 +0000 (05:28 +0000)]
[lit] Pass CLANG env var to testing configuration
Allow CLANG environment variable be copied into the testing configuration
and proper support testing with a custom path to the clang executable.
Signed-off-by: Vladimir Vereschaka <vvereschaka@accesssoftek.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324706
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Vedant Kumar [Fri, 9 Feb 2018 05:09:50 +0000 (05:09 +0000)]
[bugpoint] Simplify reducers which can fail verification, NFC
More unique_ptr-ification, ranged for loops, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324705
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Vedant Kumar [Fri, 9 Feb 2018 05:09:49 +0000 (05:09 +0000)]
[bugpoint] Delete a dead cl::opt (-child-output)
This option isn't used anywhere, as far as I can tell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324704
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Vedant Kumar [Fri, 9 Feb 2018 05:09:48 +0000 (05:09 +0000)]
[bugpoint] Avoid noisy errors by passing a valid opt to tests
If the tests don't use the in-tree opt, we're liable to see some silly
error messages due to the version mismatch (missing flags, etc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324703
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David Blaikie [Fri, 9 Feb 2018 03:34:32 +0000 (03:34 +0000)]
DebugInfo/llvm-symbolizer: Test symbolizing Split DWARF without addresses in the skeleton CU
Identified in an llvm-dev discussion around
DWARFUnit::collectAddressRanges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324702
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Lang Hames [Fri, 9 Feb 2018 02:30:40 +0000 (02:30 +0000)]
[ORC] Remove Layer handles from the layer concept.
Handles were returned by addModule and used as keys for removeModule,
findSymbolIn, and emitAndFinalize. Their job is now subsumed by VModuleKeys,
which simplify resource management by providing a consistent handle across all
layers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324700
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Douglas Yung [Fri, 9 Feb 2018 02:13:15 +0000 (02:13 +0000)]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324699
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Aditya Nandakumar [Fri, 9 Feb 2018 01:27:23 +0000 (01:27 +0000)]
[GISel]: Verify COPIES involving generic registers.
Add verification for copies involving generic registers if they are
compatible - ie if it is a generic copy, then the types are the
same, and if a COPY b/w generic and target virtual register, then
the sizes should be the same. Only checks if there are no sub registers
involved for now.
https://reviews.llvm.org/D37775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324696
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Francis Visoiu Mistrih [Fri, 9 Feb 2018 01:14:44 +0000 (01:14 +0000)]
[CodeGen] Unify the syntax of MBB liveins in MIR and -debug output
Instead of:
Live Ins: %r0 %r1
print:
liveins: %r0, %r1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324694
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Craig Topper [Fri, 9 Feb 2018 01:14:17 +0000 (01:14 +0000)]
[x86] Add test cases to demonstrate some dumb mask->gpr->mask transition sequences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324693
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Evgeniy Stepanov [Fri, 9 Feb 2018 00:59:10 +0000 (00:59 +0000)]
[hwasan] Fix kernel instrumentation of stack.
Summary:
Kernel addresses have 0xFF in the most significant byte.
A tag can not be pushed there with OR (tag << 56);
use AND ((tag << 56) | 0x00FF..FF) instead.
Reviewers: kcc, andreyknvl
Subscribers: srhines, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D42941
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324691
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Francis Visoiu Mistrih [Fri, 9 Feb 2018 00:40:57 +0000 (00:40 +0000)]
[CodeGen] Don't compute BranchProbability for MBB::print
Avoid re-computing BP only to print successor probabilities in -debug
printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324690
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Francis Visoiu Mistrih [Fri, 9 Feb 2018 00:12:53 +0000 (00:12 +0000)]
[CodeGen] Only print successors when the list is not empty
Follow-up of r324685.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324686
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Francis Visoiu Mistrih [Fri, 9 Feb 2018 00:10:31 +0000 (00:10 +0000)]
[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
Instead of:
Successors according to CFG: %bb.6(0x12492492 / 0x80000000 = 14.29%)
print:
successors: %bb.6(0x12492492); %bb.6(14.29%)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324685
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Francis Visoiu Mistrih [Thu, 8 Feb 2018 23:42:27 +0000 (23:42 +0000)]
[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print
MBB.print wasn't printing it, but the MIRPrinter is printing it. The
goal is to unify that as much as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324681
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Jacques Pienaar [Thu, 8 Feb 2018 23:25:05 +0000 (23:25 +0000)]
[Lanai] Code model dictates section selection.
Always use the small section when the small code model is specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324679
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Sanjay Patel [Thu, 8 Feb 2018 23:21:44 +0000 (23:21 +0000)]
[x86] consolidate and add tests for undef binop folds; NFC
As was already shown in the div/rem tests and noted in PR36305,
the behavior is inconsistent, but it's not limited to div/rem only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324678
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Adrian Prantl [Thu, 8 Feb 2018 23:21:15 +0000 (23:21 +0000)]
Use a stable topological sort in DwarfCompileUnit::createScopeChildrenDIE()
This addresses review feedback for D42940. The topological sort is
slightly more expensive but it can now also detect cycles in the
dependencies and actually works correctly.
rdar://problem/
37217988
Differential Review: https://reviews.llvm.org/D43036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324677
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Dmitry Mikulin [Thu, 8 Feb 2018 23:10:07 +0000 (23:10 +0000)]
Minor tweak to test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324670
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Paul Robinson [Thu, 8 Feb 2018 23:08:02 +0000 (23:08 +0000)]
[DWARFv5] Fix dumper to show the file table starts at index 0.
Emitting the correct (root of compilation) file at index 0 will be
posted for review later; I wanted to get this minor change out of the
way first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324669
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Matt Arsenault [Thu, 8 Feb 2018 22:46:41 +0000 (22:46 +0000)]
AMDGPU: Process SDWA block at a time
Right now this loops over the entire function every time there
is a change, which is not very efficient. There's no practical
reason to track this so globally, since the code motion optimization
passes should be sinking instructions with single uses and
the pass currently will not fold with multiple uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324667
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Matt Arsenault [Thu, 8 Feb 2018 22:46:38 +0000 (22:46 +0000)]
AMDGPU: Minor cleanups
Column limit, typo, unnecessary reference
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324666
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Alexander Ivchenko [Thu, 8 Feb 2018 22:41:47 +0000 (22:41 +0000)]
[GlobalISel][X86] Fixing failures after https://reviews.llvm.org/D37775
The patch essentially makes sure that X86CallLowering adds proper
G_COPY/G_TRUNC and G_ANYEXT/G_COPY when we are doing lowering of
arguments/returns for floating point values passed on registers.
Tests are updated accordingly
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D42287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324665
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Alexander Ivchenko [Thu, 8 Feb 2018 22:40:31 +0000 (22:40 +0000)]
[GlobalIsel][X86] Making {G_IMPLICIT_DEF, s128} legal
The patch is a split from D42287 and is related to
fixing failures after https://reviews.llvm.org/D37775
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D42287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324664
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Craig Topper [Thu, 8 Feb 2018 22:26:39 +0000 (22:26 +0000)]
[X86] Improve combineCastedMaskArithmetic to fold (bitcast (vXi1 (and/or/xor X, C)))->(vXi1 (and/or/xor (bitcast X), (bitcast C)) where C is a constant build_vector.
Most vxi1 constant build vectors have to be implemented in the scalar domain anyway so we'll probably end up with a cast there later. But by then its too late to do the combine to get rid of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324662
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Craig Topper [Thu, 8 Feb 2018 22:26:36 +0000 (22:26 +0000)]
[X86] Add DAG combine to constant fold a bitcast of a vXi1 constant build_vector into a scalar integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324661
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Justin Bogner [Thu, 8 Feb 2018 22:19:00 +0000 (22:19 +0000)]
CMake: Explicitly #undef LLVM_REVISION rather than using a blank file
Including a blank file is confusing and makes it look like something
went wrong. Rather than requiring people know why this is blank, let's
just make it explicitly #undef the macro that it would define if it
weren't empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324659
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Dmitry Mikulin [Thu, 8 Feb 2018 22:14:56 +0000 (22:14 +0000)]
[ThinLTO] Skip BlockAddresses while replacing uses in function import.
Differential Revision: https://reviews.llvm.org/D43027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324658
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Paul Robinson [Thu, 8 Feb 2018 22:09:17 +0000 (22:09 +0000)]
Parameterize a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324657
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Daniel Neilson [Thu, 8 Feb 2018 21:28:26 +0000 (21:28 +0000)]
[DSan] Update uses of memory intrinsic get/setAlignment to new API (NFC)
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
DataFlowSanitizer pass to cease using the old get/setAlignment() API of MemoryIntrinsic
in favour of getting source & dest specific alignments through the new API.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324654
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Daniel Neilson [Thu, 8 Feb 2018 21:26:12 +0000 (21:26 +0000)]
[ASan] Update uses of IRBuilder::CreateMemCpy to new API (NFC)
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
AddressSanitizer pass to cease using The old IRBuilder CreateMemCpy single-alignment API
in favour of the new API that allows setting source and destination alignments independently.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324653
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Vedant Kumar [Thu, 8 Feb 2018 20:27:35 +0000 (20:27 +0000)]
Revert "WIP: [DAGCombiner] Assert that debug info is preserved"
This reverts commit r324648. It was committed accidentally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324650
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Vedant Kumar [Thu, 8 Feb 2018 20:27:09 +0000 (20:27 +0000)]
[bugpoint] Simplify the global initializer reducer, NFC
Fix the comments, use early exits, use unique_ptr, and use ranged for
loops.
This is in preparation for a global *variable* reducer, which, with any
luck will help us clean up test cases.
Differential Revision: https://reviews.llvm.org/D43084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324649
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Vedant Kumar [Thu, 8 Feb 2018 20:27:09 +0000 (20:27 +0000)]
WIP: [DAGCombiner] Assert that debug info is preserved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324648
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Craig Topper [Thu, 8 Feb 2018 20:16:06 +0000 (20:16 +0000)]
[X86] Remove kortest intrinsics and replace with native IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324646
91177308-0d34-0410-b5e6-
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David Woodhouse [Thu, 8 Feb 2018 20:06:05 +0000 (20:06 +0000)]
[X86] Support 'V' register operand modifier
This allows the register name to be printed without the leading '%'.
This can be used for emitting calls to the retpoline thunks from inline
asm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324645
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David Blaikie [Thu, 8 Feb 2018 19:57:05 +0000 (19:57 +0000)]
Fix missing field initializer warning in TableGen SubtargetEmitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324643
91177308-0d34-0410-b5e6-
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Daniel Neilson [Thu, 8 Feb 2018 19:46:12 +0000 (19:46 +0000)]
[MSan] Update uses of IRBuilder::CreateMemCpy to new API (NFC)
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
MemorySanitizer pass to cease using the old IRBuilder CreateMemCpy single-alignment APIs
in favour of the new API that allows setting source and destination alignments independently.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324642
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Simon Pilgrim [Thu, 8 Feb 2018 19:28:05 +0000 (19:28 +0000)]
Regenerate test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324639
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Simon Pilgrim [Thu, 8 Feb 2018 19:23:47 +0000 (19:23 +0000)]
[X86] Add common CHECK prefix to shift combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324638
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Simon Pilgrim [Thu, 8 Feb 2018 19:20:34 +0000 (19:20 +0000)]
[X86] Add shift undef, %X tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324637
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Simon Pilgrim [Thu, 8 Feb 2018 19:00:45 +0000 (19:00 +0000)]
[InstCombine] visitSRem - use m_Negative(APInt) helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324636
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Simon Pilgrim [Thu, 8 Feb 2018 18:58:00 +0000 (18:58 +0000)]
[InstCombine] Add vector udiv tests
Tests for X udiv C, where C >= signbit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324635
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Craig Topper [Thu, 8 Feb 2018 18:55:14 +0000 (18:55 +0000)]
[SelectionDAG] Add a helper function for creating a boolean constant based on the target's boolean content
Many in SimplifySetCC and FoldSetCC try to create true or false constants. Some of them query getBooleanContents to figure out whether to use all ones or just 1 for true. But many places do not check and just use 1 without ensuring the VT has an i1 scalar type. Note sure if those places only trigger before type legalization so they only see an i1
type?
To cleanup the inconsistency and reduce some duplicated code, this patch adds a getBoolConstant method to SelectionDAG that takes are of querying getBooleanContents and doing the right thing.
Differential Revision: https://reviews.llvm.org/D43037
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324634
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Vedant Kumar [Thu, 8 Feb 2018 18:46:49 +0000 (18:46 +0000)]
Simplify function prototypes in bugpoint, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324633
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Douglas Yung [Thu, 8 Feb 2018 18:45:16 +0000 (18:45 +0000)]
Change "UNSUPPORTED: windows" to be "UNSUPPORTED: system-windows" so that test is actually skipped on Windows.
Reviewed by Paul Robinson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324632
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Simon Pilgrim [Thu, 8 Feb 2018 18:36:01 +0000 (18:36 +0000)]
[InstCombine] Add m_Negative pattern matching
Allows us to add non-uniform constant vector support for "X urem C -> X < C ? X : X - C, where C >= signbit."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324631
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Craig Topper [Thu, 8 Feb 2018 18:34:25 +0000 (18:34 +0000)]
[X86] Add a few new test cases for shrunkblend combine
One of them shows a missed opportunity to use SimplifyDemandedBits on the condition when its used by multiple vselects.
The other is a case we shouldn't optimize because the condition has a non-vselect use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324630
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Simon Pilgrim [Thu, 8 Feb 2018 18:10:08 +0000 (18:10 +0000)]
[InstCombine] Add vector urem tests.
Improve coverage of InstCombiner::visitURem for vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324629
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Vedant Kumar [Thu, 8 Feb 2018 18:02:27 +0000 (18:02 +0000)]
Use ranged for loops in TypeFinder.cpp, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324628
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Simon Pilgrim [Thu, 8 Feb 2018 17:54:24 +0000 (17:54 +0000)]
[InstCombine] Regenerate vector mul tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324627
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Daniel Neilson [Thu, 8 Feb 2018 17:33:08 +0000 (17:33 +0000)]
[LoopIdiom] Be more aggressive when setting alignment in memcpy
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
LoopIdiom pass to cease using the old IRBuilder CreateMemCpy single-alignment APIs in
favour of the new API that allows setting source and destination alignments independently.
This allows us to be slightly more aggressive in setting the alignment of memcpy calls that
loop idiom creates.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324626
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Erich Keane [Thu, 8 Feb 2018 17:11:32 +0000 (17:11 +0000)]
Fix signed/unsigned compare warning I introduced
'size' of a vector is unsigned, and I accidentially compared
it to an int through GTEST. I switched it to unsigned, which
is the template parameter type anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324625
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Erich Keane [Thu, 8 Feb 2018 16:48:54 +0000 (16:48 +0000)]
[ARM] Add 'fillValidCPUArchList' to ARM targets
This is a support change for a CFE change (https://reviews.llvm.org/D42978)
that allows march and -target-cpu to list the valid targets in a note. The changes
are limited to the ARM/AArch64, since this is the only target that gets the CPU
list from LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324623
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Jonas Devlieghere [Thu, 8 Feb 2018 16:31:42 +0000 (16:31 +0000)]
[dsymutil] Use llvm::sys::path to join bundle path.
When processing a dSYM bundle, use llvm::sys::path to join the different
path components instead of using a string with hard coded forward
slashes as separators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324622
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Jonas Devlieghere [Thu, 8 Feb 2018 16:31:01 +0000 (16:31 +0000)]
[dwarfdump] Normalize input path.
Before this patch, llvm-dwarfdump would reject `bundel.dSYM/` as input,
while `bundel.dSYM` was accepted. The reason is that `path::extension()`
returns an empty string for the former, leading to the argument not
being recognized as a dSYM bundle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324621
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Yaxun Liu [Thu, 8 Feb 2018 15:41:19 +0000 (15:41 +0000)]
[AMDGPU] Updae documentation about address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324617
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Sanjay Patel [Thu, 8 Feb 2018 15:32:28 +0000 (15:32 +0000)]
[SLPVectorizer] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324616
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Sanjay Patel [Thu, 8 Feb 2018 15:30:39 +0000 (15:30 +0000)]
[SLPVectorizer] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324615
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Sanjay Patel [Thu, 8 Feb 2018 15:28:49 +0000 (15:28 +0000)]
[SLPVectorizer] move RUN line to top-of-file; NFC
I was confused what we were checking because the RUN line was
in the middle of the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324614
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Simon Pilgrim [Thu, 8 Feb 2018 15:19:38 +0000 (15:19 +0000)]
[InstCombine] Fix issue with X udiv (POW2_C1 << N) for non-splat constant vectors
foldUDivShl was assuming that the input was a scalar or a splat constant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324613
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Sanjay Patel [Thu, 8 Feb 2018 15:16:26 +0000 (15:16 +0000)]
[SLPVectorizer] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324612
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Sanjay Patel [Thu, 8 Feb 2018 15:13:47 +0000 (15:13 +0000)]
[LoopVectorize] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324611
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Sanjay Patel [Thu, 8 Feb 2018 14:52:40 +0000 (14:52 +0000)]
[ValueTracking] don't crash when assumptions conflict (PR36270)
The last assume in the test says that %B12 is 0.
The first assume says that %and1 is less than %B12.
Therefore, %and1 is unsigned less than 0...does not compute.
That means this line:
Known.Zero.setHighBits(RHSKnown.countMinLeadingZeros() + 1);
...tries to set more bits than exist.
Differential Revision: https://reviews.llvm.org/D43052
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324610
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Simon Pilgrim [Thu, 8 Feb 2018 14:46:10 +0000 (14:46 +0000)]
[InstCombine] Fix issue with X udiv 2^C -> X >> C for non-splat constant vectors
foldUDivPow2Cst was assuming that the input was a scalar or a splat constant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324608
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Oliver Stannard [Thu, 8 Feb 2018 14:31:22 +0000 (14:31 +0000)]
[ARM] Re-commit r324600 with fixed LLVMBuild.txt
ARMDisassembler now depends on the banked register tables in ARMUtils, so the
LLVMBuild.txt needed updating to reflect this.
Original commit mesage:
[ARM] Fix disassembly of invalid banked register moves
When disassembling banked register move instructions, we don't have an
assembly syntax for the unallocated register numbers, so we have to
return Fail rather than SoftFail. Previously we were returning SoftFail,
then crashing in the InstPrinter as we have no way to represent these
encodings in an assembly string.
This also switches the decoder to use the table-generated list of banked
registers, removing the duplicated list of encodings.
Differential revision: https://reviews.llvm.org/D43066
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324606
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Simon Pilgrim [Thu, 8 Feb 2018 14:24:26 +0000 (14:24 +0000)]
Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324605
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Oliver Stannard [Thu, 8 Feb 2018 14:21:28 +0000 (14:21 +0000)]
Revert r324600 as it breaks a buildbot
The broken bot (clang-ppc64le-linux-multistage) is doign a shared-object build,
so I guess using lookupBankedRegByEncoding in the disassembler is a layering
violation?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324604
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Simon Pilgrim [Thu, 8 Feb 2018 14:10:01 +0000 (14:10 +0000)]
[InstCombine] Improve mul(x, pow2) -> shl combine for vector constants
Refactor getLogBase2Vector into getLogBase2 to accept all scalars/vectors. Generalize from ConstantDataVector to support all constant vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324603
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Alexander Ivchenko [Thu, 8 Feb 2018 13:16:42 +0000 (13:16 +0000)]
[x86] Add test/CodeGen/X86/vmaskmov-offset.ll. NFC.
Needed for checking current code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324601
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Oliver Stannard [Thu, 8 Feb 2018 13:06:08 +0000 (13:06 +0000)]
[ARM] Fix disassembly of invalid banked register moves
When disassembling banked register move instructions, we don't have an
assembly syntax for the unallocated register numbers, so we have to
return Fail rather than SoftFail. Previously we were returning SoftFail,
then crashing in the InstPrinter as we have no way to represent these
encodings in an assembly string.
This also switches the decoder to use the table-generated list of banked
registers, removing the duplicated list of encodings.
Differential revision: https://reviews.llvm.org/D43066
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324600
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Jonas Devlieghere [Thu, 8 Feb 2018 11:58:16 +0000 (11:58 +0000)]
[test][dsymutil] Fix tests for Windows bots.
The UNSUPPORTED directive was not honored by the bot, presumably because
of the FIXME above it. This moves the comment down and removes the
remaining update check from basic-linking-x86.test.
This should un-break: llvm-clang-x86_64-expensive-checks-win/builds/7798/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324598
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Alexander Ivchenko [Thu, 8 Feb 2018 11:45:36 +0000 (11:45 +0000)]
Add missed PostDominatorTree analysis dependency to GVN hoist pass.
Summary:
GVN hoist pass is using PostDominatorTree analysis, therefore the analysis
should be listed in the pass initialization as a dependency.
Reviewed By: sebpop
Differential Revision: https://reviews.llvm.org/D43007
Author: ashlykov <arkady.shlykov@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324597
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Gadi Haber [Thu, 8 Feb 2018 11:16:02 +0000 (11:16 +0000)]
[X86][MC]: Adding test coverage of MC encoding for several small extensions.<NFC>
NFC.
Adding MC regressions tests to cover several small x86 extensions as follows:
CLWB, CLZERO, F16C, INVPCID, PKU, POPCNT, RTM, SGX, SHA, SVM, VMFUNC, VTX
This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952
Reviewers: RKSimon, craig.topper, zvi, AndreiGrischenko
Differential Revision: https://reviews.llvm.org/D41388
Change-Id: I254508cd17faca00b780be0fc2abf6c71b61faab
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324595
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Jonas Devlieghere [Thu, 8 Feb 2018 10:48:54 +0000 (10:48 +0000)]
Re-land [dsymutil] Upstream update feature
This commit attempts to re-land the r324480 which was reverted in
r324493 because it broke the Windows bots. For now I disabled the two
update tests on Windows until I'm able to debug this.
Differential revision: https://reviews.llvm.org/D42880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324592
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Serguei Katkov [Thu, 8 Feb 2018 10:34:08 +0000 (10:34 +0000)]
[Loop Predication] Teach LP about reverse loops with uge and sge latch conditions
Add support of uge and sge latch condition to Loop Prediction for
reverse loops.
Reviewers: apilipenko, mkazantsev, sanjoy, anna
Reviewed By: anna
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324589
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Clement Courbet [Thu, 8 Feb 2018 09:41:50 +0000 (09:41 +0000)]
[X86] Fix compilation of r324580.
@ctopper Can you check that the fix is correct ?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324586
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Stefan Maksimovic [Thu, 8 Feb 2018 09:31:48 +0000 (09:31 +0000)]
Revert accidental changes that snuck in r324584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324585
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Stefan Maksimovic [Thu, 8 Feb 2018 09:25:17 +0000 (09:25 +0000)]
[mips] Define certain instructions in microMIPS32r3
Instructions affected:
mthc1, mfhc1, add.d, sub.d, mul.d, div.d,
mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d
These instructions are now defined for
microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td
since they shared their encoding with those already defined
in microMIPS32r6InstrInfo.td and have been therefore
removed from the latter file.
Some instructions present in MicroMipsInstrFPU.td which
did not have both AFGR64 and FGR64 variants defined have
been altered to do so.
Differential revision: https://reviews.llvm.org/D42738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324584
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Dylan McKay [Thu, 8 Feb 2018 09:17:11 +0000 (09:17 +0000)]
[AVR] Fix the testsuite after '%' changed to '$' in MIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324583
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Clement Courbet [Thu, 8 Feb 2018 08:46:48 +0000 (08:46 +0000)]
[TargetSchedule] Expose sub-units of a ProcResGroup in MCProcResourceDesc.
Summary:
Right now using a ProcResource automatically counts as usage of all
super ProcResGroups. All this is done during codegen, so there is no
way for schedulers to get this information at runtime.
This adds the information of which individual ProcRes units are
contained in a ProcResGroup in MCProcResourceDesc.
Reviewers: gchatelet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324582
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