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Dmytro Laktyushkin [Mon, 6 Jul 2020 14:54:37 +0000 (10:54 -0400)]
drm/amd/display: Clean up global sync param retrieval
[Why]
This change replaces older looping code in favor of these functions.
[How]
There are built in functions for extracting global sync params
during mode validation now.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Mon, 27 Jul 2020 01:08:22 +0000 (09:08 +0800)]
drm/amd/swsmu: allow asic to handle sensor type by itself
1. allow asic to handle sensor type by itself.
2. if not, use smu common sensor to handle it.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Mon, 27 Jul 2020 13:39:40 +0000 (16:39 +0300)]
drm/amd/powerplay: off by one bugs in smu_cmn_to_asic_specific_index()
These tables have _COUNT number of elements so the comparisons should be
>= instead of > to prevent reading one element beyond the end of the
array.
Fixes:
8264ee69f0d8 ("drm/amd/powerplay: drop unused code")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 24 Jul 2020 09:24:08 +0000 (17:24 +0800)]
drm/amd/powerplay: update driver if file for sienna_cichlid
Update sienna_cichlid driver if header and related files.
Support new smu metrics for pre & postDS frequency.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Changfeng [Fri, 24 Jul 2020 05:15:10 +0000 (13:15 +0800)]
drm/amd/powerplay: drop unnecessary message support check(v2)
Take back patch:drop unnecessary message support check
Because the gpu reset fail problem on renoir can be fixed by:
drm/amd/powerplay: skip invalid msg when smu set mp1 state
It needs to remove SWSMU_CODE_LAYER_L1 in smu_cmn.h to guard a clear
code layer.
Signed-off-by: changfeng <Changfeng.Zhu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 24 Jul 2020 02:34:22 +0000 (22:34 -0400)]
drm/amdgpu: update dec ring test for VCN 3.0
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Thu, 23 Jul 2020 15:07:52 +0000 (11:07 -0400)]
drm/amdgpu/jpeg3.0: remove extra asic type check
jpeg ip block is already selected based on ASIC type during set_ip_blocks.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 23 Jul 2020 07:26:27 +0000 (15:26 +0800)]
drm/amdgpu: update golden setting for sienna_cichlid
Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 21 Jul 2020 08:39:45 +0000 (16:39 +0800)]
drm/amd/powerplay: correct smu message for vf mode
Set valid_in_vf to false for the message not support in vf mode on
sienna cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 21 Jul 2020 05:13:39 +0000 (13:13 +0800)]
drm/amd/powerplay: add msg map for mode1 reset
Mapping Mode1Reset message for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 21 Jul 2020 06:01:53 +0000 (14:01 +0800)]
drm/amd/powerplay: skip invalid msg when smu set mp1 state
Some asic may not support for some message of set mp1 state.
If the return value of smu_send_smc_msg is -EINVAL, that means it failed
to send msg to smc as it can not map an valid message for the ASIC. And
with that case, smu_set_mp1_state should be skipped as those ASIC was in
fact do not support for that.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Wed, 22 Jul 2020 13:27:35 +0000 (21:27 +0800)]
drm/amd/powerplay: remove the dpm checking in the boot sequence
It's not necessary to retrieve the power features status when the
asic is booted up the first time. This patch can have the features
enablement status still checked in suspend/resume case and removed
from the first boot up sequence.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Changfeng [Tue, 21 Jul 2020 02:38:19 +0000 (10:38 +0800)]
Revert "drm/amd/powerplay: drop unnecessary message support check"
The below 3 messages are not supported on Renoir
SMU_MSG_PrepareMp1ForShutdown
SMU_MSG_PrepareMp1ForUnload
SMU_MSG_PrepareMp1ForReset
It needs to revert patch:
drm/amd/powerplay: drop unnecessary message support check
to avoid set mp1 state fail during gpu reset on renoir.
Signed-off-by: changfeng <Changfeng.Zhu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Guchun Chen [Mon, 20 Jul 2020 03:11:13 +0000 (11:11 +0800)]
drm/amdgpu: add printing after executing page reservation to eeprom
This will tell users if the faulty page has been written to
external eeprom device in dmesg log.
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Wed, 22 Jul 2020 01:40:11 +0000 (09:40 +0800)]
drm/amdgpu: expand sienna chichlid reg access support
Added dedicated 64bit reg read/write support
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Fri, 10 Jul 2020 08:37:58 +0000 (09:37 +0100)]
drm/amdgpu: fix spelling mistake "Falied" -> "Failed"
There is a spelling mistake in a DRM_ERROR error message. Fix it.
This got lost in a merge, restore the fix.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit
4afaa61db9cf5250b5734c2531b226e7b3a3d691)
Dave Airlie [Tue, 4 Aug 2020 21:41:23 +0000 (07:41 +1000)]
Merge tag 'drm-msm-next-2020-07-30' of https://gitlab.freedesktop.org/drm/msm into drm-next
Take 2 of msm-next pull, this version drops the OPP patch due to [1],
so I'll send the gpu opp/bw scaling patch after the OPP patch lands.
Since I had to force-push I took the opportunity to rebase on
drm-next, and since you already merged in 5.8-rc6 a few fixes from the
last cycle dropped out.
This time around:
* A bunch more a650/a640 (sm8150/sm8250) display and GPU enablement
and fixes
* Enable dpu dither block for 6bpc panels
* dpu suspend fixes
* dpu fix for cursor on 2nd display
* dsi/mdp5 enablement for sdm630/sdm636/sdm660
I also regenerated the register headers, which accounts for a good
bit of the size this time, because we hadn't re-synced the register
headers since the early days of a6xx bringup.
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/
Bernard [Tue, 21 Jul 2020 01:33:03 +0000 (09:33 +0800)]
drm/msm: use kthread_create_worker instead of kthread_run
Use kthread_create_worker to simplify the code and optimise
the manager struct: msm_drm_thread. With this change, we
could remove struct element (struct task_struct *thread &
struct kthread_worker worker), instead, use one point (struct
kthread_worker *worker).
Signed-off-by: Bernard Zhao <bernard@vivo.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Sun, 26 Jul 2020 11:12:04 +0000 (13:12 +0200)]
drm/msm/mdp5: Add MDP5 configuration for SDM636/660
This commit adds support for the MDP5 IP on Snapdragon
636/660.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Sun, 26 Jul 2020 11:12:03 +0000 (13:12 +0200)]
drm/msm/dsi: Add DSI configuration for SDM660
This also applies to sdm630/636 and their SDA
counterparts.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Sun, 26 Jul 2020 11:12:02 +0000 (13:12 +0200)]
drm/msm/mdp5: Add MDP5 configuration for SDM630
This commit adds support for the MDP5 IP on Snapdragon
630. The configuration is different from SDM660's, as
the latter one has two DSI outputs.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Sun, 26 Jul 2020 11:12:01 +0000 (13:12 +0200)]
drm/msm/dsi: Add phy configuration for SDM630/636/660
These SoCs make use of the 14nm phy, but at different
addresses than other 14nm units.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Fri, 10 Jul 2020 23:04:10 +0000 (19:04 -0400)]
drm/msm/a6xx: add A640/A650 hwcg
Initialize hardware clock-gating registers on A640 and A650 GPUs.
At least for A650, this solves some performance issues.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Fri, 10 Jul 2020 23:04:09 +0000 (19:04 -0400)]
drm/msm/a6xx: hwcg tables in gpulist
This will allow supporting different hwcg tables for a6xx.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Sat, 11 Jul 2020 00:47:31 +0000 (20:47 -0400)]
drm/msm/dpu: add SM8250 to hw catalog
This brings up basic video mode functionality for SM8250 DPU. Command mode
and dual mixer/intf configurations are not working, future patches will
address this. Scaler functionality and multiple planes is also untested.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Sat, 11 Jul 2020 00:47:30 +0000 (20:47 -0400)]
drm/msm/dpu: add SM8150 to hw catalog
This brings up basic video mode functionality for SM8150 DPU. Command mode
and dual mixer/intf configurations are not working, future patches will
address this. Scaler functionality and multiple planes is also untested.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
[fixup max_linewidth warning]
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Sat, 11 Jul 2020 00:47:29 +0000 (20:47 -0400)]
drm/msm/dpu: intf timing path for displayport
Calculate the correct timings for displayport, from downstream driver.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Sat, 11 Jul 2020 00:47:28 +0000 (20:47 -0400)]
drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3
This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Sat, 11 Jul 2020 00:47:27 +0000 (20:47 -0400)]
drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845
The INTF_INPUT_CTRL feature is not available on sdm845, so don't set it.
This also adds separate feature bits for INTF (based on downstream) instead
of using CTL feature bit for it, and removes the unnecessary NULL check in
the added bind_pingpong_blk function.
Fixes:
73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath for SC7180 target")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Sat, 11 Jul 2020 00:47:26 +0000 (20:47 -0400)]
drm/msm/dpu: move some sspp caps to dpu_caps
This isn't something that ever changes between planes, so move it to
dpu_caps struct. Making this change will allow more re-use in the
"SSPP sub blocks config" part of the catalog, in particular when adding
support for SM8150 and SM8250 which have different max_linewidth.
This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation
is not supported on the newest DPU versions. (note that decimation is not
implemented, so this changes nothing)
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Sat, 11 Jul 2020 00:47:25 +0000 (20:47 -0400)]
drm/msm/dpu: update UBWC config for sm8150 and sm8250
Update the UBWC registers to the right values for sm8150 and sm8250.
This removes broken dpu_hw_reset_ubwc, which doesn't work because the
"force blk offset to zero to access beginning of register region" hack is
copied from downstream, where mapped region starts 0x1000 below what is
used in the upstream driver.
Also simplifies the overly complicated change that was introduced in
e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Sat, 11 Jul 2020 00:47:24 +0000 (20:47 -0400)]
drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250
All DPU versions starting from 4.0 use the sdm845 version, so check for
that instead of checking each version individually. This chooses the right
function for sm8150 and sm8250.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Tue, 26 May 2020 03:25:13 +0000 (23:25 -0400)]
drm/msm/a6xx: set ubwc config for A640 and A650
This is required for A640 and A650 to be able to share UBWC-compressed
images with other HW such as display, which expect this configuration.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Tue, 7 Jul 2020 20:35:00 +0000 (13:35 -0700)]
drm/msm/adreno: un-open-code some packets
Small cleanup, lets not open-code bits/bitfields that are properly
defined in the rnndb xml (and therefore have builders in the generated
headers)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Tue, 7 Jul 2020 20:34:59 +0000 (13:34 -0700)]
drm/msm: sync generated headers
We haven't sync'd for a while.. pull in updates to get definitions for
some fields in pkt7 payloads.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Wed, 1 Jul 2020 03:09:57 +0000 (23:09 -0400)]
drm/msm/a6xx: add build_bw_table for A640/A650
This sets up bw tables for A640/A650 similar to A618/A630, 0 DDR bandwidth
vote, and the CNOC vote. A640 has the same CNOC addresses as A630 and was
working, but this is required for A650 to work.
Eventually the bw table should be filled by querying the interconnect
driver for each BW in the dts, but use these dummy tables for now.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Tue, 30 Jun 2020 00:10:06 +0000 (20:10 -0400)]
drm/msm/a6xx: fix crashstate capture for A650
A650 has a separate RSCC region, so dump RSCC registers separately, reading
them from the RSCC base. Without this change a GPU hang will cause a system
reset if CONFIG_DEV_COREDUMP is enabled.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Eric Anholt [Mon, 29 Jun 2020 18:19:21 +0000 (11:19 -0700)]
drm/msm: Quiet error during failure in optional resource mappings.
We don't expect to find vbif_nrt or regdma on sdm845, but were clogging
up dmesg with errors about it.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Eric Anholt [Mon, 29 Jun 2020 18:19:20 +0000 (11:19 -0700)]
drm/msm: Garbage collect unused resource _len fields.
Nothing was using the lengths of these ioremaps.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Wed, 15 Jul 2020 22:19:51 +0000 (15:19 -0700)]
drm/msm/dpu: fix/enable 6bpc dither with split-lm
If split-lm is used (for ex, on sdm845), we can have multiple ping-
pongs, but only a single phys encoder. We need to configure dithering
on each of them.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Kalyan Thota <kalyan_t@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Akhil P Oommen [Fri, 17 Jul 2020 14:34:18 +0000 (20:04 +0530)]
drm: msm: a6xx: fix gpu failure after system resume
On targets where GMU is available, GMU takes over the ownership of GX GDSC
during its initialization. So, move the refcount-get on GX PD before we
initialize the GMU. This ensures that nobody can collapse the GX GDSC
once GMU owns the GX GDSC. This patch fixes some GMU OOB errors seen
during GPU wake up during a system resume.
Reported-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rajendra Nayak [Thu, 9 Jul 2020 11:04:32 +0000 (16:34 +0530)]
drm/msm: dsi: Use OPP API to set clk/perf state
On SDM845 and SC7180 DSI needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
dev_pm_opp_set_rate() is designed to be equivalent to clk_set_rate()
for devices without an OPP table, hence the change works fine
on devices/platforms which only need to set a clock rate.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rajendra Nayak [Thu, 9 Jul 2020 11:04:31 +0000 (16:34 +0530)]
drm/msm/dpu: Use OPP API to set clk/perf state
On some qualcomm platforms DPU needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Wed, 1 Jul 2020 20:36:00 +0000 (13:36 -0700)]
drm/msm: ratelimit crtc event overflow error
This can happen a lot when things go pear shaped. Lets not flood dmesg
when this happens.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Sharat Masetty [Mon, 13 Jul 2020 12:41:42 +0000 (18:11 +0530)]
drm: msm: a6xx: send opp instead of a frequency
This patch changes the plumbing to send the devfreq recommended opp rather
than the frequency. Also consolidate and rearrange the code in a6xx to set
the GPU frequency and the icc vote in preparation for the upcoming
changes for GPU->DDR scaling votes.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Sharat Masetty [Mon, 13 Jul 2020 12:41:41 +0000 (18:11 +0530)]
dt-bindings: drm/msm/gpu: Document gpu opp table
Update documentation to list the gpu opp table bindings including the
newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Akhil P Oommen [Thu, 9 Jul 2020 20:31:55 +0000 (02:01 +0530)]
drm/msm: Fix a null pointer access in msm_gem_shrinker_count()
Adding an msm_gem_object object to the inactive_list before completing
its initialization is a bad idea because shrinker may pick it up from the
inactive_list. Fix this by making sure that the initialization is complete
before moving the msm_obj object to the inactive list.
This patch fixes the below error:
[10027.553044] Unable to handle kernel NULL pointer dereference at virtual address
0000000000000068
[10027.573305] Mem abort info:
[10027.590160] ESR = 0x96000006
[10027.597905] EC = 0x25: DABT (current EL), IL = 32 bits
[10027.614430] SET = 0, FnV = 0
[10027.624427] EA = 0, S1PTW = 0
[10027.632722] Data abort info:
[10027.638039] ISV = 0, ISS = 0x00000006
[10027.647459] CM = 0, WnR = 0
[10027.654345] user pgtable: 4k pages, 39-bit VAs, pgdp=
00000001e3a6a000
[10027.672681] [
0000000000000068] pgd=
0000000198c31003, pud=
0000000198c31003, pmd=
0000000000000000
[10027.693900] Internal error: Oops:
96000006 [#1] PREEMPT SMP
[10027.738261] CPU: 3 PID: 214 Comm: kswapd0 Tainted: G S 5.4.40 #1
[10027.745766] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT)
[10027.752472] pstate:
80c00009 (Nzcv daif +PAN +UAO)
[10027.757409] pc : mutex_is_locked+0x14/0x2c
[10027.761626] lr : msm_gem_shrinker_count+0x70/0xec
[10027.766454] sp :
ffffffc011323ad0
[10027.769867] x29:
ffffffc011323ad0 x28:
ffffffe677e4b878
[10027.775324] x27:
0000000000000cc0 x26:
0000000000000000
[10027.780783] x25:
ffffff817114a708 x24:
0000000000000008
[10027.786242] x23:
ffffff8023ab7170 x22:
0000000000000001
[10027.791701] x21:
ffffff817114a080 x20:
0000000000000119
[10027.797160] x19:
0000000000000068 x18:
00000000000003bc
[10027.802621] x17:
0000000004a34210 x16:
00000000000000c0
[10027.808083] x15:
0000000000000000 x14:
0000000000000000
[10027.813542] x13:
ffffffe677e0a3c0 x12:
0000000000000000
[10027.819000] x11:
0000000000000000 x10:
ffffff8174b94340
[10027.824461] x9 :
0000000000000000 x8 :
0000000000000000
[10027.829919] x7 :
00000000000001fc x6 :
ffffffc011323c88
[10027.835373] x5 :
0000000000000001 x4 :
ffffffc011323d80
[10027.840832] x3 :
ffffffff0477b348 x2 :
0000000000000000
[10027.846290] x1 :
ffffffc011323b68 x0 :
0000000000000068
[10027.851748] Call trace:
[10027.854264] mutex_is_locked+0x14/0x2c
[10027.858121] msm_gem_shrinker_count+0x70/0xec
[10027.862603] shrink_slab+0xc0/0x4b4
[10027.866187] shrink_node+0x4a8/0x818
[10027.869860] kswapd+0x624/0x890
[10027.873097] kthread+0x11c/0x12c
[10027.876424] ret_from_fork+0x10/0x18
[10027.880102] Code:
f9000bf3 910003fd aa0003f3 d503201f (
f9400268)
[10027.886362] ---[ end trace
df5849a1a3543251 ]---
[10027.891518] Kernel panic - not syncing: Fatal exception
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Kalyan Thota [Thu, 25 Jun 2020 12:16:59 +0000 (17:46 +0530)]
drm/msm/dpu: add support for dither block in display
This change enables dither block for primary interface
in display.
Enabled for 6bpc in the current version.
Changes in v1:
- Remove redundant error checks (Rob).
Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Kristian H. Kristensen <hoegsberg@google.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Wed, 15 Jul 2020 19:07:30 +0000 (12:07 -0700)]
drm/msm/adreno: fix gpu probe if no interconnect-names
If there is no interconnect-names, but there is an interconnects
property, then of_icc_get(dev, "gfx-mem"); would return an error
rather than NULL.
Also, if there is no interconnect-names property, there will never
be a ocmem path. But of_icc_get(dev, "ocmem") would return -EINVAL
instead of -ENODATA. Just don't bother trying in this case.
v2: explicity check for interconnect-names property
Fixes:
08af4769c7d2 ("drm/msm: handle for EPROBE_DEFER for of_icc_get")
Fixes:
00bb9243d346 ("drm/msm/gpu: add support for ocmem interconnect path")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Dave Airlie [Thu, 30 Jul 2020 19:25:42 +0000 (05:25 +1000)]
Merge tag 'drm-intel-next-2020-07-15' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
drm/i915 features for v5.9, batch #2
Highlights:
- Very early DG1 enabling (Abdiel, Lucas, Anusha)
Gem/GT:
- Fix spinlock recursion on signaling a signaled request (Chris)
- Perf: Use GTT when saving/restoring engine GPR (Umesh Nerlige Ramappa)
- SSEU refactoring, debugfs move under gt/ (Daniele, Venkata Sandeep Dhanalakota)
- Various GT refactoring and cleanup, preparation for future changes (Daniele)
- Adjust HuC state accordingly after GuC fetch error (Michał Winiarski)
- UC debugfs updates (Michał Winiarski)
- Only revoke the GGTT mmappings on aperture detiling changes (Chris)
- Only revoke mmap handlers if active (Chris)
- Split the context's obj:vma lut into its own mutex (Chris)
- Various memory, mmap and performance optimisations (Chris)
- Improve system stability in case of false CS events (Chris)
- Various refactorings and cleanup (Chris)
- Always reset the engine on execlist failures (Chris)
- Trace placement of timeline HWSP (Chris)
- Update dma-attributes for our sg DMA (Chris)
Display:
- TGL CDCLK workaround tweaks to unbreak 8K display support (Stanislav)
- A number of FBC fixes, along with i865 FBC enabling (Ville)
- Validate MST modes against PBN limits (Lyude, Shawn Lee)
- Do not access non-existing swizzle registers (Lucas)
- Revert GEN11+ HBR3 rate fix that caused issues on TGL (Matt Atwood)
- Update TGL+ combo phy initialization to match spec update (José)
- Fix HDCP Content Protection property state machine (Anshuman)
- Fix HDCP revoked keys handling (Ram)
- Improve DDI BUF status checks and waits (Manasi)
- Various SDVO+HDMI+DVI fixes around colorimetry, clocking, pixel repeat etc. (Ville)
- DP voltage swing function refactoring (José)
- WARN if max vswing/pre-emphasis violates the DP spec (Ville)
Other:
- Add new EHL PCI IDs (José)
- Unify struct intel_digital_port variable naming (Lucas)
- Various taint updates to aid debugging and improve CI (Michał Winiarski)
- Straggler conversions to new mmio register accessors (Daniele)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87a70029vz.fsf@intel.com
Kalyan Thota [Thu, 25 Jun 2020 12:45:53 +0000 (18:15 +0530)]
drm/msm/dpu: enumerate second cursor pipe for external interface
Setup an RGB HW pipe as cursor which can be used on
secondary interface.
For SC7180 2 HW pipes are enumerated as cursors
1 - primary interface
2 - secondary interface
Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Kalyan Thota [Thu, 18 Jun 2020 14:01:24 +0000 (19:31 +0530)]
drm/msm/dpu: ensure device suspend happens during PM sleep
"The PM core always increments the runtime usage counter
before calling the ->suspend() callback and decrements it
after calling the ->resume() callback"
DPU and DSI are managed as runtime devices. When
suspend is triggered, PM core adds a refcount on all the
devices and calls device suspend, since usage count is
already incremented, runtime suspend was not getting called
and it kept the clocks on which resulted in target not
entering into XO shutdown.
Add changes to force suspend on runtime devices during pm sleep.
Changes in v1:
- Remove unnecessary checks in the function
_dpu_kms_disable_dpu (Rob Clark).
Changes in v2:
- Avoid using suspend_late to reset the usagecount
as suspend_late might not be called during suspend
call failures (Doug).
Changes in v3:
- Use force suspend instead of managing device usage_count
via runtime put and get API's to trigger callbacks (Doug).
Changes in v4:
- Check the return values of pm_runtime_force_suspend and
pm_runtime_force_resume API's and pass appropriately (Doug).
Changes in v5:
- With v4 patch, test cycle has uncovered issues in device resume.
On bubs: cmd tx failures were seen as SW is sending panel off
commands when the dsi resources are turned off.
Upon suspend, DRM driver will issue a NULL composition to the
dpu, followed by turning off all the HW blocks.
v5 changes will serialize the NULL commit and resource unwinding
by handling them under PM prepare and PM complete phases there by
ensuring that clks are on when panel off commands are being
processed.
Changes in v6:
- Use drm_mode_config_helper_suspend/resume() instead of legacy API
drm_atomic_helper_suspend/resume() (Doug).
Trigger runtime callbacks from the suspend/resume call to turn
off the resources.
Changes in v7:
- Add "__maybe_unused" to the functions to avoid compilation
failures. Cleanup unnecessary configs (Doug).
Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Mon, 13 Jul 2020 22:53:42 +0000 (18:53 -0400)]
drm/msm: handle for EPROBE_DEFER for of_icc_get
Check for errors instead of silently not using icc if the msm driver
probes before the interconnect driver.
Allow ENODATA for ocmem path, as it is optional and this error
is returned when "gfx-mem" path is provided but not "ocmem".
Because msm_gpu_cleanup assumes msm_gpu_init has been called, the icc path
init needs to be after msm_gpu_init for the error path to work.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Mon, 13 Jul 2020 22:53:41 +0000 (18:53 -0400)]
drm/msm: reset devfreq freq_table/max_state before devfreq_add_device
These never get set back to 0 when probing fails, so an attempt to probe
again results in broken behavior. Fix the problem by setting thse to zero
before they are used.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Jonathan Marek [Mon, 13 Jul 2020 22:53:40 +0000 (18:53 -0400)]
drm/msm: fix unbalanced pm_runtime_enable in adreno_gpu_{init, cleanup}
adreno_gpu_init calls pm_runtime_enable, so adreno_gpu_cleanup needs to
call pm_runtime_disable.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Dave Airlie [Tue, 28 Jul 2020 04:17:36 +0000 (14:17 +1000)]
drm/ttm/nouveau: don't call tt destroy callback on alloc failure.
This is confusing, and from my reading of all the drivers only
nouveau got this right.
Just make the API act under driver control of it's own allocation
failing, and don't call destroy, if the page table fails to
create there is nothing to cleanup here.
(I'm willing to believe I've missed something here, so please
review deeply).
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200728041736.20689-1-airlied@gmail.com
Dave Airlie [Tue, 28 Jul 2020 03:42:54 +0000 (13:42 +1000)]
drm/ttm: ttm_bo_swapout_all doesn't use it's argument.
Just drop the argument from this.
This does ask the question if this is the function vmwgfx
should be using or should it be doing an evict all like
the other drivers.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200728034254.20114-1-airlied@gmail.com
Dave Airlie [Tue, 28 Jul 2020 04:51:29 +0000 (14:51 +1000)]
drm/ttm: drop unusued function declaration
This was removed in
f5a9a9383f279 ("drm/ttm: remove TTM_MEMTYPE_FLAG_CMA")
but the the declaration was left dangling.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200728045129.21065-1-airlied@gmail.com
Dave Airlie [Tue, 28 Jul 2020 04:00:03 +0000 (14:00 +1000)]
drm/ttm: make ttm_tt unbind function return void.
The return value just led to BUG_ON, I think if a driver wants
to BUG_ON here it can do it itself. (don't BUG_ON).
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200728040003.20398-1-airlied@gmail.com
Dave Airlie [Mon, 27 Jul 2020 02:32:12 +0000 (12:32 +1000)]
Merge tag 'amd-drm-next-5.9-2020-07-24' of git://people.freedesktop.org/~agd5f/linux into drm-next
amd-drm-next-5.9-2020-07-24:
amdgpu:
- Misc sienna cichlid fixes
- Final bits of swSMU cleanup
- Misc display fixes
- Misc VCN fixes
- Eeprom i2c cleanup
- Drop amd vrr_range debugfs in favor of core drm
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200724205712.3913-1-alexander.deucher@amd.com
Dave Airlie [Mon, 27 Jul 2020 02:03:52 +0000 (12:03 +1000)]
Merge branch 'linux-5.9' of git://github.com/skeggsb/linux into drm-next
- Conversion of all push buffer emission to a new set of macros, with
better safety, sanity-checking, debug ability, and the use of NVIDIA's
class headers. The headers have been trimmed to just what we use as
they're rather extensive, the full versions can be found on NVIDIA's
github[1].
- Proper push buffer space management for EVO/NVD channels.
- Fixes to firmware loading behaviour in odd situations (various
combinations of missing/incompatible FW).
- runpm reference leak fixes
- crc compile fixes without debugfs
- 2MiB system memory pages support on Pascal and newer
- misc other cleanups
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Ben Skeggs <skeggsb@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/
Lyude Paul [Mon, 20 Jul 2020 20:56:56 +0000 (16:56 -0400)]
drm/nouveau/kms/nv50-: Fix CRC-related compile errors with debugfs disabled
Looks like I made the mistake of forgetting to check whether or not this
would build without CONFIG_DEBUG_FS, as the Kbuild bot reported some
issues building with tegra_defconfig:
In file included from drivers/gpu/drm/nouveau/nouveau_display.c:47:
./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function
‘nv50_head_crc_late_register’:
./drivers/gpu/drm/nouveau/dispnv50/crc.h:106:47: error: parameter name
omitted
106 | static inline int nv50_head_crc_late_register(struct nv50_head *) {}
| ^~~~~~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h:106:54: warning: no return
statement in function returning non-void [-Wreturn-type]
106 | static inline int nv50_head_crc_late_register(struct nv50_head *) {}
| ^~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function
‘nv50_crc_handle_vblank’:
./drivers/gpu/drm/nouveau/dispnv50/crc.h:108:57: warning: ‘return’ with
a value, in function returning void [-Wreturn-type]
108 | nv50_crc_handle_vblank(struct nv50_head *head) { return 0; }
| ^
./drivers/gpu/drm/nouveau/dispnv50/crc.h:108:1: note: declared here
108 | nv50_crc_handle_vblank(struct nv50_head *head) { return 0; }
| ^~~~~~~~~~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function
‘nv50_crc_atomic_check’:
./drivers/gpu/drm/nouveau/dispnv50/crc.h:111:23: error: parameter name
omitted
111 | nv50_crc_atomic_check(struct nv50_head *, struct nv50_head_atom *,
| ^~~~~~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h:111:43: error: parameter name
omitted
111 | nv50_crc_atomic_check(struct nv50_head *, struct nv50_head_atom *,
| ^~~~~~~~~~~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h:112:9: error: parameter name
omitted
112 | struct nv50_head_atom *) {}
| ^~~~~~~~~~~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h:112:16: warning: no return
statement in function returning non-void [-Wreturn-type]
112 | struct nv50_head_atom *) {}
| ^~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function
‘nv50_crc_atomic_stop_reporting’:
./drivers/gpu/drm/nouveau/dispnv50/crc.h:114:32: error: parameter name
omitted
114 | nv50_crc_atomic_stop_reporting(struct drm_atomic_state *) {}
| ^~~~~~~~~~~~~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function
‘nv50_crc_atomic_prepare_notifier_contexts’:
./drivers/gpu/drm/nouveau/dispnv50/crc.h:116:43: error: parameter name
omitted
116 | nv50_crc_atomic_prepare_notifier_contexts(struct drm_atomic_state *) {}
| ^~~~~~~~~~~~~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function
‘nv50_crc_atomic_start_reporting’:
./drivers/gpu/drm/nouveau/dispnv50/crc.h:118:33: error: parameter name
omitted
118 | nv50_crc_atomic_start_reporting(struct drm_atomic_state *) {}
| ^~~~~~~~~~~~~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function
‘nv50_crc_atomic_set’:
./drivers/gpu/drm/nouveau/dispnv50/crc.h:120:21: error: parameter name
omitted
120 | nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {}
| ^~~~~~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h:120:41: error: parameter name
omitted
120 | nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {}
| ^~~~~~~~~~~~~~~~~~~~~~~
./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function
‘nv50_crc_atomic_clr’:
./drivers/gpu/drm/nouveau/dispnv50/crc.h:122:21: error: parameter name
omitted
122 | nv50_crc_atomic_clr(struct nv50_head *) {}
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/nouveau/nouveau_display.c: In function
‘nouveau_framebuffer_new’:
drivers/gpu/drm/nouveau/nouveau_display.c:286:15: warning: variable
‘width’ set but not used [-Wunused-but-set-variable]
286 | unsigned int width, height, i;
| ^~~~~
So, fix the inline function declarations we use in
drm/drivers/gpu/drm/nouveau/dispnv50/crc.h when CONFIG_DEBUG_FS is
enabled.
Fixes:
12885ecbfe62 ("drm/nouveau/kms/nvd9-: Add CRC support")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 22 Jul 2020 07:21:59 +0000 (17:21 +1000)]
drm/nouveau/fence: use NVIDIA's headers for read()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Mon, 20 Jul 2020 01:19:26 +0000 (11:19 +1000)]
drm/nouveau/fence: use NVIDIA's headers for sync()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Mon, 20 Jul 2020 01:19:14 +0000 (11:19 +1000)]
drm/nouveau/fence: use NVIDIA's headers for emit()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Mon, 22 Jun 2020 09:27:00 +0000 (19:27 +1000)]
drm/nouveau/svm: use NVIDIA's headers for migrate_clear()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Mon, 22 Jun 2020 09:16:31 +0000 (19:16 +1000)]
drm/nouveau/svm: use NVIDIA's headers for migrate_copy()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Mon, 22 Jun 2020 07:07:31 +0000 (17:07 +1000)]
drm/nouveau/bo: use NVIDIA's headers for move move()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Mon, 22 Jun 2020 06:29:45 +0000 (16:29 +1000)]
drm/nouveau/bo: use NVIDIA's headers for move init()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Mon, 22 Jun 2020 04:27:41 +0000 (14:27 +1000)]
drm/nouveau/fbcon/nv50-: use NVIDIA's headers for fillrect()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Mon, 22 Jun 2020 04:16:03 +0000 (14:16 +1000)]
drm/nouveau/fbcon/nv50-: use NVIDIA's headers for copyarea()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Mon, 22 Jun 2020 04:12:07 +0000 (14:12 +1000)]
drm/nouveau/fbcon/nv50-: use NVIDIA's headers for imageblit()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 19 Jul 2020 21:59:22 +0000 (07:59 +1000)]
drm/nouveau/fbcon/nv50-: use NVIDIA's headers for accel_init()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 19 Jul 2020 23:49:39 +0000 (09:49 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core crc_set_ctx()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 19 Jul 2020 21:56:31 +0000 (07:56 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core crc_set_src()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 02:46:31 +0000 (12:46 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_or()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 02:40:59 +0000 (12:40 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_procamp()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 02:35:48 +0000 (12:35 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_dither()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 02:31:42 +0000 (12:31 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_ovly()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 02:31:24 +0000 (12:31 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_base()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 02:16:24 +0000 (12:16 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_curs_clr()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 02:10:42 +0000 (12:10 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_curs_set()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 01:59:54 +0000 (11:59 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_core_clr()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 01:59:09 +0000 (11:59 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_core_set()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 01:47:21 +0000 (11:47 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_olut_clr()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 01:44:39 +0000 (11:44 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_olut_set()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 01:25:06 +0000 (11:25 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_mode()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 00:55:21 +0000 (10:55 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_view()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 07:40:51 +0000 (17:40 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core or_get_caps()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sat, 20 Jun 2020 08:09:59 +0000 (18:09 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core or_ctrl()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sat, 20 Jun 2020 07:59:39 +0000 (17:59 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core wndw_owner()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sat, 20 Jun 2020 07:39:00 +0000 (17:39 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core update()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 07:24:27 +0000 (17:24 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core ntfy_wait_done()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sat, 20 Jun 2020 07:55:22 +0000 (17:55 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core caps_init()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sun, 21 Jun 2020 07:21:16 +0000 (17:21 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core ntfy_init()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sat, 20 Jun 2020 07:51:49 +0000 (17:51 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for core init()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sat, 20 Jun 2020 05:53:59 +0000 (15:53 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw update()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sat, 20 Jun 2020 05:46:52 +0000 (15:46 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw blend_set()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sat, 20 Jun 2020 04:24:57 +0000 (14:24 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw scale_set()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Sat, 20 Jun 2020 04:21:59 +0000 (14:21 +1000)]
drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw image_clr()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>