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Jordan Rupprecht [Mon, 10 Jun 2019 18:35:01 +0000 (18:35 +0000)]
[llvm-objcopy] Fix SHT_GROUP ordering.
Summary:
When llvm-objcopy sorts sections during finalization, it only sorts based on the offset, which can cause the group section to come after the sections it contains. This causes link failures when using gold to link objects created by llvm-objcopy.
Fix this for now by copying GNU objcopy's behavior of placing SHT_GROUP sections first. In the future, we may want to remove this sorting entirely to more closely preserve the input file layout.
This fixes https://bugs.llvm.org/show_bug.cgi?id=42052.
Reviewers: jakehehrlich, jhenderson, MaskRay, espindola, alexshap
Reviewed By: MaskRay
Subscribers: phuongtrang148993, emaste, arichardson, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362973
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Sanjay Patel [Mon, 10 Jun 2019 18:19:05 +0000 (18:19 +0000)]
[Analysis] add unit test file for VectorUtils; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362972
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Philip Reames [Mon, 10 Jun 2019 17:51:13 +0000 (17:51 +0000)]
Prepare for multi-exit LFTR [NFC]
This change does the plumbing to wire an ExitingBB parameter through the LFTR implementation, and reorganizes the code to work in terms of a set of individual loop exits. Most of it is fairly obvious, but there's one key complexity which makes it worthy of consideration. The actual multi-exit LFTR patch is in D62625 for context.
Specifically, it turns out the existing code uses the backedge taken count from before a IV is widened. Oddly, we can end up with a different (more expensive, but semantically equivelent) BE count for the loop when requerying after widening. For the nestedIV example from elim-extend, we end up with the following BE counts:
BEFORE: (-2 + (-1 * %innercount) + %limit)
AFTER: (-1 + (sext i32 (-1 + %limit) to i64) + (-1 * (sext i32 %innercount to i64))<nsw>)
This is the only test in tree which seems sensitive to this difference. The actual result of using the wider BETC on this example is that we actually produce slightly better code. :)
In review, we decided to accept that test change. This patch is structured to preserve the old behavior, but a separate change will immediate follow with the behavior change. (I wanted it separate for problem attribution purposes.)
Differential Revision: https://reviews.llvm.org/D62880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362971
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Wolfgang Pieb [Mon, 10 Jun 2019 17:50:24 +0000 (17:50 +0000)]
[ELF][llvm-objdump] Treat dynamic tag values as virtual addresses instead of offsets
The ELF gABI requires the tag values of DT_REL, DT_RELA and DT_JMPREL to be
treated as virtual addresses. They were treated as offsets. Fixes PR41832.
Differential Revision: https://reviews.llvm.org/D62972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362969
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Sameer AbuAsal [Mon, 10 Jun 2019 17:15:45 +0000 (17:15 +0000)]
[RISCV] Replace map with set in getReqFeatures
Summary:
Use a set in getReqFeatures() in RISCVCompressInstEmitter instead of a map
because the index we save is not needed.
This also fixes bug 41666.
Reviewers: llvm-commits, apazos, asb, nickdesaulniers
Reviewed By: asb
Subscribers: Jim, nickdesaulniers, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362968
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Jordan Rupprecht [Mon, 10 Jun 2019 17:00:49 +0000 (17:00 +0000)]
[docs] Add 'git llvm revert' to getting started guide
Summary: This documents `git llvm revert rNNNNNN` in the getting started guide for broader visibility.
Reviewers: jyknight, mehdi_amini
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362966
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Andrea Di Biagio [Mon, 10 Jun 2019 16:56:25 +0000 (16:56 +0000)]
[llvm-mca] Enable bottleneck analysis when flag -all-views is specified.
Bottleneck Analysis is one of the many views available in llvm-mca. Therefore,
it should be enabled when flag -all-views is passed in input to the tool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362964
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Francis Visoiu Mistrih [Mon, 10 Jun 2019 16:53:37 +0000 (16:53 +0000)]
[FastISel] Skip creating unnecessary vregs for arguments
This behavior was added in r130928 for both FastISel and SD, and then
disabled in r131156 for FastISel.
This re-enables it for FastISel with the corresponding fix.
This is triggered only when FastISel can't lower the arguments and falls
back to SelectionDAG for it.
FastISel contains a map of "register fixups" where at the end of the
selection phase it replaces all uses of a register with another
register that FastISel sometimes pre-assigned. Code at the end of
SelectionDAGISel::runOnMachineFunction is doing the replacement at the
very end of the function, while other pieces that come in before that
look through the MachineFunction and assume everything is done. In this
case, the real issue is that the code emitting COPY instructions for the
liveins (physreg to vreg) (EmitLiveInCopies) is checking if the vreg
assigned to the physreg is used, and if it's not, it will skip the COPY.
If a register wasn't replaced with its assigned fixup yet, the copy will
be skipped and we'll end up with uses of undefined registers.
This fix moves the replacement of registers before the emission of
copies for the live-ins.
The initial motivation for this fix is to enable tail calls for
swiftself functions, which were blocked because we couldn't prove that
the swiftself argument (which is callee-save) comes from a function
argument (live-in), because there was an extra copy (vreg to vreg).
A few tests are affected by this:
* llvm/test/CodeGen/AArch64/swifterror.ll: we used to spill x21
(callee-save) but never reload it because it's attached to the return.
We now don't even spill it anymore.
* llvm/test/CodeGen/*/swiftself.ll: we tail-call now.
* llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll: I believe this
test was not really testing the right thing, but it worked because the
same registers were re-used.
* llvm/test/CodeGen/ARM/cmpxchg-O0.ll: regalloc changes
* llvm/test/CodeGen/ARM/swifterror.ll: get rid of a copy
* llvm/test/CodeGen/Mips/*: get rid of spills and copies
* llvm/test/CodeGen/SystemZ/swift-return.ll: smaller stack
* llvm/test/CodeGen/X86/atomic-unordered.ll: smaller stack
* llvm/test/CodeGen/X86/swifterror.ll: same as AArch64
* llvm/test/DebugInfo/X86/dbg-declare-arg.ll: stack size changed
Differential Revision: https://reviews.llvm.org/D62361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362963
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Cameron McInally [Mon, 10 Jun 2019 16:05:25 +0000 (16:05 +0000)]
[ExecutionEngine] Fix rL362941: Add UnaryOperator visitor to the interpreter
Missed break statements. This was D62881.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362958
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Piotr Sobczak [Mon, 10 Jun 2019 15:58:51 +0000 (15:58 +0000)]
[AMDGPU] Optimize image_[load|store]_mip
Summary:
Replace image_load_mip/image_store_mip
with image_load/image_store if lod is 0.
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63073
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362957
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Simon Tatham [Mon, 10 Jun 2019 15:58:19 +0000 (15:58 +0000)]
Revert rL362953 and its followup rL362955.
These caused a build failure because I managed not to notice they
depended on a later unpushed commit in my current stack. Sorry about
that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362956
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Simon Tatham [Mon, 10 Jun 2019 15:41:58 +0000 (15:41 +0000)]
[ARM] Add the non-MVE instructions in Arm v8.1-M.
This should have been part of r362953, but I had a finger-trouble
incident and committed the old rather than new version of the patch.
Sorry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362955
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Sanjay Patel [Mon, 10 Jun 2019 15:39:00 +0000 (15:39 +0000)]
[InstCombine] allow unordered preds when canonicalizing to fabs()
We have a known-never-nan value via 'nnan', so an unordered predicate
is the same as its ordered sibling.
Similar to:
rL362937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362954
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Simon Tatham [Mon, 10 Jun 2019 15:36:34 +0000 (15:36 +0000)]
[ARM] Add the non-MVE instructions in Arm v8.1-M.
This adds support for the new family of conditional selection /
increment / negation instructions; the low-overhead branch
instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole
list of registers at once; the new VMRS/VMSR and VLDR/VSTR
instructions to get data in and out of 8.1-M system registers,
particularly including the new VPR register used by MVE vector
predication.
To support this, we also add a register name 'zr' (used by the CSEL
family to force one of the inputs to the constant 0), and operand
types for lists of registers that are also allowed to include APSR or
VPR (used by CLRM). The VLDR/VSTR instructions also need some new
addressing modes.
The low-overhead branch instructions exist in their own separate
architecture extension, which we treat as enabled by default, but you
can say -mattr=-lob or equivalent to turn it off.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Reviewed By: samparker
Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62667
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362953
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Whitney Tsang [Mon, 10 Jun 2019 15:29:07 +0000 (15:29 +0000)]
[DA] Add an option to control delinearization validity checks
Summary: Dependence Analysis performs static checks to confirm validity
of delinearization. These checks often fail for 64-bit targets due to
type conversions and integer wrapping that prevent simplification of the
SCEV expressions. These checks would also fail at compile-time if the
lower bound of the loops are compile-time unknown.
Author: bmahjour
Reviewer: Meinersbur, jdoerfert, kbarton, dmgreen, fhahn
Reviewed By: Meinersbur, jdoerfert, dmgreen
Subscribers: fhahn, hiraditya, javed.absar, llvm-commits, Whitney,
etiotto
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D62610
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362952
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Jeremy Morse [Mon, 10 Jun 2019 15:23:46 +0000 (15:23 +0000)]
[DebugInfo] Terminate all location-lists at end of block
This commit reapplies r359426 (which was reverted in r360301 due to
performance problems) and rolls in D61940 to address the performance problem.
I've combined the two to avoid creating a span of slow-performance, and to
ease reverting if more problems crop up.
The summary of D61940: This patch removes the "ChangingRegs" facility in
DbgEntityHistoryCalculator, as its overapproximate nature can produce incorrect
variable locations. An unchanging register doesn't mean a variable doesn't
change its location.
The patch kills off everything that calculates the ChangingRegs vector.
Previously ChangingRegs spotted epilogues and marked registers as unchanging if
they weren't modified outside the epilogue, increasing the chance that we can
emit a single-location variable record. Without this feature,
debug-loc-offset.mir and pr19307.mir become temporarily XFAIL. They'll be
re-enabled by D62314, using the FrameDestroy flag to identify epilogues, I've
split this into two steps as FrameDestroy isn't necessarily supported by all
backends.
The logic for terminating variable locations at the end of a basic block now
becomes much more enjoyably simple: we just terminate them all.
Other test changes: inlined-argument.ll becomes XFAIL, but for a longer term.
The current algorithm for detecting that a variable has a single-location
doesn't work in this scenario (inlined function in multiple blocks), only other
bugs were making this test work. fission-ranges.ll gets slightly refreshed too,
as the location of "p" is now correctly determined to be a single location.
Differential Revision: https://reviews.llvm.org/D61940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362951
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Sanjay Patel [Mon, 10 Jun 2019 15:08:22 +0000 (15:08 +0000)]
[InstCombine] add tests for fabs() with unordered preds; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362949
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Cameron McInally [Mon, 10 Jun 2019 15:07:29 +0000 (15:07 +0000)]
[IRBuilder] Add CreateFNegFMF(...) to the IRBuilder
Differential Revision: https://reviews.llvm.org/D62521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362947
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Sanjay Patel [Mon, 10 Jun 2019 14:57:45 +0000 (14:57 +0000)]
[InstCombine] fix bug in canonicalization to fabs()
Forgot to translate the predicate clauses in rL362943.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362945
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Sanjay Patel [Mon, 10 Jun 2019 14:46:36 +0000 (14:46 +0000)]
[InstCombine] change canonicalization to fabs() to use FMF on fsub
Similar to rL362909:
This isn't the ideal fix (use FMF on the select), but it's still an
improvement until we have better FMF propagation to selects and other
FP math operators.
I don't think there's much risk of regression from this change by
not including the FMF on the fcmp any more. The nsz/nnan FMF
should be the same on the fcmp and the fsub because they have the
same operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362943
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Simon Tatham [Mon, 10 Jun 2019 14:43:55 +0000 (14:43 +0000)]
[ARM] Disallow PC, and optionally SP, in VMOVRH and VMOVHR.
Arm v8.1-M supports the VMOV instructions that move a half-precision
value to and from a GPR, but not if the GPR is SP or PC.
To fix this, I've changed those instructions to use the rGPR register
class instead of GPR. rGPR always excludes PC, and it excludes SP
except in the presence of the HasV8Ops target feature (i.e. Arm v8-A).
So the effect is that VMOV.F16 to and from PC is now illegal
everywhere, but VMOV.F16 to and from SP is illegal only on non-v8-A
cores (which I believe is all as it should be).
Reviewers: dmgreen, samparker, SjoerdMeijer, ostannard
Reviewed By: ostannard
Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362942
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Cameron McInally [Mon, 10 Jun 2019 14:38:48 +0000 (14:38 +0000)]
[ExecutionEngine] Add UnaryOperator visitor to the interpreter
This is to support the unary FNeg instruction.
Differential Revision: https://reviews.llvm.org/D62881
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362941
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George Rimar [Mon, 10 Jun 2019 14:33:24 +0000 (14:33 +0000)]
[yaml2obj] - Remove TODOs from dynsymtab-implicit-sections-size-content.yaml. NFCI.
Now when https://bugs.llvm.org/show_bug.cgi?id=42215 is fixed,
we can remove these TODOs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362940
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George Rimar [Mon, 10 Jun 2019 14:23:46 +0000 (14:23 +0000)]
[llvm-readobj/llvm-readelf] - Don't fail to dump the object if .dynsym has broken sh_link field.
This is https://bugs.llvm.org/show_bug.cgi?id=42215.
GNU readelf allows to dump the objects in that case,
but llvm-readobj/llvm-readelf reports an error and stops.
The patch fixes that.
Differential revision: https://reviews.llvm.org/D63074
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362938
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Sanjay Patel [Mon, 10 Jun 2019 14:14:51 +0000 (14:14 +0000)]
[InstCombine] allow unordered preds when canonicalizing to fabs()
PR42179:
https://bugs.llvm.org/show_bug.cgi?id=42179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362937
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Sanjay Patel [Mon, 10 Jun 2019 14:04:10 +0000 (14:04 +0000)]
[InstCombine] add tests for fcmp unordered pred -> fabs (PR42179); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362936
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Andrea Di Biagio [Mon, 10 Jun 2019 13:33:54 +0000 (13:33 +0000)]
[MCA] Fix -Wunused-private-field warning after r362933. NFC
This should unbreak the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362935
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Andrea Di Biagio [Mon, 10 Jun 2019 12:50:08 +0000 (12:50 +0000)]
[MCA] Further refactor the bottleneck analysis view. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362933
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Nico Weber [Mon, 10 Jun 2019 12:49:02 +0000 (12:49 +0000)]
gn build: Merge r362913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362932
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George Rimar [Mon, 10 Jun 2019 12:43:18 +0000 (12:43 +0000)]
[yaml2obj/obj2yaml] - Make RawContentSection::Content and RawContentSection::Size optional
This is a follow-up for D62809.
Content and Size fields should be optional as was discussed in comments
of the D62809's thread. With that, we can describe a specific string table and
symbol table sections in a more correct way and also show appropriate errors.
The patch adds lots of test cases where the behavior is described in details.
Differential revision: https://reviews.llvm.org/D62957
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362931
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George Rimar [Mon, 10 Jun 2019 11:38:06 +0000 (11:38 +0000)]
[yaml2obj] - Do not assert when .dynsym is specified explicitly, but .dynstr is not present.
We have a code in buildSectionIndex() that adds implicit sections:
// Add special sections after input sections, if necessary.
for (StringRef Name : implicitSectionNames())
if (SN2I.addName(Name, SecNo)) {
// Account for this section, since it wasn't in the Doc
++SecNo;
DotShStrtab.add(Name);
}
The problem arises when .dynsym is specified explicitly and no
DynamicSymbols is used. In that case, we do not add
.dynstr implicitly and will assert later when will try to set Link
for .dynsym.
Seems, in this case, reasonable behavior is to allow Link field to be zero.
This is what this patch does.
Differential revision: https://reviews.llvm.org/D63001
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362929
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David Green [Mon, 10 Jun 2019 10:22:14 +0000 (10:22 +0000)]
[ARM] Enable Unroll UpperBound
This option allows loops with small max trip counts to be fully unrolled. This
can help with code like the remainder loops from manually unrolled loops like
those that appear in the cmsis dsp library. We would apparently previously
runtime unroll them with the default unroll count (4).
Differential Revision: https://reviews.llvm.org/D63064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362928
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Simon Pilgrim [Mon, 10 Jun 2019 10:13:32 +0000 (10:13 +0000)]
Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362927
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George Rimar [Mon, 10 Jun 2019 09:57:29 +0000 (09:57 +0000)]
[yaml2obj] - Remove helper methods that are probably excessive. NFC.
These methods are used only once. One of them is not used at all.
Differential revision: https://reviews.llvm.org/D63002
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362925
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Nikola Prica [Mon, 10 Jun 2019 08:41:06 +0000 (08:41 +0000)]
[DebugInfo] More strict debug range for stack variables
Variable's stack location can stretch longer than it should. If a
variable is placed at the stack in a some nested basic block its range
can be calculated to be up to the next occurrence of the variable's
DBG_VALUE, or up to the end of the function, thus covering a basic
blocks that should not be included in the variable’s location range.
This happens because the DbgEntityHistoryCalculator ends register
locations at the end of a basic block only if the variable’s location
register has been changed throughout the function, which is not the
case for the register used to reference stack objects.
This patch also tries to produce a single value location if the location
list builder managed to merge all the locations into one.
Reviewers: aprantl, dstenb, jmorse
Reviewed By: aprantl, dstenb, jmorse
Subscribers: djtodoro, ivanbaev, asowda
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D61600
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362923
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QingShan Zhang [Mon, 10 Jun 2019 05:40:21 +0000 (05:40 +0000)]
[DAGCombine] Match a pattern where a wide type scalar value is stored by several narrow stores
This opportunity is found from spec 2017 557.xz_r. And it is used by the sha encrypt/decrypt. See sha-2/sha512.c
static void store64(u64 x, unsigned char* y)
{
for(int i = 0; i != 8; ++i)
y[i] = (x >> ((7-i) * 8)) & 255;
}
static u64 load64(const unsigned char* y)
{
u64 res = 0;
for(int i = 0; i != 8; ++i)
res |= (u64)(y[i]) << ((7-i) * 8);
return res;
}
The load64 has been implemented by https://reviews.llvm.org/D26149
This patch is trying to implement the store pattern.
Match a pattern where a wide type scalar value is stored by several narrow
stores. Fold it into a single store or a BSWAP and a store if the targets
supports it.
Assuming little endian target:
i8 *p = ...
i32 val = ...
p[0] = (val >> 0) & 0xFF;
p[1] = (val >> 8) & 0xFF;
p[2] = (val >> 16) & 0xFF;
p[3] = (val >> 24) & 0xFF;
>
*((i32)p) = val;
i8 *p = ...
i32 val = ...
p[0] = (val >> 24) & 0xFF;
p[1] = (val >> 16) & 0xFF;
p[2] = (val >> 8) & 0xFF;
p[3] = (val >> 0) & 0xFF;
>
*((i32)p) = BSWAP(val);
Differential Revision: https://reviews.llvm.org/D62897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362921
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Craig Topper [Mon, 10 Jun 2019 04:50:12 +0000 (04:50 +0000)]
[X86] When promoting i16 compare with immediate to i32, try to use sign_extend for eq/ne if the input is truncated from a type with enough sign its.
Summary:
Our default behavior is to use sign_extend for signed comparisons and zero_extend for everything else. But for equality we have the freedom to use either extension. If we can prove the input has been truncated from something with enough sign bits, we can use sign_extend instead and let DAG combine optimize it out. A similar rule is used by type legalization in LegalizeIntegerTypes.
This gets rid of the movzx in PR42189. The immediate will still take 4 bytes instead of the 2 bytes plus 0x66 prefix a cmp di, 32767 would get, but it avoids a length changing prefix.
Reviewers: RKSimon, spatel, xbolva00
Reviewed By: xbolva00
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63032
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362920
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Craig Topper [Mon, 10 Jun 2019 04:37:16 +0000 (04:37 +0000)]
[X86] Disable f32->f64 extload when sse2 is enabled
Summary:
We can only use the memory form of cvtss2sd under optsize due to a partial register update. So previously we were emitting 2 instructions for extload when optimizing for speed. Also due to a late optimization in preprocessiseldag we had to handle (fpextend (loadf32)) under optsize.
This patch forces extload to expand so that it will always be in the (fpextend (loadf32)) form during isel. And when optimizing for speed we can just let each of those pieces select an instruction independently.
Reviewers: spatel, RKSimon
Reviewed By: RKSimon
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362919
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Vivek Pandya [Mon, 10 Jun 2019 04:16:04 +0000 (04:16 +0000)]
Do not derive no-recurse attribute if function does not have exact definition.
This is fix for https://bugs.llvm.org/show_bug.cgi?id=41336
Reviewers: jdoerfert
Reviewed by: jdoerfert
Differential Revision: https://reviews.llvm.org/D63045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362918
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Kai Luo [Mon, 10 Jun 2019 03:20:33 +0000 (03:20 +0000)]
[NFC] Test if commit access granted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362917
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Nico Weber [Mon, 10 Jun 2019 01:47:04 +0000 (01:47 +0000)]
Make test not write to source directory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362916
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Craig Topper [Mon, 10 Jun 2019 01:18:55 +0000 (01:18 +0000)]
[X86] Use EVEX instructions for f128 FAND/FOR/FXOR when avx512vl is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362915
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Craig Topper [Mon, 10 Jun 2019 00:41:07 +0000 (00:41 +0000)]
[X86] Convert f32/f64 FANDN/FAND/FOR/FXOR to vector logic ops and scalar_to_vector/extract_vector_elts to reduce isel patterns.
Previously we did the equivalent operation in isel patterns with
COPY_TO_REGCLASS operations to transition. By inserting
scalar_to_vetors and extract_vector_elts before isel we can
allow each piece to be selected individually and accomplish the
same final result.
I ideally we'd use vector operations earlier in lowering/combine,
but that looks to be more difficult.
The scalar-fp-to-i64.ll changes are because we have a pattern for
using movlpd for store+extract_vector_elt. While an f64 store
uses movsd. The encoding sizes are the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362914
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Nico Weber [Sun, 9 Jun 2019 19:27:50 +0000 (19:27 +0000)]
Revert r361953 "[SVE][IR] Scalable Vector IR Type"
This reverts commit
f4fc01f8dd3a5dfd2060d1ad0df6b90e8351ddf7.
It caused a 3-4x slowdown when doing thinlto links, PR42210.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362913
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David Bolvansky [Sun, 9 Jun 2019 18:18:57 +0000 (18:18 +0000)]
[TargetLowering] Simplify (ctpop x) == 1
Reviewers: craig.topper, spatel, RKSimon, bkramer
Reviewed By: spatel
Subscribers: javed.absar, lebedev.ri, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362912
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Roman Lebedev [Sun, 9 Jun 2019 16:30:42 +0000 (16:30 +0000)]
[InstCombine] foldICmpWithLowBitMaskedVal(): 'icmp sgt/sle': avoid miscompiles
A precondition 'x != 0' was forgotten by me:
https://rise4fun.com/Alive/JFNP
https://rise4fun.com/Alive/jHvL
These 4 folds with non-constants could be re-enabled,
but for now let's go for the simplest solution.
https://bugs.llvm.org/show_bug.cgi?id=42198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362911
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Roman Lebedev [Sun, 9 Jun 2019 16:30:14 +0000 (16:30 +0000)]
[NFC][InstCombine] Revisit canonicalize-constant-low-bit-mask-and-icmp-s* tests in preparatio for PR42198.
The `icmp sgt`/`icmp sle` variants are, too, miscompiles:
https://rise4fun.com/Alive/JFNP
https://rise4fun.com/Alive/jHvL
A precondition 'x != 0' was forgotten by me.
While ensuring test coverage for `-1`, also add test coverage
for `0` mask. Mask `0` is allowed for all the folds,
mask `-1` is allowed for all the folds with unsigned `icmp` pred.
Constant mask `0` is missed though.
https://bugs.llvm.org/show_bug.cgi?id=42198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362910
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Sanjay Patel [Sun, 9 Jun 2019 16:22:01 +0000 (16:22 +0000)]
[InstCombine] change canonicalization to fabs() to use FMF on fneg
This isn't the ideal fix (use FMF on the select), but it's still an
improvement until we have better FMF propagation to selects and other
FP math operators.
I don't think there's much risk of regression from this change by
not including the FMF on the fcmp any more. The nsz/nnan FMF
should be the same on the fcmp and the fneg (fsub) because they
have the same operand.
This works around the most glaring FMF logical inconsistency cited
in PR38086:
https://bugs.llvm.org/show_bug.cgi?id=38086
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362909
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David Bolvansky [Sun, 9 Jun 2019 16:15:08 +0000 (16:15 +0000)]
[NFC] Adjust test for D63004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362908
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David Bolvansky [Sun, 9 Jun 2019 15:12:46 +0000 (15:12 +0000)]
[NFC] Added test from PR19758
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362907
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David Bolvansky [Sun, 9 Jun 2019 14:56:46 +0000 (14:56 +0000)]
[NFC] Added test from PR42084 for D63058
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362906
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Nikita Popov [Sun, 9 Jun 2019 14:39:47 +0000 (14:39 +0000)]
[InstCombine] Add tests for usub.sat(x,y)+y etc; NFC
For PR42178.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362905
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Sanjay Patel [Sun, 9 Jun 2019 13:58:46 +0000 (13:58 +0000)]
[InstSimplify] reduce code duplication for fcmp folds; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362904
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Sanjay Patel [Sun, 9 Jun 2019 13:48:59 +0000 (13:48 +0000)]
[InstSimplify] enhance fcmp fold with never-nan operand
This is another step towards correcting our usage of fast-math-flags when applied on an fcmp.
In this case, we are checking for 'nnan' on the fcmp itself rather than the operand of
the fcmp. But I'm leaving that clause in until we're more confident that we can stop
relying on fcmp's FMF.
By using the more general "isKnownNeverNaN()", we gain a simplification shown on the
tests with 'uitofp' regardless of the FMF on the fcmp (uitofp never produces a NaN).
On the tests with 'fabs', we are now relying on the FMF for the call fabs instruction
in addition to the FMF on the fcmp.
This is a continuation of D62979 / rL362879.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362903
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Sanjay Patel [Sun, 9 Jun 2019 13:30:14 +0000 (13:30 +0000)]
[InstSimplify] add tests for fcmp with known-never-nan operands; NFC
Opposite predicate for rL362742 / rL362879 / D62979
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362902
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Anton Afanasyev [Sun, 9 Jun 2019 12:15:47 +0000 (12:15 +0000)]
[MIR] Add simple PRE pass to MachineCSE
This is the second part of the commit fixing PR38917 (hoisting
partitially redundant machine instruction). Most of PRE (partitial
redundancy elimination) and CSE work is done on LLVM IR, but some of
redundancy arises during DAG legalization. Machine CSE is not enough
to deal with it. This simple PRE implementation works a little bit
intricately: it passes before CSE, looking for partitial redundancy
and transforming it to fully redundancy, anticipating that the next
CSE step will eliminate this created redundancy. If CSE doesn't
eliminate this, than created instruction will remain dead and eliminated
later by Remove Dead Machine Instructions pass.
The third part of the commit is supposed to refactor MachineCSE,
to make it more clear and to merge MachinePRE with MachineCSE,
so one need no rely on further Remove Dead pass to clear instrs
not eliminated by CSE.
First step: https://reviews.llvm.org/D54839
Fixes llvm.org/PR38917
This is fixed recommit of r361356 after PowerPC64 multistage build failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362901
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Ayke van Laethem [Sun, 9 Jun 2019 10:20:33 +0000 (10:20 +0000)]
[CaptureTracking] Don't let comparisons against null escape inbounds pointers
Pointers that are in-bounds (either through dereferenceable_or_null or
thorough a getelementptr inbounds) cannot be captured with a comparison
against null. There is no way to construct a pointer that is still in
bounds but also NULL.
This helps safe languages that insert null checks before load/store
instructions. Without this patch, almost all pointers would be
considered captured even for simple loads. With this patch, an icmp with
null will not be seen as escaping as long as certain conditions are met.
There was a lot of discussion about this patch. See the Phabricator
thread for detals.
Differential Revision: https://reviews.llvm.org/D60047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362900
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Ayke van Laethem [Sun, 9 Jun 2019 10:06:35 +0000 (10:06 +0000)]
[bindings/go] Add wrappers for atomic operations.
This patch adds Go bindings for atomic operations in LLVM.
Differential Revision: https://reviews.llvm.org/D61034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362899
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Jatin Bhateja [Sun, 9 Jun 2019 09:59:26 +0000 (09:59 +0000)]
[X86] NFCI : Comment updation for EVEX to VEX translation.
Reviewers: llvm-commits, jbhateja
Reviewed By: jbhateja
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362898
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Simon Pilgrim [Sun, 9 Jun 2019 09:07:30 +0000 (09:07 +0000)]
Use for-range loop. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362897
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Amara Emerson [Sun, 9 Jun 2019 07:31:25 +0000 (07:31 +0000)]
[AArch64][GlobalISel] Select immediate forms of cmp instructions.
A simple re-use of the immediate operand matcher and renderer functions.
rdar://
43795178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362896
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Craig Topper [Sun, 9 Jun 2019 03:21:33 +0000 (03:21 +0000)]
[X86] Remove (store (f32 (extractelt (v4f32))) isel patterns which is redundant.
We emit a MOVSSmr and a COPY_TO_REGCLASS, but that's what we would get from
selecting the store and extractelt independently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362895
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Craig Topper [Sat, 8 Jun 2019 23:53:31 +0000 (23:53 +0000)]
[X86] Mutate scalar fceil/ffloor/ftrunc/fnearbyint/frint into X86ISD::RNDSCALE during PreProcessIselDAG to cut down on number of isel patterns.
Similar was done for vectors in r362535. Removes about 1200 bytes from the isel table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362894
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Ayke van Laethem [Sat, 8 Jun 2019 22:21:37 +0000 (22:21 +0000)]
[bindings/go] Add bindings to LLVMGet?CmpPredicate
Add bindings so that predicates on comparisons (icmp/fcmp) can be
inspected from IR.
Note: I considered adding Value.ICmpPredicate() etc. instead but
Value.IntPredicate() seemed easier to read and matches the name of the
returned type.
(This change was also pushed two commits ago but accidentally had the
wrong title and description.)
Revision: https://reviews.llvm.org/D53884
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362893
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Ayke van Laethem [Sat, 8 Jun 2019 22:17:51 +0000 (22:17 +0000)]
Revert "[bindings/go] Add Go bindings for CalledValue"
This reverts commit
f675a60ca7a93f22e22dd4209504a9846dd04630.
The commit had the wrong title/description. Sorry about the mess!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362892
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Ayke van Laethem [Sat, 8 Jun 2019 22:15:38 +0000 (22:15 +0000)]
[bindings/go] Add Go bindings for CalledValue
This is very useful for inspecting generated IR, there appears to be no
other way to get the called function from a CallInst.
Differential Revision: https://reviews.llvm.org/D52972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362891
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Ayke van Laethem [Sat, 8 Jun 2019 22:08:52 +0000 (22:08 +0000)]
[bindings/go] Add Go bindings for CalledValue
This is very useful for inspecting generated IR, there appears to be no
other way to get the called function from a CallInst.
Revision: https://reviews.llvm.org/D52972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362890
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Ayke van Laethem [Sat, 8 Jun 2019 22:00:19 +0000 (22:00 +0000)]
[bindings/go] Add EraseFromParent
After using ReplaceAllUsesWith on an instruction, it may be necessary to
erase it even though it is dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362889
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Ayke van Laethem [Sat, 8 Jun 2019 21:42:00 +0000 (21:42 +0000)]
[NFC] Test commit
Add a newline, which is missing according to go fmt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362888
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Roman Lebedev [Sat, 8 Jun 2019 19:38:14 +0000 (19:38 +0000)]
[X86][Codegen] Add missed pattern that may be a lea+neg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362886
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Simon Pilgrim [Sat, 8 Jun 2019 17:02:00 +0000 (17:02 +0000)]
[DAGCombine] visitAND - merge (zext_inreg ((s)extload x)) -> (zextload x) combines. NFCI.
Same codegen, only differ by the oneuse limit for the sextload case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362880
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Sanjay Patel [Sat, 8 Jun 2019 15:12:33 +0000 (15:12 +0000)]
[InstSimplify] enhance fcmp fold with never-nan operand
This is 1 step towards correcting our usage of fast-math-flags when applied on an fcmp.
In this case, we are checking for 'nnan' on the fcmp itself rather than the operand of
the fcmp. But I'm leaving that clause in until we're more confident that we can stop
relying on fcmp's FMF.
By using the more general "isKnownNeverNaN()", we gain a simplification shown on the
tests with 'uitofp' regardless of the FMF on the fcmp (uitofp never produces a NaN).
On the tests with 'fabs', we are now relying on the FMF for the call fabs instruction
in addition to the FMF on the fcmp.
I'll update the 'ult' case below here as a follow-up assuming no problems here.
Differential Revision: https://reviews.llvm.org/D62979
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362879
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Sylvestre Ledru [Sat, 8 Jun 2019 15:07:55 +0000 (15:07 +0000)]
fix a typo unavaliable=>unavailable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362878
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David Bolvansky [Sat, 8 Jun 2019 12:07:59 +0000 (12:07 +0000)]
[NFC] Added tests for D63038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362875
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David Green [Sat, 8 Jun 2019 10:32:53 +0000 (10:32 +0000)]
[ARM] Adjust isLegalT1AddressImmediate for non-legal types
Types such as float and i64's do not have legal loads in Thumb1, but will still
be loaded with a LDR (or potentially multiple LDR's). As such we can treat the
cost of addressing mode calculations the same as an i32 and get some optimisation
benefits.
Differential Revision: https://reviews.llvm.org/D62968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362874
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David Green [Sat, 8 Jun 2019 10:18:23 +0000 (10:18 +0000)]
[ARM] Add MVE addressing to isLegalT2AddressImmediate
Now with MVE being added, we can add the vector addressing mode costs for it.
These are generally imm7 multiplied by the size of the type being loaded /
stored.
Differential Revision: https://reviews.llvm.org/D62967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362873
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David Green [Sat, 8 Jun 2019 10:09:02 +0000 (10:09 +0000)]
[ARM] Add fp16 addressing to isLegalT2AddressImmediate
The fp16 version of VLDR takes a imm8 multiplied by 2. This updates the costs
to account for those, and adds extra testing. It is dependant upon hasFPRegs16
as this is what the load/store instructions require.
Differential Revision: https://reviews.llvm.org/D62966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362872
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David Green [Sat, 8 Jun 2019 09:58:05 +0000 (09:58 +0000)]
[ARM] Add extra gep costmodel tests for MVE and half float. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362871
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David Green [Sat, 8 Jun 2019 09:36:49 +0000 (09:36 +0000)]
[ARM] Add HasNEON for all Neon patterns in ARMInstrNEON.td. NFCI
We are starting to add an entirely separate vector architecture to the ARM
backend. To do that we need at least some separation between the existing NEON
and the new MVE code. This patch just goes through the Neon patterns and
ensures that they are predicated on HasNEON, giving MVE a stable place to start
from.
No tests yet as this is largely an NFC, and we don't have the other target that
will treat any of these intructions as legal.
Differential Revision: https://reviews.llvm.org/D62945
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362870
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Jonas Paulsson [Sat, 8 Jun 2019 06:42:02 +0000 (06:42 +0000)]
[SystemZ] Fix CMakeLists.txt for alphabetical order (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362869
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Jonas Paulsson [Sat, 8 Jun 2019 06:19:15 +0000 (06:19 +0000)]
[SystemZ, RegAlloc] Favor 3-address instructions during instruction selection.
This patch aims to reduce spilling and register moves by using the 3-address
versions of instructions per default instead of the 2-address equivalent
ones. It seems that both spilling and register moves are improved noticeably
generally.
Regalloc hints are passed to increase conversions to 2-address instructions
which are done in SystemZShortenInst.cpp (after regalloc).
Since the SystemZ reg/mem instructions are 2-address (dst and lhs regs are
the same), foldMemoryOperandImpl() can no longer trivially fold a spilled
source register since the reg/reg instruction is now 3-address. In order to
remedy this, new 3-address pseudo memory instructions are used to perform the
folding only when the dst and lhs virtual registers are known to be allocated
to the same physreg. In order to not let MachineCopyPropagation run and
change registers on these transformed instructions (making it 3-address), a
new target pass called SystemZPostRewrite.cpp is run just after
VirtRegRewriter, that immediately lowers the pseudo to a target instruction.
If it would have been possibe to insert a COPY instruction and change a
register operand (convert to 2-address) in foldMemoryOperandImpl() while
trusting that the caller (e.g. InlineSpiller) would update/repair the
involved LiveIntervals, the solution involving pseudo instructions would not
have been needed. This is perhaps a potential improvement (see Phabricator
post).
Common code changes:
* A new hook TargetPassConfig::addPostRewrite() is utilized to be able to run a
target pass immediately before MachineCopyPropagation.
* VirtRegMap is passed as an argument to foldMemoryOperand().
Review: Ulrich Weigand, Quentin Colombet
https://reviews.llvm.org/D60888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362868
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Nico Weber [Sat, 8 Jun 2019 01:27:47 +0000 (01:27 +0000)]
gn build: Merge r362857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362864
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Seiya Nuta [Sat, 8 Jun 2019 01:22:54 +0000 (01:22 +0000)]
[llvm-objcopy][MachO] Recompute and update offset/size fields in the writer
Summary:
Recompute and update offset/size fields so that we can implement llvm-objcopy options like --only-section.
This patch is the first step and focuses on supporting load commands that covered by existing tests: executable files and
dynamic libraries are not supported.
Reviewers: alexshap, rupprecht, jhenderson
Reviewed By: alexshap, rupprecht
Subscribers: compnerd, jakehehrlich, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62652
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362863
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Mike Spertus [Sat, 8 Jun 2019 00:23:08 +0000 (00:23 +0000)]
Visualizer for APInt and remove obsolete visualizer
Visualizer for the simple case of APInt (uints < 2^64)
as will be required for Clang ConstantArrayType visualizer.
Also, removed obsolete VS2013 SmallVectorVisualizer as VS2013
is no longer supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362860
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Amara Emerson [Sat, 8 Jun 2019 00:05:17 +0000 (00:05 +0000)]
Factor out SelectionDAG's switch analysis and lowering into a separate component.
In order for GlobalISel to re-use the significant amount of analysis and
optimization code in SDAG's switch lowering, we first have to extract it and
create an interface to be used by both frameworks.
No test changes as it's NFC.
Differential Revision: https://reviews.llvm.org/D62745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362857
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Matt Arsenault [Fri, 7 Jun 2019 23:17:38 +0000 (23:17 +0000)]
LoopDistribute: Add testcase where SCEV wants to insert a runtime
check.
Only the memory based checks were being tested. Prepare for fix in
convergent handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362854
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Keno Fischer [Fri, 7 Jun 2019 23:08:38 +0000 (23:08 +0000)]
[GVN] non-functional code movement
Summary: Move some code around, in preparation for later fixes
to the non-integral addrspace handling (D59661)
Patch By Jameson Nash <jameson@juliacomputing.com>
Reviewed By: reames, loladiro
Differential Revision: https://reviews.llvm.org/D59729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362853
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Matt Arsenault [Fri, 7 Jun 2019 23:02:52 +0000 (23:02 +0000)]
AMDGPU: Force skips around traps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362852
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Reid Kleckner [Fri, 7 Jun 2019 22:05:12 +0000 (22:05 +0000)]
[COFF] Fix /export:foo=bar when bar is a weak alias
Summary:
When handling exports from the command line or from .def files, the
linker does a "fuzzy" string lookup to allow finding mangled symbols.
However, when the symbol is re-exported under a new name, the linker has
to transfer the decorations from the exported symbol over to the new
name. This is implemented by taking the mangled symbol that was found in
the object and replacing the original symbol name with the export name.
Before this patch, LLD implemented the fuzzy search by adding an
undefined symbol with the unmangled name, and then during symbol
resolution, checking if similar mangled symbols had been added after the
last round of symbol resolution. If so, LLD makes the original symbol a
weak alias of the mangled symbol. Later, to get the original symbol
name, LLD would look through the weak alias and forward it on to the
import library writer, which copies the symbol decorations. This
approach doesn't work when bar is itself a weak alias, as is the case in
asan. It's especially bad when the aliasee of bar contains the string
"bar", consider "bar_default". In this case, we would end up exporting
the symbol "foo_default" when we should've exported just "foo".
To fix this, don't look through weak aliases to find the mangled name.
Save the mangled name earlier during fuzzy symbol lookup.
Fixes PR42074
Reviewers: mstorsjo, ruiu
Subscribers: thakis, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362849
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Alexander Shaposhnikov [Fri, 7 Jun 2019 22:03:02 +0000 (22:03 +0000)]
[llvm-lipo] Add docs for llvm-lipo
Add docs (llvm-lipo.rst) for llvm-lipo.
Test plan:
make -j8 sphinx
check that ./docs/html/CommandGuide/llvm-lipo.html is built correctly and looks okay.
Differential revision: https://reviews.llvm.org/D62706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362848
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Jordan Rupprecht [Fri, 7 Jun 2019 21:49:26 +0000 (21:49 +0000)]
[llvm-objdump] Fix Bugzilla ID 41862 to support checking addresses of disassembled object
Summary:
This fixes the bugzilla id,41862 to support dealing with checking
stop address against start address to support this not being a
proper object to check the disasembly against like gnu objdump
currently does.
Reviewers: jakehehrlich, rupprecht, echristo, jhenderson, grimar
Reviewed By: jhenderson
Subscribers: MaskRay, smeenai, rupprecht, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61969
Patch by Nicholas Krause!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362847
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Adrian McCarthy [Fri, 7 Jun 2019 21:14:33 +0000 (21:14 +0000)]
Fix string literals to avoid deprecation warnings in regexp patterns
In LLDB, where tests run with the debug version of Python, we get a
series of deprecation warnings because escape sequences like `\(` are
being treated as part of the string literal rather than an escape for
the regexp pattern.
NFC intended.
Differential Revision: https://reviews.llvm.org/D62882
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362846
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Shoaib Meenai [Fri, 7 Jun 2019 20:52:17 +0000 (20:52 +0000)]
[llvm-lipo] Drop unneeded braces. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362841
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Shoaib Meenai [Fri, 7 Jun 2019 20:47:58 +0000 (20:47 +0000)]
[llvm-lipo] Implement -archs
Displays the architecture names of an input file.
Unknown architectures are represented by unknown(cputype,cpusubtype).
Patch by Anusha Basana <anusha.basana@gmail.com>
Differential Revision: https://reviews.llvm.org/D62753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362840
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Alina Sbirlea [Fri, 7 Jun 2019 20:43:55 +0000 (20:43 +0000)]
[DomTreeUpdater] Add all insert before all delete updates to reduce compile time.
Summary:
The cleanup in D62751 introduced a compile-time regression due to the way DT updates are performed.
Add all insert edges then all delete edges in DTU to match the previous compile time.
Compile time on the test provided by @mstorsjo before and after this patch on my machine:
113.046s vs 35.649s
Repro: clang -target x86_64-w64-mingw32 -c -O3 glew-preproc.c; on https://martin.st/temp/glew-preproc.c.
Reviewers: kuhar, NutshellySima, mstorsjo
Subscribers: jlebar, mstorsjo, dmgreen, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362839
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Michael Pozulp [Fri, 7 Jun 2019 20:34:31 +0000 (20:34 +0000)]
[llvm-objdump] Add warning if --disassemble-functions specifies an unknown symbol
Summary:
Fixes Bug 41904 https://bugs.llvm.org/show_bug.cgi?id=41904
Re-land r362768 after it was reverted in r362826.
Reviewers: jhenderson, rupprecht, grimar, MaskRay
Reviewed By: jhenderson, rupprecht, MaskRay
Subscribers: dexonsmith, rupprecht, kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62275
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362838
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Craig Topper [Fri, 7 Jun 2019 20:30:40 +0000 (20:30 +0000)]
[X86] Remove unnecessary new line escape from the end of a macro. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362837
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Michael Pozulp [Fri, 7 Jun 2019 20:23:03 +0000 (20:23 +0000)]
[ADT] Enable set_difference() to be used on StringSet
Summary: Re-land r362766 after it was reverted in r362823.
Reviewers: jhenderson, dsanders, aaron.ballman, MatzeB, lhames, dblaikie
Reviewed By: dblaikie
Subscribers: smeenai, mgrang, mgorny, dexonsmith, kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362835
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Volkan Keles [Fri, 7 Jun 2019 20:19:27 +0000 (20:19 +0000)]
[GlobalISel] IRTranslator: Translate the intrinsics ignored by CodeGen
Summary:
Translate `llvm.assume`, `llvm.var.annotation` and `llvm.sideeffect` to nothing
as they have no effect on CodeGen.
Reviewers: qcolombet, aditya_nandakumar, dsanders, paquette, aemerson, arsenm
Reviewed By: arsenm
Subscribers: hiraditya, wdng, rovka, kristof.beyls, javed.absar, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362834
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Nick Desaulniers [Fri, 7 Jun 2019 19:51:22 +0000 (19:51 +0000)]
[APFloat] APFloat::Storage::Storage - refix use after move
Summary:
Re-land r360675 after it was reverted in r360770.
This was reported in:
https://llvm.org/reports/scan-build/
Based on feedback in:
https://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20190513/652286.html
Reviewers: RKSimon, efriedma
Reviewed By: RKSimon, efriedma
Subscribers: eli.friedman, hiraditya, llvm-commits, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362833
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