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NAKAMURA Takumi [Sun, 19 Feb 2017 02:31:06 +0000 (02:31 +0000)]
llvm/test/CodeGen/AMDGPU/r600.alu-limits.ll should require +Asserts. This would run into infinite loop anyways with -Asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295591
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Craig Topper [Sun, 19 Feb 2017 02:08:48 +0000 (02:08 +0000)]
[X86] Remove patterns for MOVSD with v4i32 types. We don't appear to really need them and if we do we should just use a bitcast to a 64-bit element type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295589
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Craig Topper [Sun, 19 Feb 2017 01:54:47 +0000 (01:54 +0000)]
[X86] Tighten up some of the SDNode type constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295588
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Simon Pilgrim [Sun, 19 Feb 2017 00:33:37 +0000 (00:33 +0000)]
Fix unused variable warning when assertions are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295587
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Simon Pilgrim [Sun, 19 Feb 2017 00:04:30 +0000 (00:04 +0000)]
[X86] Fix enumeral/non-enumeral conditional expression warning.
gcc only allows you to mix enums / ints if they have the same signedness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295586
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Simon Pilgrim [Sun, 19 Feb 2017 00:03:46 +0000 (00:03 +0000)]
Fix 'variable set but not used' warning when assertions are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295585
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Daniel Berlin [Sat, 18 Feb 2017 23:06:50 +0000 (23:06 +0000)]
NewGVN: Start making use of predicateinfo pass.
Summary: This begins using the predicateinfo pass in NewGVN.
Reviewers: davide
Subscribers: llvm-commits, Prazek
Differential Revision: https://reviews.llvm.org/D29682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295583
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Daniel Berlin [Sat, 18 Feb 2017 23:06:47 +0000 (23:06 +0000)]
NewGVN: Make ranking prefer undef to constants. Fix direction of
shouldSwapOperands to be correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295582
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Daniel Berlin [Sat, 18 Feb 2017 23:06:38 +0000 (23:06 +0000)]
PredicateInfo: Clean up predicate info a little, using insertion
helpers, and fixing support for the renaming the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295581
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Simon Pilgrim [Sat, 18 Feb 2017 22:56:17 +0000 (22:56 +0000)]
Fix signed/unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295580
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Craig Topper [Sat, 18 Feb 2017 22:53:43 +0000 (22:53 +0000)]
[X86][XOP] Reduce the size of a multiclass by moving more stuff to parameters instead of doing 128-bit and 256-bit simultaneously.
This requires some instructions to be renamed to move the Y earlier in the instruction name. The new names are more consistent with other instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295579
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Craig Topper [Sat, 18 Feb 2017 22:53:38 +0000 (22:53 +0000)]
[TableGen] Make sure EnforceSameSize populates the type sets if necessary.
This was found by another commit I'm working on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295578
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Simon Pilgrim [Sat, 18 Feb 2017 22:50:28 +0000 (22:50 +0000)]
[AArch64] Fix enumeral/non-enumeral conditional expression warning.
gcc only allows you to mix enums / ints if they have the same signedness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295577
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Simon Pilgrim [Sat, 18 Feb 2017 22:40:58 +0000 (22:40 +0000)]
[X86] Fix enumeral/non-enumeral comparison warning.
gcc only allows you to mix enums / ints if they have the same signedness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295576
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Simon Pilgrim [Sat, 18 Feb 2017 22:25:27 +0000 (22:25 +0000)]
[X86][SSE] Avoid repeated calls to SDValue::getValueType.
Added assertion to check input type of X86ISD::VZEXT during target known bits calculation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295575
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Sanjay Patel [Sat, 18 Feb 2017 22:20:09 +0000 (22:20 +0000)]
[InstCombine] add nsw/nuw X, signbit --> or X, signbit
Changing to 'or' (rather than 'xor' when no wrapping flags are set)
allows icmp simplifies to happen as expected.
Differential Revision: https://reviews.llvm.org/D29729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295574
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Sanjay Patel [Sat, 18 Feb 2017 21:59:09 +0000 (21:59 +0000)]
[InstSimplify] add nsw/nuw (xor X, signbit), signbit --> X
The change to InstCombine in:
https://reviews.llvm.org/D29729
...exposes this missing fold in InstSimplify, so adding this
first to avoid a regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295573
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Sanjay Patel [Sat, 18 Feb 2017 21:51:14 +0000 (21:51 +0000)]
[InstSimplify] add tests for add nsw/nuw (xor X, signbit), signbit --> X; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295572
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Craig Topper [Sat, 18 Feb 2017 21:50:58 +0000 (21:50 +0000)]
Recommit "[X86] Remove XOP VPCMOV intrinsics and autoupgrade them to native IR."
Clang has now been fixed to not use these intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295571
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Sanjay Patel [Sat, 18 Feb 2017 21:07:37 +0000 (21:07 +0000)]
[x86] remove stale comments from tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295569
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Sanjay Patel [Sat, 18 Feb 2017 21:03:28 +0000 (21:03 +0000)]
[x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1
This is the same transform that is current used for:
select Bool, 0, -1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295568
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Piotr Padlewski [Sat, 18 Feb 2017 20:34:36 +0000 (20:34 +0000)]
[MemorySSA] NFC small fixes
Summary:
2 small fixes extracted from
https://reviews.llvm.org/D29064
Reviewers: kuhar, davide, dberlin, george.burgess.iv
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295566
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Craig Topper [Sat, 18 Feb 2017 20:14:20 +0000 (20:14 +0000)]
Revert "[X86] Remove XOP VPCMOV intrinsics and autoupgrade them to native IR."
This reverts r295564. I missed that clang was still using the intrinsics despite our half implemented autoupgrade support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295565
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Craig Topper [Sat, 18 Feb 2017 19:51:25 +0000 (19:51 +0000)]
[X86] Remove XOP VPCMOV intrinsics and autoupgrade them to native IR.
It seems we were already upgrading 128-bit VPCMOV, but the intrinsic was still defined and being used in isel patterns. While I was here I also simplified the tablegen multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295564
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Craig Topper [Sat, 18 Feb 2017 19:51:19 +0000 (19:51 +0000)]
[X86][IR] Simplify the XOP vpcmov autoupgrade code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295563
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Craig Topper [Sat, 18 Feb 2017 19:51:14 +0000 (19:51 +0000)]
[X86][IR] Merge together some very similar AutoUpgrade handling. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295562
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Matt Arsenault [Sat, 18 Feb 2017 19:12:26 +0000 (19:12 +0000)]
AMDGPU: Fix assembler subtarget predicate for gfx9
This was accepting GFX9 instructions on VI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295557
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Matt Arsenault [Sat, 18 Feb 2017 18:41:41 +0000 (18:41 +0000)]
AMDGPU: Fix disassembly of aperture registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295555
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Matt Arsenault [Sat, 18 Feb 2017 18:29:53 +0000 (18:29 +0000)]
AMDGPU: Merge initial gfx9 support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295554
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Sanjay Patel [Sat, 18 Feb 2017 18:27:04 +0000 (18:27 +0000)]
[InstCombine] add tests for trunc(insertelement); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295553
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Easwaran Raman [Sat, 18 Feb 2017 17:22:52 +0000 (17:22 +0000)]
Refactor instruction simplification code in visitors. NFC.
Several visitors check if operands to the instruction are constants,
either as it is or after looking up SimplifiedValues, check if the
result is a constant and update the SimplifiedValues map. This
refactoring splits it into a common function that does the checking of
whether the operands are constants and updating of the SimplifiedValues
table, and an instruction specific part that is implemented by each
instruction visitor as a lambda and passed to the common function.
Differential revision: https://reviews.llvm.org/D30104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295552
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Sanjay Patel [Sat, 18 Feb 2017 15:24:31 +0000 (15:24 +0000)]
[InstCombine] update trunc(shuffle) tests to reflect IR reality; NFC
We're ok shrinking splats, but not shuffles in general.
See https://reviews.llvm.org/D30123 for discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295547
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Brian Cain [Sat, 18 Feb 2017 15:13:58 +0000 (15:13 +0000)]
opt-viewer: Fix syntax highlighting
Syntax highlighting has been done line-at-a-time. Done this way, the lexer
resets the context at each line, distorting the formatting.
This change will render the whole file at once and feed the highlighted text
line-at-a-time to be wrapped by the SourceFileRenderer.
Leading/trailing newlines were being ignored by Pygments but since each line
was rendered in its own row, it didn't matter. This bug was masked by the
line-at-a-time algorithm. So now we need to add "stripnl=False" to the
CppLexer to change its behavior to match the expectation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295546
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Craig Topper [Sat, 18 Feb 2017 07:07:50 +0000 (07:07 +0000)]
[AVX-512] Remove 128/256-bit masked fp max/min intrinsics. Upgrade them to legacy unmasked intrinsics and select instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295543
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Dehao Chen [Sat, 18 Feb 2017 06:42:16 +0000 (06:42 +0000)]
Add default OptLevel value for createSimpleLoopUnrollPass to fix the build break introduced by r295538. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295542
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Jan Vesely [Sat, 18 Feb 2017 04:24:10 +0000 (04:24 +0000)]
AMDGPU/R600: Assert on infinite loop in EmitClauseMarkers
Differential Revision: https://reviews.llvm.org/D29792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295539
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Dehao Chen [Sat, 18 Feb 2017 03:46:51 +0000 (03:46 +0000)]
Increases full-unroll threshold.
Summary:
The default threshold for fully unroll is too conservative. This patch doubles the full-unroll threshold
This change will affect the following speccpu2006 benchmarks (performance numbers were collected from Intel Sandybridge):
Performance:
403 0.11%
433 0.51%
445 0.48%
447 3.50%
453 1.49%
464 0.75%
Code size:
403 0.56%
433 0.96%
445 2.16%
447 2.96%
453 0.94%
464 8.02%
The compiler time overhead is similar with code size.
Reviewers: davidxl, mkuper, mzolotukhin, hfinkel, chandlerc
Reviewed By: hfinkel, chandlerc
Subscribers: mehdi_amini, zzheng, efriedma, haicheng, hfinkel, llvm-commits
Differential Revision: https://reviews.llvm.org/D28368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295538
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Davide Italiano [Sat, 18 Feb 2017 03:02:44 +0000 (03:02 +0000)]
[IR/Verifier] Don't visit DISubprograms more than needed.
Before this patch we happened to visit twice, one when scanning
MDNodes and the other one while visiting the function. Remove
the explicit call to visitDISubprogram there, so we don't emit
the same error twice in case the verifier fail and we save some
time when running it.
Thanks to Justin Bogner for the report and Adrian for the quick
review!
PR: 31995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295537
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Dylan McKay [Sat, 18 Feb 2017 02:26:11 +0000 (02:26 +0000)]
[AVR] Set UseIntegratedAssembler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295535
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Justin Bogner [Sat, 18 Feb 2017 02:00:27 +0000 (02:00 +0000)]
OptDiag: Allow constructing DiagnosticLocation from DISubprograms
This avoids creating a DILocation just to represent a line number,
since creating Metadata is expensive. Creating a DiagnosticLocation
directly is much cheaper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295531
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Zachary Turner [Sat, 18 Feb 2017 01:51:00 +0000 (01:51 +0000)]
Remove the is_trivially_copyable check entirely.
This is still breaking builds because some compilers think
this type is not trivially copyable even when it should be.
Reverting this static_assert until I have time to investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295529
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Zachary Turner [Sat, 18 Feb 2017 01:46:01 +0000 (01:46 +0000)]
Use llvm workaround for missing is_trivially_copyable.
some versions of GCC don't have this, so LLVM provides a
workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295526
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Zachary Turner [Sat, 18 Feb 2017 01:35:33 +0000 (01:35 +0000)]
Don't assume little endian in StreamReader / StreamWriter.
In an effort to generalize this so it can be used by more than
just PDB code, we shouldn't assume little endian.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295525
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Matthias Braun [Sat, 18 Feb 2017 00:48:43 +0000 (00:48 +0000)]
machine-region-info.mir: Slightly simplify test, -mtriple
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295520
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Justin Bogner [Sat, 18 Feb 2017 00:42:23 +0000 (00:42 +0000)]
OptDiag: Decouple backend diagnostics from debug info metadata
This creates and uses a DiagnosticLocation type rather than using
DebugLoc for this purpose in the backend diagnostics. This is NFC for
now, but will allow us to create locations for diagnostics without
having to create new metadata nodes when we don't have a DILocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295519
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Matthias Braun [Sat, 18 Feb 2017 00:41:16 +0000 (00:41 +0000)]
MachineRegionInfo: Fix pass initialization
- Adapt MachineBasicBlock::getName() to have the same behavior as the IR
BasicBlock (Value::getName()).
- Add it to lib/CodeGen/CodeGen.cpp::initializeCodeGen so that it is linked in
the CodeGen library.
- MachineRegionInfoPass's name conflicts with RegionInfoPass's name ("region").
- MachineRegionInfo should depend on MachineDominatorTree,
MachinePostDominatorTree and MachineDominanceFrontier instead of their
respective IR versions.
- Since there were no tests for this, add a X86 MIR test.
Patch by Francis Visoiu Mistrih<fvisoiumistrih@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295518
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Justin Bogner [Fri, 17 Feb 2017 23:57:42 +0000 (23:57 +0000)]
Verifier: Disallow a line number without a file in DISubprogram
A line number doesn't make much sense if you don't say where it's
from. Add a verifier check for this and update some tests that had
bogus debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295516
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Sanjay Patel [Fri, 17 Feb 2017 23:16:54 +0000 (23:16 +0000)]
[InstCombine] add tests for trunc(shuffle X, C, M); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295513
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Matthias Braun [Fri, 17 Feb 2017 23:15:03 +0000 (23:15 +0000)]
AArch64LoadStoreOptimizer: Correctly clear kill flags
When promoting the Load of a Store-Load pair to a COPY all kill flags
between the store and the load need to be cleared.
rdar://
30402435
Differential Revision: https://reviews.llvm.org/D30110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295512
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Simon Pilgrim [Fri, 17 Feb 2017 23:00:21 +0000 (23:00 +0000)]
[X86] Add MOVBE targets to load combine tests
Test folded endian swap tests with MOVBE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295508
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Guozhi Wei [Fri, 17 Feb 2017 22:29:39 +0000 (22:29 +0000)]
[PPC] Give unaligned memory access lower cost on processor that supports it
Newer ppc supports unaligned memory access, it reduces the cost of unaligned memory access significantly. This patch handles this case in PPCTTIImpl::getMemoryOpCost.
This patch fixes pr31492.
Differential Revision: https://reviews.llvm.org/D28630
This is resubmit of r292680, which was reverted by r293092. The internal application failures were actually caused by a source code bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295506
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Eugene Zelenko [Fri, 17 Feb 2017 22:23:34 +0000 (22:23 +0000)]
[CodeGen] Revert changes in LowLevelType to pre-r295499 to fix broken buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295505
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Krzysztof Parzyszek [Fri, 17 Feb 2017 22:14:51 +0000 (22:14 +0000)]
[Hexagon] Start using regmasks on calls
Reapply r295371 with a fix for the Windows bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295504
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Davide Italiano [Fri, 17 Feb 2017 22:12:30 +0000 (22:12 +0000)]
[NewGVN] isOnlyReachableViaThisEdge() is dead now. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295503
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Simon Pilgrim [Fri, 17 Feb 2017 22:10:10 +0000 (22:10 +0000)]
[X86] Simplify by pulling out valuetype. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295502
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Eugene Zelenko [Fri, 17 Feb 2017 22:07:26 +0000 (22:07 +0000)]
[CodeGen] Attempt to fix buildbots broken in r295499.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295501
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Davide Italiano [Fri, 17 Feb 2017 21:55:47 +0000 (21:55 +0000)]
[NewGVN] createVariableOrConstant is not required anymore. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295500
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Eugene Zelenko [Fri, 17 Feb 2017 21:43:25 +0000 (21:43 +0000)]
[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295499
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Simon Pilgrim [Fri, 17 Feb 2017 21:16:24 +0000 (21:16 +0000)]
[X86] Add subborrow stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295496
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Sanjay Patel [Fri, 17 Feb 2017 21:10:40 +0000 (21:10 +0000)]
[x86] add tests for sext (not bool); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295495
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Matthew Simpson [Fri, 17 Feb 2017 20:46:52 +0000 (20:46 +0000)]
[LAA] Remove unused code (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295493
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Simon Pilgrim [Fri, 17 Feb 2017 20:43:32 +0000 (20:43 +0000)]
[X86][SSE] Add (V)MOVD folding pattern with zextloadi64i32 load node.
Fixes PRPR31309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295492
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Adrian Prantl [Fri, 17 Feb 2017 20:02:26 +0000 (20:02 +0000)]
Fix windows bots by locking down the target triple on this testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295490
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Matt Arsenault [Fri, 17 Feb 2017 19:49:10 +0000 (19:49 +0000)]
AMDGPU: Fix crashes on invalid icmp/fcmp intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295489
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Peter Collingbourne [Fri, 17 Feb 2017 19:43:45 +0000 (19:43 +0000)]
WholeProgramDevirt: For VCP use a 32-bit ConstantInt for the byte offset.
A future change will cause this byte offset to be inttoptr'd and then exported
via an absolute symbol. On the importing end we will expect the symbol to be
in range [0,2^32) so that it will fit into a 32-bit relocation. The problem
is that on 64-bit architectures if the offset is negative it will not be in
the correct range once we inttoptr it.
This change causes us to use a 32-bit integer so that it can be inttoptr'd
(which zero extends) into the correct range.
Differential Revision: https://reviews.llvm.org/D30016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295487
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Adrian Prantl [Fri, 17 Feb 2017 19:42:32 +0000 (19:42 +0000)]
Debug Info: Sort frame index expressions before emitting them.
This fixes PR31381, which caused an assertion and/or invalid debug info.
This affects debug variables that have multiple fragments in the MMI
side (i.e.: in the stack frame) table.
rdar://problem/
30571676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295486
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Petr Hosek [Fri, 17 Feb 2017 19:29:12 +0000 (19:29 +0000)]
[CMake] Support externalizing debug info on non-Darwin platforms
On other platorms, we use objcopy to export the debug info.
Differential Revision: https://reviews.llvm.org/D28575
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295481
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Simon Pilgrim [Fri, 17 Feb 2017 19:24:55 +0000 (19:24 +0000)]
[X86][SHA] Add SHA stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295479
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Artyom Skrobov [Fri, 17 Feb 2017 18:59:16 +0000 (18:59 +0000)]
In Thumb1 mode, the custom lowering for ARMISD::CMPZ could never emit tADDi3
Reviewers: jmolloy, t.p.northover
Reviewed By: t.p.northover
Subscribers: t.p.northover, aemerson, rengolin, llvm-commits
Differential Revision: https://reviews.llvm.org/D30097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295478
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Simon Pilgrim [Fri, 17 Feb 2017 18:51:53 +0000 (18:51 +0000)]
[X86][TBM] Add TBM stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295477
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Tim Northover [Fri, 17 Feb 2017 18:50:15 +0000 (18:50 +0000)]
GlobalISel: verify that generic loads & stores have a mem operand.
The mem operand is used by GlobalISel to convey atomic constraints so dropping
it is invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295476
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Joel Jones [Fri, 17 Feb 2017 18:34:24 +0000 (18:34 +0000)]
[AArch64] Add Cavium ThunderX support
This set of patches adds support for Cavium ThunderX ARM64 processors:
* ThunderX
* ThunderX T81
* ThunderX T83
* ThunderX T88
Patch by Stefan Teleman
Differential Revision: https://reviews.llvm.org/D28891
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295475
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Peter Collingbourne [Fri, 17 Feb 2017 18:17:04 +0000 (18:17 +0000)]
WholeProgramDevirt: Examine the function body when deciding whether functions are readnone.
The goal is to get an analysis result even for de-refineable functions.
Differential Revision: https://reviews.llvm.org/D29803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295472
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Simon Pilgrim [Fri, 17 Feb 2017 18:00:43 +0000 (18:00 +0000)]
[X86][BMI] Add BMI2 stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295470
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Peter Collingbourne [Fri, 17 Feb 2017 17:36:52 +0000 (17:36 +0000)]
opt: Rename -default-data-layout flag to -data-layout and make it always override the layout.
There isn't much point in a flag that only works if the data layout is empty.
Differential Revision: https://reviews.llvm.org/D30014
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295468
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Justin Bogner [Fri, 17 Feb 2017 17:34:37 +0000 (17:34 +0000)]
OptDiag: Rename DiagnosticInfoWithDebugLoc to WithLocation. NFC
This generalizes the name in preparation for decoupling the concept
from DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295465
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Rui Ueyama [Fri, 17 Feb 2017 17:32:54 +0000 (17:32 +0000)]
MC/COFF: Do not emit forward associative section referenceds.
MSVC link.exe cannot handle associative sections that refer later
sections in the section header. Technically, such COFF object doesn't
violate the Microsoft COFF spec, as the spec doesn't say anything
about that, but still we should avoid doing that to make it compatible
with MS tools.
This patch assigns smaller section numbers to non-associative sections
and larger numbers to associative sections. This should resolve the
compatibility issue.
Differential Revision: https://reviews.llvm.org/D30080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295464
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Sanjay Patel [Fri, 17 Feb 2017 17:13:27 +0000 (17:13 +0000)]
[DAGCombiner] split i1 select-of-constants from non-i1 case; NFCI
I can't find any tests of the non-i1 code path, so it may be unnecessary at this point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295463
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Simon Pilgrim [Fri, 17 Feb 2017 17:11:00 +0000 (17:11 +0000)]
[X86][BMI] Add BMI stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295462
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Sanjay Patel [Fri, 17 Feb 2017 16:43:43 +0000 (16:43 +0000)]
[PowerPC] add tests for select-of-constants; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295460
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Sanjay Patel [Fri, 17 Feb 2017 16:34:13 +0000 (16:34 +0000)]
[ARM] add tests for select-of-constants; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295459
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Matthew Simpson [Fri, 17 Feb 2017 16:09:07 +0000 (16:09 +0000)]
[LV] Remove constant restriction for vector phi creation
We previously only created a vector phi node for an induction variable if its
step had a constant integer type. However, the step actually only needs to be
loop-invariant. We only handle inductions having loop-invariant steps, so this
patch should enable vector phi node creation for all integer induction
variables that will be vectorized.
Differential Revision: https://reviews.llvm.org/D29956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295456
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Simon Pilgrim [Fri, 17 Feb 2017 16:01:16 +0000 (16:01 +0000)]
Fix signed/unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295453
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Sam Parker [Fri, 17 Feb 2017 15:42:44 +0000 (15:42 +0000)]
[ARM] Replace HasT2ExtractPack with HasDSP
Removed the HasT2ExtractPack feature and replaced its references
with HasDSP. This then allows the Thumb2 extend instructions to be
selected for ARMv8M +dsp. These instruction descriptions have also
been refactored and more target tests have been added for their isel.
Differential Revision: https://reviews.llvm.org/D29623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295452
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Simon Pilgrim [Fri, 17 Feb 2017 15:14:48 +0000 (15:14 +0000)]
[DAGCombine] Recognise any_extend_vector_inreg and truncation style shuffle masks
During legalization we are often creating shuffles (via a build_vector scalarization stage) that are "any_extend_vector_inreg" style masks, and also other masks that are the equivalent of "truncate_vector_inreg" (if we had such a thing).
This patch is an attempt to match these cases to help undo the effects of just leaving shuffle lowering to handle it - which typically means we lose track of the undefined elements of the shuffles resulting in an unnecessary extension+truncation stage for widened illegal types.
The 2011-10-21-widen-cmp.ll regression will be fixed by making SIGN_EXTEND_VECTOR_IN_REG legal in SSE instead of lowering them to X86ISD::VSEXT (PR31712).
Differential Revision: https://reviews.llvm.org/D29454
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295451
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Sanjay Patel [Fri, 17 Feb 2017 14:21:59 +0000 (14:21 +0000)]
[DAGCombiner] improve readability; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295447
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Diana Picus [Fri, 17 Feb 2017 13:44:19 +0000 (13:44 +0000)]
[ARM] GlobalISel: Clean up some helpers
Return invalid opcodes when some of the helpers in the instruction selection
pass can't handle a given combination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295446
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Diana Picus [Fri, 17 Feb 2017 13:14:25 +0000 (13:14 +0000)]
[ARM] GlobalISel: Check mappings used by reg bank select
Add some asserts to make sure we're using the mappings that we think we're
using. This is to keep us from accidentally breaking functionality while moving
to TableGen'erated mappings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295441
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Diana Picus [Fri, 17 Feb 2017 11:25:17 +0000 (11:25 +0000)]
[ARM] GlobalISel: Use Subtarget in Legalizer
Start using the Subtarget to make decisions about what's legal. In particular,
we only mark floating point operations as legal if we have VFP2, which is
something we should've done from the very start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295439
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Diana Picus [Fri, 17 Feb 2017 11:25:11 +0000 (11:25 +0000)]
[ARM] GlobalISel: Add end-to-end tests for double
Test some really basic functionality through the whole GlobalISel pipeline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295438
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Ismail Donmez [Fri, 17 Feb 2017 08:26:11 +0000 (08:26 +0000)]
Update Bugzilla URLs in docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295432
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Eugene Leviant [Fri, 17 Feb 2017 07:36:03 +0000 (07:36 +0000)]
InstCombine: fix extraction when performing vector/array punning
Differential revision: https://reviews.llvm.org/D29491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295429
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Craig Topper [Fri, 17 Feb 2017 07:07:24 +0000 (07:07 +0000)]
[IR][X86] Simplify some AutoUpgrade code slightly. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295426
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Craig Topper [Fri, 17 Feb 2017 07:07:21 +0000 (07:07 +0000)]
[IR][X86] Rename an AutoUpgrade helper function to more accurately match what intrinsics it handles. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295425
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Craig Topper [Fri, 17 Feb 2017 07:07:19 +0000 (07:07 +0000)]
[IR][X86] Move X86 specific portions of UpgradeIntrinsicFunction1 to a couple helper functions. NFC
This enables some early outs to avoid repeatedly using IsX86 check to qualify. I hope to continue to improve this to shorten the lengths of some of the string comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295424
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Andrew Wilkins [Fri, 17 Feb 2017 05:41:05 +0000 (05:41 +0000)]
Go binding: Add methods for missing PassManagerBuilder C APIs
Patch by Ryuichi Hayashida!
Differential Revision: http://reviews.llvm.org/D30042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295420
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Sanjoy Das [Fri, 17 Feb 2017 04:21:14 +0000 (04:21 +0000)]
[JumpThreading] Re-enable JumpThreading for guards
Summary:
JumpThreading for guards feature has been reverted at https://reviews.llvm.org/rL295200
due to the following problem: the feature used the following algorithm for detection of
diamond patters:
1. Find a block with 2 predecessors;
2. Check that these blocks have a common single parent;
3. Check that the parent's terminator is a branch instruction.
The problem is that these checks are insufficient. They may pass for a non-diamond
construction in case if those two predecessors are actually the same block. This may
happen if parent's terminator is a br (either conditional or unconditional) to a block
that ends with "switch" instruction with exactly two branches going to one block.
This patch re-enables the JumpThreading for guards and fixes this issue by adding the
check that those found predecessors are actually different blocks. This guarantees that
parent's terminator is a conditional branch with exactly 2 different successors, which
is now ensured by assertions. It also adds two more tests for this situation (with parent's
terminator being a conditional and an unconditional branch).
Patch by Max Kazantsev!
Reviewers: anna, sanjoy, reames
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295410
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Rafael Espindola [Fri, 17 Feb 2017 02:08:58 +0000 (02:08 +0000)]
Revert "[Hexagon] Start using regmasks on calls"
This reverts commit r295371.
It broke windows bots:
http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295402
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Dean Michael Berris [Fri, 17 Feb 2017 01:47:16 +0000 (01:47 +0000)]
[XRAY] [x86_64] Adding a Flight Data filetype reader to the llvm-xray Trace implementation.
Summary:
The file type packs function trace data onto disk from potentially multiple
threads that are aggregated and flushed during the course of an instrumented
program's runtime.
It is named FDR mode or Flight Data recorder as an analogy to plane
blackboxes, which instrument a running system without access to IO.
The writer code is defined in compiler-rt in xray_fdr_logging.h/cc
Reviewers: rSerge, kcc, dberris
Reviewed By: dberris
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D29697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295397
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Teresa Johnson [Fri, 17 Feb 2017 01:23:28 +0000 (01:23 +0000)]
Move test to X86 subdirectory for bot failures
Second attempt at fixing bot failures from r295384.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295395
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