OSDN Git Service
Craig Topper [Thu, 23 Nov 2017 03:24:00 +0000 (03:24 +0000)]
[X86] Remove unnecessary check for is128BitVector. NFC
256 and 512 bit vectors were picked off earlier in the function. Lots of code between there and here already assumed 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318893
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Craig Topper [Thu, 23 Nov 2017 03:23:59 +0000 (03:23 +0000)]
[X86] Simplify some bitmasking and use llvm_unreachable to mark an impossible case. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318892
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Craig Topper [Thu, 23 Nov 2017 03:23:58 +0000 (03:23 +0000)]
[X86] Remove a ternary operator that can only ever be false. NFC
We are checking for AVX512 in an SSE1 only block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318891
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Yaxun Liu [Thu, 23 Nov 2017 03:08:51 +0000 (03:08 +0000)]
[NFC] CodeGen: Handle shift amount type in DAGTypeLegalizer::SplitInteger
This patch reverts change to X86TargetLowering::getScalarShiftAmountTy in
rL318727 and move the logic to DAGTypeLegalizer::SplitInteger.
The reason is that getScalarShiftAmountTy returns a shift amount type that
is suitable for common use cases in CodeGen. DAGTypeLegalizer::SplitInteger
is a rare situation which requires a shift amount type larger than what
getScalarShiftAmountTy. In this case, it is more reasonable to do special
handling of shift amount type in DAGTypeLegalizer::SplitInteger only. If
similar situations arises the logic may be moved to a separate function.
Differential Revision: https://reviews.llvm.org/D40320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318890
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David Blaikie [Thu, 23 Nov 2017 00:08:40 +0000 (00:08 +0000)]
Instrumentation.h: Remove dead/untested code for DFSan JIT support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318887
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Craig Topper [Wed, 22 Nov 2017 23:35:12 +0000 (23:35 +0000)]
[X86] Regenerate the vector-popcnt and vector-tzcnt tests to get BITALG CHECK linse on all functions not just the vXi16/vXi8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318885
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Evandro Menezes [Wed, 22 Nov 2017 22:48:50 +0000 (22:48 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix the modeling of some loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318884
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Fedor Sergeev [Wed, 22 Nov 2017 20:59:53 +0000 (20:59 +0000)]
IR printing improvement for loop passes
Summary:
Loop-pass printing is somewhat deficient since it does not provide the
context around the loop (e.g. preheader). This context information becomes
pretty essential when analyzing transformations that move stuff out of the loop.
Extending printLoop to cover preheader and exit blocks (if any).
Reviewers: sanjoy, silvas, weimingz
Reviewed By: sanjoy
Subscribers: apilipenko, skatkov, llvm-commits
Differential Revision: https://reviews.llvm.org/D40246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318878
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Krzysztof Parzyszek [Wed, 22 Nov 2017 20:56:23 +0000 (20:56 +0000)]
[Hexagon] Implement buildVector32 and buildVector64 as utility functions
Change LowerBUILD_VECTOR to use those functions. This commit will tempora-
rily affect constant vector generation (it will generate constant-extended
values instead of non-extended combines), but the code for the general case
should be better. The constant selection part will be fixed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318877
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Krzysztof Parzyszek [Wed, 22 Nov 2017 20:55:41 +0000 (20:55 +0000)]
[Hexagon] Add patterns to select A2_combine_ll and its variants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318876
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Krzysztof Parzyszek [Wed, 22 Nov 2017 20:43:00 +0000 (20:43 +0000)]
[Hexagon] Remove trailing spaces, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318875
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Paul Robinson [Wed, 22 Nov 2017 20:31:39 +0000 (20:31 +0000)]
Add a missing include found by modules bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318873
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Craig Topper [Wed, 22 Nov 2017 20:05:57 +0000 (20:05 +0000)]
[X86] Support v32i16/v64i8 CTLZ using lookup table.
Had to tweak the setcc's used by the code to use a vXi1 result type with a sign extend back to vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318871
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Craig Topper [Wed, 22 Nov 2017 20:05:54 +0000 (20:05 +0000)]
[X86] Move the BITALG setOperationAction code into the hasBWI section to match what is done for VPOPCNTDQ in the AVX512F block. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318870
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Craig Topper [Wed, 22 Nov 2017 20:05:51 +0000 (20:05 +0000)]
[X86] Sink the MGATHER setOperationActions for AVX2 into the AVX block where most of the rest of the AVX2 legalization lives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318869
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Rafael Espindola [Wed, 22 Nov 2017 20:02:57 +0000 (20:02 +0000)]
Remove unnecessary code.
There is already an RAII in place to discard the temporary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318868
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Rafael Espindola [Wed, 22 Nov 2017 19:59:05 +0000 (19:59 +0000)]
Allow TempFile::discard to be called twice.
We already allowed keep+discard. It is important to be able to discard
a temporary if a rename fail. It is also convenient as it allows the
use of RAII for discarding.
Allow discarding twice for similar reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318867
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Paul Robinson [Wed, 22 Nov 2017 18:39:26 +0000 (18:39 +0000)]
Remove unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318861
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Peter Collingbourne [Wed, 22 Nov 2017 18:27:31 +0000 (18:27 +0000)]
CachePruning: Allow limiting the number of files in the cache directory.
The default limit is
1000000 but it can be configured with a cache
policy. The motivation is that some filesystems (notably ext4) have
a limit on the number of files that can be contained in a directory
(separate from the inode limit).
Differential Revision: https://reviews.llvm.org/D40327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318857
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Paul Robinson [Wed, 22 Nov 2017 18:23:55 +0000 (18:23 +0000)]
[DwarfDump] -debug-line=offset applies to .dwo too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318856
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Craig Topper [Wed, 22 Nov 2017 18:23:40 +0000 (18:23 +0000)]
[X86] Spell penryn correctly in some comments. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318855
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Yaxun Liu [Wed, 22 Nov 2017 16:13:35 +0000 (16:13 +0000)]
[AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argument
SITargetLowering::LowerCall uses dummy pointer info for byval argument, which causes
flat load instead of buffer load.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D40040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318844
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Paul Robinson [Wed, 22 Nov 2017 15:48:30 +0000 (15:48 +0000)]
[DebugInfo] Dump a .debug_line section, including line-number program,
without any compile units.
Differential Revision: https://reviews.llvm.org/D40114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318842
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Dmitry Preobrazhensky [Wed, 22 Nov 2017 15:47:27 +0000 (15:47 +0000)]
[AMDGPU][mc][tests] Updated generated lit tests for GFX8/9
Summary:
Added tests to better cover features introduced by commit rL318675.
See http://llvm.org/viewvc/llvm-project?view=revision&revision=318675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318841
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Paul Robinson [Wed, 22 Nov 2017 15:33:17 +0000 (15:33 +0000)]
[DWARFv5] Support DW_FORM_strp in the .debug_line.dwo header.
As a side effect, the .debug_line section will be dumped in physical
order, rather than in the order that compile units refer to their
associated portions of the .debug_line section. These are probably
always the same order anyway, and no tests noticed the difference.
Differential Revision: https://reviews.llvm.org/D39854
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318839
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Paul Robinson [Wed, 22 Nov 2017 15:14:49 +0000 (15:14 +0000)]
[DWARF] Fix handling of extended line-number opcodes
Differential Revision: https://reviews.llvm.org/D40200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318838
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Nicolai Haehnle [Wed, 22 Nov 2017 12:25:21 +0000 (12:25 +0000)]
AMDGPU: Consider memory dependencies with moved instructions in SILoadStoreOptimizer
Summary:
This bug seems to have gone unnoticed because critical cases with LDS
instructions are eliminated by the peephole optimizer.
However, equivalent situations arise with buffer loads and stores
as well, so this fixes regressions since r317751 ("AMDGPU: Merge
S_BUFFER_LOAD_DWORD_IMM into x2, x4").
Fixes at least:
KHR-GL45.shader_storage_buffer_object.basic-operations-case1-cs
KHR-GL45.cull_distance.functional
piglit tes-input-gl_ClipDistance.shader_test
... and probably more
Change-Id: I0e371536288eb8e6afeaa241a185266fd45d129d
Reviewers: arsenm, mareko, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D40303
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318829
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Jonas Paulsson [Wed, 22 Nov 2017 08:58:30 +0000 (08:58 +0000)]
[DAGCombiner] Bugfix in isAlias().
Since i1 is a legal type, this:
NumBytes = Op1->getMemoryVT().getSizeInBits() >> 3;
is wrong and should be instead
NumBytes = Op0->getMemoryVT().getStoreSize();
There seems to be more places where this should be fixed outside DAGCombiner.
Review: Hal Finkel
https://bugs.llvm.org/show_bug.cgi?id=35366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318824
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Craig Topper [Wed, 22 Nov 2017 08:10:54 +0000 (08:10 +0000)]
[X86] Add an X86ISD::MSCATTER node for consistency with the X86ISD::MGATHER.
This makes the fact that X86 needs an explicit mask output not part of the type constraint for the ISD::MSCATTER.
This also gives the X86ISD::MGATHER/MSCATTER nodes a common base class simplifying the address selection code in X86ISelDAGToDAG.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318823
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George Rimar [Wed, 22 Nov 2017 07:53:48 +0000 (07:53 +0000)]
[llvm-tblgen] - Stop using std::string in RecordKeeper.
RecordKeeper::getDef() is a hot place, it shows up in profiling
and it creates std::string instance for each search in RecordMap
though RecordKeeper::RecordMap can use StringRef as a key
instead to avoid that. Patch do that change.
Differential revision: https://reviews.llvm.org/D40170
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318822
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Craig Topper [Wed, 22 Nov 2017 07:11:03 +0000 (07:11 +0000)]
[X86] Lower all ISD::MGATHER nodes to X86ISD:MGATHER.
Now we consistently represent the mask result without relying on isel ignoring it.
We now have a more general SDNode and type constraints to represent these nodes in isel patterns. This allows us to present both both vXi1 and XMM/YMM mask types with a single set of constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318821
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Craig Topper [Wed, 22 Nov 2017 07:11:01 +0000 (07:11 +0000)]
[SelectionDAG] Add a isel matcher op to check the type of node results other than result 0.
I plan to use this to check the type of the mask result of masked gathers in the X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318820
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Max Kazantsev [Wed, 22 Nov 2017 06:21:39 +0000 (06:21 +0000)]
[SCEV] Strengthen variance condition in calculateLoopDisposition
Given loops `L1` and `L2` with AddRecs `AR1` and `AR2` varying in them respectively.
When identifying loop disposition of `AR2` w.r.t. `L1`, we only say that it is varying if
`L1` contains `L2`. But there is also a possible situation where `L1` and `L2` are
consecutive sibling loops within the parent loop. In this case, `AR2` is also varying
w.r.t. `L1`, but we don't correctly identify it.
It can lead, for exaple, to attempt of incorrect folding. Consider:
AR1 = {a,+,b}<L1>
AR2 = {c,+,d}<L2>
EXAR2 = sext(AR1)
MUL = mul AR1, EXAR2
If we incorrectly assume that `EXAR2` is invariant w.r.t. `L1`, we can end up trying to
construct something like: `{a * {c,+,d}<L2>,+,b * {c,+,d}<L2>}<L1>`, which is incorrect
because `AR2` is not available on entrance of `L1`.
Both situations "`L1` contains `L2`" and "`L1` preceeds sibling loop `L2`" can be handled
with one check: "header of `L1` dominates header of `L2`". This patch replaces the old
insufficient check with this one.
Differential Revision: https://reviews.llvm.org/D39453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318819
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Davide Italiano [Wed, 22 Nov 2017 03:04:55 +0000 (03:04 +0000)]
[SCCP] Pick the right lattice value for constants.
After the dataflow algorithm proves that an argument is constant,
it replaces it value with the integer constant and drops the lattice
value associated to the DEF.
e.g. in the example we have @f() that's called twice:
call @f(undef, ...)
call @f(2, ...)
`undef` MEET 2 = 2 so we replace the argument and all its uses with
the constant 2.
Shortly after, tryToReplaceWithConstantRange() tries to get the lattice
value for the argument we just replaced, causing an assertion.
This function is a little peculiar as it runs when we're doing replacement
and not as part of the solver but still queries the solver.
The fix is that of checking whether we replaced the value already and
get a temporary lattice value for the constant.
Thanks to Zhendong Su for the report!
Fixes PR35357.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318817
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Craig Topper [Tue, 21 Nov 2017 23:36:42 +0000 (23:36 +0000)]
[X86] Move the information about the feature bits used by compiler-rt and shared by Host.cpp to a .def file and TargetParser.h so clang can make use of it.
Since we keep Host.cpp and compiler-rt relatively in sync, clang can use this information as a proxy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318814
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Krzysztof Parzyszek [Tue, 21 Nov 2017 22:13:16 +0000 (22:13 +0000)]
[Hexagon] Add HexagonSubtarget::getVectorLength()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318807
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Peter Collingbourne [Tue, 21 Nov 2017 22:06:20 +0000 (22:06 +0000)]
Object: Improve COFF irsymtab comdat representation.
Change the representation of COFF comdats so that a COFF linker
is able to accurately resolve comdats between IR and native object
files. Specifically, apply name mangling to comdat names consistently
with native object files, and do not export comdats with an internal
leader because they do not affect symbol resolution.
Differential Revision: https://reviews.llvm.org/D40278
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318805
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Evandro Menezes [Tue, 21 Nov 2017 21:33:52 +0000 (21:33 +0000)]
[TableGen] Improve error reporting
When searching for a resource unit, use the reference location instead of
the definition location in case of an error.
Differential revision: https://reviews.llvm.org/D40263
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318803
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Krzysztof Parzyszek [Tue, 21 Nov 2017 21:05:51 +0000 (21:05 +0000)]
[Hexagon] Make sure that RDF does not remove EH_LABELs
Since EH_LABELs (and other labels) no longer have "side-effects", they
should be checked for separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318801
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Craig Topper [Tue, 21 Nov 2017 21:05:21 +0000 (21:05 +0000)]
[X86] Allow vpclmulqdq instructions to be commuted during isel to allow load folding.
The commuting patterns for the AVX version actually still had priority over the new patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318800
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Craig Topper [Tue, 21 Nov 2017 21:05:18 +0000 (21:05 +0000)]
[X86] Add BITALG, VAES, VBMI2, VNNI, VPCLMULQDQ, and VPOPCNTDQ instructions to icelake CPU.
This is based on table 1-1 of the October 2017 revision of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318799
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Nirav Dave [Tue, 21 Nov 2017 19:28:13 +0000 (19:28 +0000)]
Avoid unecessary opsize byte in segment move to memory
Segment moves to memory are always 16-bit. Remove invalid 32 and 64
bit variants.
Recommiting with missing clang inline assembly test change.
Fixes PR34478.
Reviewers: rnk, craig.topper
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318797
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Craig Topper [Tue, 21 Nov 2017 18:50:41 +0000 (18:50 +0000)]
[X86] Sort bits in getHostCPUFeatures again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318792
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Chad Rosier [Tue, 21 Nov 2017 18:08:34 +0000 (18:08 +0000)]
[AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects.
This partially reverts r298851. The the underlying issue is that we don't
currently model the dependency between mrs (read system register) and
msr (write system register) instructions.
Something like the below should never be reordered:
msr TPIDR_EL0, x0 ;; set thread pointer
mrs x8, TPIDR_EL0 ;; read thread pointer
but was being reordered after r298851. The functional part of the patch
that wasn't reverted needed to remain in place in order to not break
r299462.
PR35317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318788
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Hans Wennborg [Tue, 21 Nov 2017 18:00:01 +0000 (18:00 +0000)]
Fix r318786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318787
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Nuno Lopes [Tue, 21 Nov 2017 17:53:19 +0000 (17:53 +0000)]
removed unused private method decl. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318786
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Hans Wennborg [Tue, 21 Nov 2017 17:22:19 +0000 (17:22 +0000)]
Rename test/Transforms/CountingFunctionInserter -> EntryExitInstrumenter
The pass was renamed in r318195.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318784
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Hans Wennborg [Tue, 21 Nov 2017 17:22:19 +0000 (17:22 +0000)]
EntryExitInstrumenter: support __cyg_profile_func_enter_bare
It works just like __cyg_profile_func_enter but takes no arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318783
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Oliver Stannard [Tue, 21 Nov 2017 16:20:25 +0000 (16:20 +0000)]
[ARM] Remove pre-UAL FLDM/FSTM aliases
These are pre-UAL syntax, and we don't support any other pre-UAL instructions,
with the exception of FLDMX/FSTMX, which don't have a UAL equivalent. Therefore
there's no reason to keep them or their AsmParser hacks around.
With the AsmParser hacks removed, the FLDMX and FSTMX instructions get the same
operand diagnostics as the UAL instructions.
Differential revision: https://reviews.llvm.org/D39196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318777
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Alina Sbirlea [Tue, 21 Nov 2017 15:45:46 +0000 (15:45 +0000)]
Add MemorySSA as loop dependency, disabled by default [NFC].
Summary:
First step in adding MemorySSA as dependency for loop pass manager.
Adding the dependency under a flag.
New pass manager: MSSA pointer in LoopStandardAnalysisResults can be null.
Legacy and new pass manager: Use cl::opt EnableMSSALoopDependency. Disabled by default.
Reviewers: sanjoy, davide, gberry
Subscribers: mehdi_amini, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D40274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318772
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Oliver Stannard [Tue, 21 Nov 2017 15:34:15 +0000 (15:34 +0000)]
[ARM] Don't omit non-default predication code
This was causing the (invalid) predicated versions of the NEON VRINTX and
VRINTZ instructions to be accepted, with the condition code being ignored.
Also, there is no NEON VRINTR instruction, so that part of the check was not
necessary.
Differential revision: https://reviews.llvm.org/D39193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318771
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Oliver Stannard [Tue, 21 Nov 2017 15:16:50 +0000 (15:16 +0000)]
[Asm] Improve "too few operands" errors
- We can still emit this error if the actual instruction has two or more
operands missing compared to the expected one.
- We should only emit this error once per instruction.
Differential revision: https://reviews.llvm.org/D36746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318770
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Oliver Stannard [Tue, 21 Nov 2017 15:12:05 +0000 (15:12 +0000)]
[Asm] Finish matching once end of formal and actual lists reached (NFC)
This is NFC, as the matcher would continue looping up to the maximum
number of operands with no effect, but this should improve performance a
bit, and makes the debug trace clearer.
Differential revision: https://reviews.llvm.org/D36744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318769
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Sander de Smalen [Tue, 21 Nov 2017 15:07:43 +0000 (15:07 +0000)]
Revert r318759 due to make check-all failure on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318768
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Oliver Stannard [Tue, 21 Nov 2017 15:06:01 +0000 (15:06 +0000)]
[ARM] Add diagnostics for SPR/DPR lists
Differential revision: https://reviews.llvm.org/D39195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318766
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Alexey Bataev [Tue, 21 Nov 2017 14:49:13 +0000 (14:49 +0000)]
[InstCombine] Test for PR35354: unable to vectorize loop with std::max
on floats, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318764
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Sam Kolton [Tue, 21 Nov 2017 14:11:59 +0000 (14:11 +0000)]
[AMDGPU] SDWA: remove omod src operand for VOP2b instructions
Summary: VOP2b instructions (v_subbrev_u32, v_add_i32 ...) shouldn't support OMod operand in SDWA encoding
Reviewers: rampitec, dp
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D40172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318761
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Alex Bradbury [Tue, 21 Nov 2017 12:41:41 +0000 (12:41 +0000)]
[RISCV][NFC] Remove unnecessary {} around single statement if block
Almost too trivial to worry about, but it seems worth having consistency with
upcoming commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318760
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Sander de Smalen [Tue, 21 Nov 2017 12:26:06 +0000 (12:26 +0000)]
[TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.
Summary:
The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand.
This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate.
Reviewers: craig.topper, olista01, rengolin, stoklund
Reviewed By: olista01
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D40011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318759
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Simon Pilgrim [Tue, 21 Nov 2017 12:02:18 +0000 (12:02 +0000)]
[X86][XOP] Add missing scheduler classes to XOP instructions
All match equivalent basic classes (WritePHAdd, WriteFAdd etc.) according to both the AMD 15h SOG and Agner's tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318758
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Alex Bradbury [Tue, 21 Nov 2017 12:00:19 +0000 (12:00 +0000)]
[RISCV][NFC] Clean up RISCVDAGToDAGISel::Select
As pointed out in post-commit review of r318738, `return ReplaceNode(..)` when
both ReplaceNode and the current function return void is confusing. This patch
moves to using a more obvious early return, and moves to just using an if to
catch the one case we currently care about. A future patch that adds further
custom instruction selection can introduce a switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318757
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Martell Malone [Tue, 21 Nov 2017 11:30:20 +0000 (11:30 +0000)]
[ARM] Use SEH exceptions on thumbv7-windows
Reviewers: mstorsjo
Differential Revision: https://reviews.llvm.org/D40286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318756
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Simon Pilgrim [Tue, 21 Nov 2017 11:17:11 +0000 (11:17 +0000)]
[X86][LWP] Add missing LWP itinerary class to lwpins instructions
It's on all other LWP instruction but I missed it from lwpins, despite similar scheduling behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318751
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Eugene Leviant [Tue, 21 Nov 2017 11:01:28 +0000 (11:01 +0000)]
[MI scheduler] Fix VADD and VSUB in cortex-a57 model
This patch fixes instregex for interger vector add/sub instructions
Differential revision: https://reviews.llvm.org/D40254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318749
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Coby Tayree [Tue, 21 Nov 2017 10:32:42 +0000 (10:32 +0000)]
[x86][icelake]BITALG
vpopcnt{b,w}
Differential Revision: https://reviews.llvm.org/D40213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318748
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Diana Picus [Tue, 21 Nov 2017 10:17:02 +0000 (10:17 +0000)]
[ARM GlobalISel] Add comment for r318398. NFC.
Mention the purpose of the BICri tests added by r318398, as requested in
post-commit review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318747
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Coby Tayree [Tue, 21 Nov 2017 10:04:28 +0000 (10:04 +0000)]
[x86][icelake]VNNI
Introducing Vector Neural Network Instructions, consisting of:
vpdpbusd{s}
vpdpwssd{s}
Differential Revision: https://reviews.llvm.org/D40208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318746
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Coby Tayree [Tue, 21 Nov 2017 09:48:44 +0000 (09:48 +0000)]
[x86][icelake]vbmi2
introducing vbmi2, consisting of
vpcompress{b,w}
vpexpand{b,w}
vpsh{l,r}d{w,d,q}
vpsh{l,r}dv{w,d,q}
Differential Revision: https://reviews.llvm.org/D40206
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318745
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NAKAMURA Takumi [Tue, 21 Nov 2017 09:41:01 +0000 (09:41 +0000)]
SLPVectorizer.cpp: Avoid std::stable_sort(properlyDominates()).
properlyDominates() shouldn't be used as sort key. It causes different output between stdlibc++ and libc++.
Instead, I introduced RPOT. In most cases, it works for CSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318743
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Coby Tayree [Tue, 21 Nov 2017 09:30:33 +0000 (09:30 +0000)]
[x86][icelake]vpclmulqdq introduction
an icelake promotion of pclmulqdq
Differential Revision: https://reviews.llvm.org/D40101
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318741
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Coby Tayree [Tue, 21 Nov 2017 09:11:41 +0000 (09:11 +0000)]
[x86][icelake]VAES introduction
an icelake promotion of AES
Differential Revision: https://reviews.llvm.org/D40078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318740
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Alex Bradbury [Tue, 21 Nov 2017 08:23:08 +0000 (08:23 +0000)]
[RISCV] Use register X0 (ZERO) for constant 0
The obvious approach of defining a pattern like the one below actually doesn't
work:
`def : Pat<(i32 0), (i32 X0)>;`
As was noted when Lanai made this change (https://reviews.llvm.org/rL288215),
attempting to handle the constant 0 in tablegen leads to assertions due to a
physical register being used where a virtual register is expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318738
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Alex Bradbury [Tue, 21 Nov 2017 08:11:03 +0000 (08:11 +0000)]
[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318737
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Alex Bradbury [Tue, 21 Nov 2017 07:51:32 +0000 (07:51 +0000)]
[RISCV] Implement lowering of ISD::SELECT
Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and
ultimately the integer RISC-V conditional branch instructions), we choose to
expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch
will be created in the case where an ISD::SELECT condition value is created by
an ISD::SETCC node, which operates on XLen types. Other datatypes such as
floating point don't have conditional branch instructions, and lowering
ISD::SELECT allows more flexibility for handling these cases.
Differential Revision: https://reviews.llvm.org/D29937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318735
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Dean Michael Berris [Tue, 21 Nov 2017 07:16:57 +0000 (07:16 +0000)]
[XRay] Use optimistic logging model for FDR mode
Summary:
Before this change, the FDR mode implementation relied on at thread-exit
handling to return buffers back to the (global) buffer queue. This
introduces issues with the initialisation of the thread_local objects
which, even through the use of pthread_setspecific(...) may eventually
call into an allocation function. Similar to previous changes in this
line, we're finding that there is a huge potential for deadlocks when
initialising these thread-locals when the memory allocation
implementation is also xray-instrumented.
In this change, we limit the call to pthread_setspecific(...) to provide
a non-null value to associate to the key created with
pthread_key_create(...). While this doesn't completely eliminate the
potential for the deadlock(s), it does allow us to still clean up at
thread exit when we need to. The change is that we don't need to do more
work when starting and ending a thread's lifetime. We also have a test
to make sure that we actually can safely recycle the buffers in case we
end up re-using the buffer(s) available from the queue on multiple
thread entry/exits.
This change cuts across both LLVM and compiler-rt to allow us to update
both the XRay runtime implementation as well as the library support for
loading these new versions of the FDR mode logging. Version 2 of the FDR
logging implementation makes the following changes:
* Introduction of a new 'BufferExtents' metadata record that's outside
of the buffer's contents but are written before the actual buffer.
This data is associated to the Buffer handed out by the BufferQueue
rather than a record that occupies bytes in the actual buffer.
* Removal of the "end of buffer" records. This is in-line with the
changes we described above, to allow for optimistic logging without
explicit record writing at thread exit.
The optimistic logging model operates under the following assumptions:
* Threads writing to the buffers will potentially race with the thread
attempting to flush the log. To avoid this situation from occuring,
we make sure that when we've finalized the logging implementation,
that threads will see this finalization state on the next write, and
either choose to not write records the thread would have written or
write the record(s) in two phases -- first write the record(s), then
update the extents metadata.
* We change the buffer queue implementation so that once it's handed
out a buffer to a thread, that we assume that buffer is marked
"used" to be able to capture partial writes. None of this will be
safe to handle if threads are racing to write the extents records
and the reader thread is attempting to flush the log. The optimism
comes from the finalization routine being required to complete
before we attempt to flush the log.
This is a fairly significant semantics change for the FDR
implementation. This is why we've decided to update the version number
for FDR mode logs. The tools, however, still need to be able to support
older versions of the log until we finally deprecate those earlier
versions.
Reviewers: dblaikie, pelikan, kpw
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318733
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Craig Topper [Tue, 21 Nov 2017 06:28:15 +0000 (06:28 +0000)]
[X86] Simplify type constraints for AVX2 masked gather.
We don't need separate 32 and 64 node types. We can use SDTCisInt and SDTCisSameSizeAs to ensure the mask size the result type and is integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318732
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Serguei Katkov [Tue, 21 Nov 2017 06:03:43 +0000 (06:03 +0000)]
Revert "[CGP] Enable complex addr mode (2nd attempt)"
Revert the patch rl318728 causing buildbot hangs-ups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318731
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Craig Topper [Tue, 21 Nov 2017 06:01:20 +0000 (06:01 +0000)]
[X86] Simplify the predicates for avx2 masked gather patterns.
We don't need a dyn_cast and we only need to check the type of the index. The base ptr is guaranteed to be scalar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318730
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Rafael Espindola [Tue, 21 Nov 2017 05:35:45 +0000 (05:35 +0000)]
move static function. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318729
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Serguei Katkov [Tue, 21 Nov 2017 05:31:47 +0000 (05:31 +0000)]
[CGP] Enable complex addr mode (2nd attempt)
2nd attempt to enable complex addr modes after
fix of the crash by rL318638.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318728
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Yaxun Liu [Tue, 21 Nov 2017 02:29:54 +0000 (02:29 +0000)]
[AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type
DAGTypeLegalizer::SplitInteger uses default pointer size as shift amount constant type,
which causes less performant ISA in amdgcn---amdgiz target since the default pointer
type is i64 whereas the desired shift amount type is i32.
This patch fixes that by using TLI.getScalarShiftAmountTy in DAGTypeLegalizer::SplitInteger.
The X86 change is necessary since splitting i512 requires shifting amount of 256, which
cannot be held by i8.
Differential Revision: https://reviews.llvm.org/D40148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318727
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Rafael Espindola [Tue, 21 Nov 2017 01:52:44 +0000 (01:52 +0000)]
Split a rename_handle out of rename on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318725
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Richard Trieu [Tue, 21 Nov 2017 01:45:17 +0000 (01:45 +0000)]
Add default values for member functions.
Initialize IsVis2 and IsVis3 in SparcSubtarget::initializeSubtargetDependencies.
MSan detected uninitialized read of IsVis3 after r318704. Initializing the
variables to false will prevent undefined behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318724
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Zachary Turner [Tue, 21 Nov 2017 01:20:28 +0000 (01:20 +0000)]
Re-revert "Refactor debuginfo-tests."
This is still breaking greendragon.
At this point I give up until someone can fix the greendragon
bots, and I will probably abandon this effort in favor of using
a private github repository.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318722
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David Blaikie [Tue, 21 Nov 2017 00:33:17 +0000 (00:33 +0000)]
xray-record-yaml.h: Remove unused file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318715
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David Blaikie [Tue, 21 Nov 2017 00:23:19 +0000 (00:23 +0000)]
llvm-rc/ResourceScriptTokenList.h: Turns this into a .def file to imply that it's non-modular
Also undef the macros at the end of the file to make it easier to use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318714
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David Blaikie [Tue, 21 Nov 2017 00:23:19 +0000 (00:23 +0000)]
XRayRecord.h: Add missing #include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318713
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David Blaikie [Tue, 21 Nov 2017 00:23:17 +0000 (00:23 +0000)]
YAML/XRay/std::vector: Fix ODR violation by removing local specialization
There's a generic partial specialization for all std::vector<T> that
does what's desired, so no need for this full specialization that's
causing an ODR violation anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318712
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Davide Italiano [Tue, 21 Nov 2017 00:21:52 +0000 (00:21 +0000)]
[SCCP] If we replace with a constant, we can't replace with a range.
This microoptimization is NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318711
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Richard Trieu [Tue, 21 Nov 2017 00:12:18 +0000 (00:12 +0000)]
Revert r318678 to fix Clang test
r318678 caused the Clang test CodeGen/ms-inline-asm.c to start failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318710
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Vitaly Buka [Mon, 20 Nov 2017 23:37:56 +0000 (23:37 +0000)]
[msan] Don't sanitize "nosanitize" instructions
Reviewers: eugenis
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D40205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318708
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Craig Topper [Mon, 20 Nov 2017 23:08:50 +0000 (23:08 +0000)]
[SelectionDAG] When promoting the result of a VSELECT, make sure we promote the condition to the SetCC type for the final result type not the original type.
Normally this would be cleaned up by promoting the condition operand next. But in the attached case we promoted the result from v2i48 to v2i64 and the condition from v2i1 to v2i48. Then we tried to "promote" the v2i48 condition back to v2i1 because that's what the SetCC result type for v2i64 is on X86 with VLX. But promote is either a NOP or SIGN_EXTEND and this would need a truncation.
With the change here we now get the SetCC type of v2i1 when we're handling the result promotion and the operand no longer needs to be promoted itself.
Fixes PR35272.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318706
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Fedor Sergeev [Mon, 20 Nov 2017 22:33:58 +0000 (22:33 +0000)]
[Sparc] efficient pattern for UINT_TO_FP conversion
Summary:
while investigating performance degradation of imagick benchmark
there were found inefficient pattern for UINT_TO_FP conversion.
That pattern causes RAW hazard in assembly code. Specifically,
uitofp IR operator results in poor assembler :
st %i0, [%fp - 952]
ldd [%fp - 952], %f0
it stores 32-bit integer register into memory location and then
loads 64-bit floating point data from that location.
That is exactly RAW hazard case. To optimize that case it is
possible to use SPISD::ITOF and SPISD::XTOF for conversion from
integer to floating point data type and to use ISD::BITCAST to
copy from integer register into floating point register.
The fix is to write custom UINT_TO_FP pattern using SPISD::ITOF,
SPISD::XTOF, ISD::BITCAST.
Patch by Alexey Lapshin
Reviewers: fedor.sergeev, jyknight, dcederman, lero_chris
Reviewed By: jyknight
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36875
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318704
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David Blaikie [Mon, 20 Nov 2017 22:12:55 +0000 (22:12 +0000)]
Add ADL support to range based <algorithm> extensions
This adds support for ADL in the range based <algorithm> extensions
(llvm::for_each etc.).
Also adds the helper functions llvm::adl::begin and llvm::adl::end which wrap
std::begin and std::end with ADL support.
Saw this was missing from a recent llvm weekly post about adding llvm::for_each
and thought I might add it.
Patch by Stephen Dollberg!
Differential Revision: https://reviews.llvm.org/D40006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318703
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Zachary Turner [Mon, 20 Nov 2017 21:41:36 +0000 (21:41 +0000)]
Resubmit "Refactor debuginfo-tests" again.
This was reverted due to the tests being run twice on some
build bots. Each run had a slightly different configuration
due to the way in which it was being invoked. This fixes
the problem (albeit in a somewhat hacky way). Hopefully in
the future we can get rid of the workflow of running
debuginfo-tests as part of clang, and then this hack can
go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318697
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Hiroshi Yamauchi [Mon, 20 Nov 2017 21:38:43 +0000 (21:38 +0000)]
Fix a lld-x86_64-darwin13 build error.
Summary:
Fix this build error
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/15112/steps/build_Lld/logs/stdio
after https://reviews.llvm.org/rL318693
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318696
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Yonghong Song [Mon, 20 Nov 2017 21:37:58 +0000 (21:37 +0000)]
bpf: add a test case for trunc-op optimization
Commit
b5cbc7760ab8 ("[bpf] allow direct and indirect calls")
allowed more than one function in the bpf program, and
commit
114353884415 ("bpf: fix a bug in trunc-op optimization")
fixed a bug in trunc-op optimization which only showed up
with more than one function in the bpf program.
This patch added a test case for trunc-op optimization
for bpf programs with two functions. Reverting commit
"bpf: fix a bug in trunc-op optimization" will cause
failure for this test case.
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318695
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Hiroshi Yamauchi [Mon, 20 Nov 2017 21:03:38 +0000 (21:03 +0000)]
Add heuristics for irreducible loop metadata under PGO
Summary:
Add the following heuristics for irreducible loop metadata:
- When an irreducible loop header is missing the loop header weight metadata,
give it the minimum weight seen among other headers.
- Annotate indirectbr targets with the loop header weight metadata (as they are
likely to become irreducible loop headers after indirectbr tail duplication.)
These greatly improve the accuracy of the block frequency info of the Python
interpreter loop (eg. from ~3-16x off down to ~40-55% off) and the Python
performance (eg. unpack_sequence from ~50% slower to ~8% faster than GCC) due to
better register allocation under PGO.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318693
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Simon Pilgrim [Mon, 20 Nov 2017 19:18:33 +0000 (19:18 +0000)]
Fix spelling in comment. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318687
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Mandeep Singh Grang [Mon, 20 Nov 2017 19:17:11 +0000 (19:17 +0000)]
Revert "[SelectionDAG] Make sorting predicate stronger to remove non-deterministic ordering"
This broke the bots. Reverting this until I can fix the failures.
This reverts commit
5a3db2856d12a3c4b400f487d39f8f05989e79f0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318686
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