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Marc-André Lureau [Mon, 12 Dec 2016 22:17:59 +0000 (01:17 +0300)]
trace-events: spelling fix
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id:
20161212221759.28949-1-marcandre.lureau@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Peter Maydell [Mon, 16 Jan 2017 12:41:35 +0000 (12:41 +0000)]
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.9-pull-request' into staging
# gpg: Signature made Sat 14 Jan 2017 09:06:31 GMT
# gpg: using RSA key 0xF30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg: aka "Laurent Vivier <laurent@vivier.eu>"
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/m68k-for-2.9-pull-request:
target-m68k: increment/decrement with SP
target-m68k: CAS doesn't need aligned access
target-m68k: manage pre-dec et post-inc in CAS
target-m68k: fix gen_flush_flags()
target-m68k: fix bit operation with immediate value
m68k: Remove PCI and USB from config file
target-m68k: Implement bfffo
target-m68k: Implement bitfield ops for memory
target-m68k: Implement bitfield ops for registers
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 16 Jan 2017 11:17:38 +0000 (11:17 +0000)]
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-
20170113' into staging
Fixes and more queued patches
# gpg: Signature made Fri 13 Jan 2017 20:00:53 GMT
# gpg: using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B
* remotes/rth/tags/pull-tcg-
20170113:
tcg/aarch64: Fix tcg_out_movi
tcg/aarch64: Fix addsub2 for 0+C
target/arm: Fix ubfx et al for aarch64
tcg/s390: Fix merge error with facilities
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Laurent Vivier [Fri, 13 Jan 2017 18:36:33 +0000 (19:36 +0100)]
target-m68k: increment/decrement with SP
On 680x0 family only.
Address Register indirect With postincrement:
When using the stack pointer (A7) with byte size data, the register
is incremented by two.
Address Register indirect With predecrement:
When using the stack pointer (A7) with byte size data, the register
is decremented by two.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Thomas Huth <huth@tuxfamily.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
1484332593-16782-6-git-send-email-laurent@vivier.eu>
Laurent Vivier [Fri, 13 Jan 2017 18:36:32 +0000 (19:36 +0100)]
target-m68k: CAS doesn't need aligned access
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
1484332593-16782-5-git-send-email-laurent@vivier.eu>
Laurent Vivier [Fri, 13 Jan 2017 18:36:31 +0000 (19:36 +0100)]
target-m68k: manage pre-dec et post-inc in CAS
In these cases we must update the address register after
the operation.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
1484332593-16782-4-git-send-email-laurent@vivier.eu>
Laurent Vivier [Fri, 13 Jan 2017 18:36:30 +0000 (19:36 +0100)]
target-m68k: fix gen_flush_flags()
gen_flush_flags() is setting unconditionally cc_op_synced to 1
and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set
to something else by a previous tcg fragment.
We fix that by not setting cc_op_synced to 1
(except for gen_helper_flush_flags() that updates env->cc_op)
FIX: https://github.com/vivier/qemu-m68k/issues/19
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
1484332593-16782-3-git-send-email-laurent@vivier.eu>
Laurent Vivier [Fri, 13 Jan 2017 18:36:29 +0000 (19:36 +0100)]
target-m68k: fix bit operation with immediate value
M680x0 bit operations with an immediate value use 9 bits of the 16bit
value, while coldfire ones use only 8 bits.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
1484332593-16782-2-git-send-email-laurent@vivier.eu>
Thomas Huth [Fri, 6 Jan 2017 07:39:56 +0000 (08:39 +0100)]
m68k: Remove PCI and USB from config file
None of the ColdFire boards that we currently support has a PCI or
USB bus (and AFAIK the upcoming q800 machine does not support PCI
and USB either), so we do not need these settings the config file.
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <
20170106083956.
53d08923@thl530>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Richard Henderson [Tue, 15 Nov 2016 20:44:29 +0000 (21:44 +0100)]
target-m68k: Implement bfffo
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
1479242669-25852-1-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Richard Henderson [Wed, 9 Nov 2016 13:46:11 +0000 (14:46 +0100)]
target-m68k: Implement bitfield ops for memory
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
1478699171-10637-6-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Richard Henderson [Wed, 9 Nov 2016 13:46:10 +0000 (14:46 +0100)]
target-m68k: Implement bitfield ops for registers
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
1478699171-10637-5-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Richard Henderson [Wed, 7 Dec 2016 18:07:27 +0000 (10:07 -0800)]
tcg/aarch64: Fix tcg_out_movi
There were some patterns, like 0x0000_ffff_ffff_00ff, for which we
would select to begin a multi-insn sequence with MOVN, but would
fail to set the 0x0000 lane back from 0xffff.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20161207180727.6286-3-rth@twiddle.net>
Richard Henderson [Wed, 7 Dec 2016 18:07:26 +0000 (10:07 -0800)]
tcg/aarch64: Fix addsub2 for 0+C
When al == xzr, we cannot use addi/subi because that encodes xsp.
Force a zero into the temp register for that (rare) case.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20161207180727.6286-2-rth@twiddle.net>
Richard Henderson [Fri, 13 Jan 2017 17:48:20 +0000 (09:48 -0800)]
target/arm: Fix ubfx et al for aarch64
The patch in
59a71b4c5b4e suffered from a merge failure
when compared to the original patch in
http://lists.nongnu.org/archive/html/qemu-devel/2016-12/msg00137.html
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 13 Jan 2017 17:30:40 +0000 (09:30 -0800)]
tcg/s390: Fix merge error with facilities
The variable was renamed s390_facilities.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Peter Maydell [Fri, 13 Jan 2017 14:38:21 +0000 (14:38 +0000)]
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging
x86 and machine queue, 2017-01-17
Includes i386, CPU, NUMA, and memory backends changes.
i386:
target/i386: Fix bad patch application to translate.c
CPU:
qmp: Report QOM type name on query-cpu-definitions
NUMA:
numa: make -numa parser dynamically allocate CPUs masks
Memory backends:
qom: remove unused header
monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends
# gpg: Signature made Thu 12 Jan 2017 17:53:11 GMT
# gpg: using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/x86-and-machine-pull-request:
qmp: Report QOM type name on query-cpu-definitions
numa: make -numa parser dynamically allocate CPUs masks
target/i386: Fix bad patch application to translate.c
monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends
monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
qom: remove unused header
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 13 Jan 2017 14:02:30 +0000 (14:02 +0000)]
Merge remote-tracking branch 'remotes/stsquad/tags/pull-travis-
20170112-1' into staging
A couple of fixes to reduce the matrix some more that just missed the
last iteration.
# gpg: Signature made Thu 12 Jan 2017 13:01:49 GMT
# gpg: using RSA key 0xFBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>"
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* remotes/stsquad/tags/pull-travis-
20170112-1:
travis: add Trusty with clang stable build
travis: trim out most clang builds
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gerd Hoffmann [Fri, 13 Jan 2017 08:14:45 +0000 (09:14 +0100)]
sdl2: fix build failure on windows
Cc: Stefan Weil <sw@weilnetz.de>
Cc: Samuel Thibault <samuel.thibault@gnu.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Message-id:
1484295285-8809-1-git-send-email-kraxel@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 12 Jan 2017 18:29:49 +0000 (18:29 +0000)]
Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2' into staging
TriCore FPU patches
# gpg: Signature made Wed 11 Jan 2017 13:40:11 GMT
# gpg: using RSA key 0x0AD2C6396B69CA14
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>"
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14
* remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2:
target-tricore: Add updfl instruction
target-tricore: Added new JNE instruction variant
target-tricore: Added new MOV instruction variant
target-tricore: Added MADD.F and MSUB.F instructions
target-tricore: Added FTOUZ instruction
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 12 Jan 2017 17:51:41 +0000 (17:51 +0000)]
Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-
20170111-1' into staging
vga: fixes for virtio-gpu and cirrus.
# gpg: Signature made Wed 11 Jan 2017 10:24:24 GMT
# gpg: using RSA key 0x4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/pull-vga-
20170111-1:
virtio-gpu: tag as not hotpluggable
virtio-gpu: Fix memory leak in virtio_gpu_load()
virtio-gpu: Recalculate VirtIOGPU::hostmem on VM load
display: cirrus: ignore source pitch value as needed in blit_is_unsafe
virtio-gpu: fix information leak in capset get dispatch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eduardo Habkost [Wed, 16 Nov 2016 18:21:39 +0000 (16:21 -0200)]
qmp: Report QOM type name on query-cpu-definitions
The new typename attribute on query-cpu-definitions will be used
to help management software use device-list-properties to check
which properties can be set using -cpu or -global for the CPU
model.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <
1479320499-29818-1-git-send-email-ehabkost@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Igor Mammedov [Fri, 18 Nov 2016 11:02:54 +0000 (12:02 +0100)]
numa: make -numa parser dynamically allocate CPUs masks
so it won't impose an additional limits on max_cpus limits
supported by different targets.
It removes global MAX_CPUMASK_BITS constant and need to
bump it up whenever max_cpus is being increased for
a target above MAX_CPUMASK_BITS value.
Use runtime max_cpus value instead to allocate sufficiently
sized node_cpu bitmasks in numa parser.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
1479466974-249781-1-git-send-email-imammedo@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
[ehabkost: Added asserts to ensure cpu_index < max_cpus]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Doug Evans [Sat, 24 Dec 2016 20:29:33 +0000 (20:29 +0000)]
target/i386: Fix bad patch application to translate.c
In commit
c52ab08aee6f7d4717fc6b517174043126bd302f,
the patch snippet for the "syscall" insn got applied to "iret".
Signed-off-by: Doug Evans <dje@google.com>
Message-Id: <
f403045cde4049058c05446d5c04@google.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Igor Mammedov [Tue, 10 Jan 2017 12:53:15 +0000 (13:53 +0100)]
monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends
Considering 'id' is mandatory for user_creatable objects/backends
and user_creatable_add_type() always has it as an argument
regardless of where from it is called CLI/monitor or QMP,
Fix issue by adding 'id' property to hostmem backends and
set it in user_creatable_add_type() for every object that
implements 'id' property. Then later at query-memdev time
get 'id' from object directly.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
1484052795-158195-4-git-send-email-imammedo@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Igor Mammedov [Tue, 10 Jan 2017 12:53:14 +0000 (13:53 +0100)]
monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
Simplify code by dropping ~57LOC by merging user_creatable_add()
into user_creatable_add_opts() and using the later from monitor.
Along with it allocate opts_visitor_new() once in user_creatable_add_opts().
As result we have one less API func and a more readable/simple
user_creatable_add_opts() vs user_creatable_add().
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
1484052795-158195-3-git-send-email-imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Peter Maydell [Thu, 12 Jan 2017 15:57:18 +0000 (15:57 +0000)]
Merge remote-tracking branch 'remotes/kraxel/tags/pull-audio-
20170111-1' into staging
audio: qomify drivers, hotplug fixes.
# gpg: Signature made Wed 11 Jan 2017 09:32:09 GMT
# gpg: using RSA key 0x4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/pull-audio-
20170111-1:
es1370: wire up reset via DeviceClass
audio: ac97: add exit function
audio: es1370: add exit function
hw/audio: QOM'ify pl041.c
hw/audio: QOM'ify marvell_88w8618.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Igor Mammedov [Tue, 10 Jan 2017 12:53:13 +0000 (13:53 +0100)]
qom: remove unused header
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
1484052795-158195-2-git-send-email-imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Peter Maydell [Thu, 12 Jan 2017 13:21:32 +0000 (13:21 +0000)]
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-
20170110' into staging
TCG opcodes for extract, clz, ctz, ctpop
# gpg: Signature made Wed 11 Jan 2017 02:12:41 GMT
# gpg: using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B
* remotes/rth/tags/pull-tcg-
20170110: (65 commits)
tcg/i386: Handle ctpop opcode
tcg/ppc: Handle ctpop opcode
tcg: Use ctpop to generate ctz if needed
tests: New test-bitcnt
qemu/host-utils.h: Reduce the operation count in the fallback ctpop
target-i386: Use ctpop helper
target-tilegx: Use ctpop helper
target-sparc: Use ctpop helper
target-s390x: Avoid a loop for popcnt
target-ppc: Use ctpop helper
target-alpha: Use ctpop helper
tcg: Add opcode for ctpop
target-xtensa: Use clrsb helper
target-tricore: Use clrsb helper
target-arm: Use clrsb helper
tcg: Add helpers for clrsb
tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR
tcg/i386: Handle ctz and clz opcodes
tcg/i386: Allow bmi2 shiftx to have non-matching operands
tcg/i386: Hoist common arguments in tcg_out_op
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Greg Kurz [Wed, 11 Jan 2017 08:49:32 +0000 (09:49 +0100)]
libqtest: handle zero length memwrite/memread
Some recently added tests pass a zero length to qtest_memwrite().
Unfortunately, the qtest protocol doesn't implement an on-the-wire
syntax for zero-length writes and the current code happily sends
garbage to QEMU. This causes intermittent failures.
It isn't worth the pain to enhance the protocol, so this patch
simply fixes the issue by "just return, doing nothing". The same
fix is applied to qtest_memread() since the issue also exists in
the QEMU part of the "memread" command.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id:
148412457273.22750.
983275587432075569.stgit@bahia
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée [Mon, 7 Nov 2016 14:41:09 +0000 (14:41 +0000)]
travis: add Trusty with clang stable build
Although we've reduced the matrix to avoid repeating clang builds we can
still add an additional clang build to use the latest stable version of
clang which will typically be available on current distros.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Daniel P. Berrange [Thu, 27 Oct 2016 13:23:45 +0000 (15:23 +0200)]
travis: trim out most clang builds
We test with both gcc and clang in order to detect cases
where clang issues warnings that gcc misses. To achieve
this though we don't need to build QEMU in multiple
different configurations. Just a single clang-on-linux
build will be sufficient, if we have an "all enabled"
config.
This cuts the number of build jobs from 21 to 16,
reducing the load imposed on shared Travis CI infra.
This will make it practical to enable jobs for other
interesting & useful configurations without DOS'ing
Travis to much.
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Bastian Koppelmann [Thu, 6 Oct 2016 15:52:04 +0000 (17:52 +0200)]
target-tricore: Add updfl instruction
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Peer Adelt [Tue, 7 Jun 2016 15:49:15 +0000 (17:49 +0200)]
target-tricore: Added new JNE instruction variant
If D[15] is != sign_ext(const4) then PC will be set to (PC +
zero_ext(disp4 + 16)).
[BK: fixed style errors]
Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
Message-Id: <
1465314555-11501-5-git-send-email-peer.adelt@c-lab.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Peer Adelt [Tue, 7 Jun 2016 15:49:14 +0000 (17:49 +0200)]
target-tricore: Added new MOV instruction variant
Puts the content of data register D[a] into E[c][63:32] and the
content of data register D[b] into E[c][31:0].
[BK: fix style error]
[BK: Allocate temporaries only when needed]
Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
Message-Id: <
1465314555-11501-4-git-send-email-peer.adelt@c-lab.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Bastian Koppelmann [Thu, 6 Oct 2016 14:50:53 +0000 (16:50 +0200)]
target-tricore: Added MADD.F and MSUB.F instructions
Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d].
The result is put in D[c]. All operands are floating-point numbers.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Bastian Koppelmann [Thu, 6 Oct 2016 14:46:36 +0000 (16:46 +0200)]
target-tricore: Added FTOUZ instruction
Converts a 32-bit floating point number to an unsigned int. The
result is rounded towards zero.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Gerd Hoffmann [Mon, 9 Jan 2017 13:55:38 +0000 (14:55 +0100)]
virtio-gpu: tag as not hotpluggable
qemu can't hotplug display devices.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id:
1483970138-20360-1-git-send-email-kraxel@redhat.com
Peter Maydell [Mon, 9 Jan 2017 13:38:43 +0000 (13:38 +0000)]
virtio-gpu: Fix memory leak in virtio_gpu_load()
Coverity points out that if we fail in the "creating resources"
loop in virtio_gpu_load() we will leak various resources (CID
1356431).
Failing a VM load is going to leave the simulation in a complete mess,
but we can tidy up to the point that a full system reset should
get us back to sanity.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1483969123-14839-3-git-send-email-peter.maydell@linaro.org
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Peter Maydell [Mon, 9 Jan 2017 13:38:42 +0000 (13:38 +0000)]
virtio-gpu: Recalculate VirtIOGPU::hostmem on VM load
The 'hostmem' field in VirtIOGPU is used to track the total memory
used in pixmaps so that we can impose a maximum limit on it.
However this field is neither migrated nor recalculated on
VM load, which means that after a migration it will be incorrectly
too low, which can allow the guest to use more pixmap memory
than it should. The per-resource hostmem fields are not filled
in either as we reallocate them in the load function.
Recalculate the memory used for each pixmap and the total memory
used as we reallocate the pixmaps in virtio_gpu_load().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1483969123-14839-2-git-send-email-peter.maydell@linaro.org
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Bruce Rogers [Mon, 9 Jan 2017 20:35:20 +0000 (13:35 -0700)]
display: cirrus: ignore source pitch value as needed in blit_is_unsafe
Commit
4299b90 added a check which is too broad, given that the source
pitch value is not required to be initialized for solid fill operations.
This patch refines the blit_is_unsafe() check to ignore source pitch in
that case. After applying the above commit as a security patch, we
noticed the SLES 11 SP4 guest gui failed to initialize properly.
Signed-off-by: Bruce Rogers <brogers@suse.com>
Message-id:
20170109203520.5619-1-brogers@suse.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Li Qiang [Tue, 1 Nov 2016 12:37:57 +0000 (05:37 -0700)]
virtio-gpu: fix information leak in capset get dispatch
In virgl_cmd_get_capset function, it uses g_malloc to allocate
a response struct to the guest. As the 'resp'struct hasn't been full
initialized it will lead the 'resp->padding' field to the guest.
Use g_malloc0 to avoid this.
Signed-off-by: Li Qiang <liqiang6-s@360.cn>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id:
58188cae.
4a6ec20a.3d2d1.aff2@mx.google.com
[ kraxel: resolved conflict ]
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Gerd Hoffmann [Tue, 10 Jan 2017 13:18:01 +0000 (14:18 +0100)]
es1370: wire up reset via DeviceClass
Instead of using qemu_register_reset().
That way we get proper cleanup for free.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
1484054281-26139-1-git-send-email-kraxel@redhat.com
Li Qiang [Thu, 15 Dec 2016 02:30:21 +0000 (18:30 -0800)]
audio: ac97: add exit function
Currently the ac97 device emulation doesn't have a exit function,
hot unplug this device will leak some memory. Add a exit function to
avoid this.
Signed-off-by: Li Qiang <liqiang6-s@360.cn>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id:
58520052.
4825ed0a.27a71.6cae@mx.google.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Li Qiang [Thu, 15 Dec 2016 02:32:22 +0000 (18:32 -0800)]
audio: es1370: add exit function
Currently the es1370 device emulation doesn't have a exit function,
hot unplug this device will leak some memory. Add a exit function to
avoid this.
Signed-off-by: Li Qiang <liqiang6-s@360.cn>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id:
585200c9.
a968ca0a.1ab80.4c98@mx.google.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
xiaoqiang zhao [Sat, 31 Dec 2016 01:17:20 +0000 (09:17 +0800)]
hw/audio: QOM'ify pl041.c
split the old SysBus init function into an instance_init
and Device realize function
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Message-id:
20161231011720.3965-3-zxq_yx_007@163.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
xiaoqiang zhao [Sat, 31 Dec 2016 01:17:19 +0000 (09:17 +0800)]
hw/audio: QOM'ify marvell_88w8618.c
split the old SysBus init function into an instance_init
and Device realize function
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Message-id:
20161231011720.3965-2-zxq_yx_007@163.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Richard Henderson [Tue, 22 Nov 2016 13:15:04 +0000 (14:15 +0100)]
tcg/i386: Handle ctpop opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Tue, 22 Nov 2016 11:43:12 +0000 (11:43 +0000)]
tcg/ppc: Handle ctpop opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Tue, 22 Nov 2016 12:40:35 +0000 (12:40 +0000)]
tcg: Use ctpop to generate ctz if needed
Particularly when andc is also available, this is two insns
shorter than using clz to compute ctz.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Alex Bennée [Fri, 9 Dec 2016 14:36:00 +0000 (14:36 +0000)]
tests: New test-bitcnt
Add some unit tests for bit count functions (currently only ctpop). As
the routines are based on the Hackers Delight optimisations I based
the test patterns on their tests.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 21 Nov 2016 11:30:34 +0000 (12:30 +0100)]
qemu/host-utils.h: Reduce the operation count in the fallback ctpop
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 21 Nov 2016 11:18:53 +0000 (12:18 +0100)]
target-i386: Use ctpop helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 21 Nov 2016 11:10:28 +0000 (12:10 +0100)]
target-tilegx: Use ctpop helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 21 Nov 2016 11:08:27 +0000 (12:08 +0100)]
target-sparc: Use ctpop helper
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 21 Nov 2016 11:06:26 +0000 (12:06 +0100)]
target-s390x: Avoid a loop for popcnt
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 21 Nov 2016 10:58:25 +0000 (11:58 +0100)]
target-ppc: Use ctpop helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 21 Nov 2016 10:48:24 +0000 (11:48 +0100)]
target-alpha: Use ctpop helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 21 Nov 2016 10:13:39 +0000 (11:13 +0100)]
tcg: Add opcode for ctpop
The number of actual invocations of ctpop itself does not warrent
an opcode, but it is very helpful for POWER7 to use in generating
an expansion for ctz.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 16:38:10 +0000 (17:38 +0100)]
target-xtensa: Use clrsb helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 16:36:51 +0000 (17:36 +0100)]
target-tricore: Use clrsb helper
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 16:35:35 +0000 (17:35 +0100)]
target-arm: Use clrsb helper
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 16:32:48 +0000 (17:32 +0100)]
tcg: Add helpers for clrsb
The number of actual invocations does not warrent an opcode,
and the backends generating it. But at least we can eliminate
redundant helpers.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 18 Nov 2016 16:02:59 +0000 (17:02 +0100)]
tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR
The ISA manual documents the output is undefined if the input was zero.
However, we document in target-i386 that the behavior of real silicon
is to preserve the contents of the output register. We also mention
that there are real applications that depend on this. That this is
baked into silicon is mentioned as a potential cause for some false
sharing behaviour wrt lzcnt/tzcnt.
Taking advantage of this allows us to save 2 insns in the normal case,
and 4 insns for i686 emulating a 64-bit clz.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 11:22:54 +0000 (12:22 +0100)]
tcg/i386: Handle ctz and clz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 18 Nov 2016 13:18:41 +0000 (14:18 +0100)]
tcg/i386: Allow bmi2 shiftx to have non-matching operands
Previously we could not have different constraints for different ISA levels,
which prevented us from eliding the matching constraint for shifts.
We do now have to make sure that the operands match for constant shifts.
We can also handle some small left shifts via lea.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 18 Nov 2016 11:50:50 +0000 (12:50 +0100)]
tcg/i386: Hoist common arguments in tcg_out_op
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 18 Nov 2016 10:55:41 +0000 (11:55 +0100)]
tcg/i386: Fuly convert tcg_target_op_def
Use a switch instead of searching a table. Share constraints between
32-bit and 64-bit, when at all possible.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 15:10:37 +0000 (16:10 +0100)]
tcg/s390: Handle clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 14:34:03 +0000 (15:34 +0100)]
tcg/mips: Handle clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 13:59:40 +0000 (14:59 +0100)]
tcg/arm: Handle ctz and clz opcodes
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 13:03:28 +0000 (14:03 +0100)]
tcg/aarch64: Handle ctz and clz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 11:48:55 +0000 (12:48 +0100)]
tcg/ppc: Handle ctz and clz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 11:21:13 +0000 (12:21 +0100)]
target-i386: Use clz and ctz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 10:49:06 +0000 (11:49 +0100)]
target-arm: Use clz opcode
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 10:48:37 +0000 (11:48 +0100)]
target-xtensa: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 10:40:39 +0000 (11:40 +0100)]
target-unicore32: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 10:37:15 +0000 (11:37 +0100)]
target-tricore: Use clz opcode
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 10:33:48 +0000 (11:33 +0100)]
target-tilegx: Use clz and ctz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 10:30:34 +0000 (11:30 +0100)]
target-s390x: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 10:27:03 +0000 (11:27 +0100)]
target-ppc: Use clz and ctz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 10:17:45 +0000 (11:17 +0100)]
target-openrisc: Use clz and ctz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 10:11:54 +0000 (11:11 +0100)]
target-mips: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 09:58:52 +0000 (10:58 +0100)]
target-microblaze: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 09:54:57 +0000 (10:54 +0100)]
target-cris: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 09:23:30 +0000 (10:23 +0100)]
target-alpha: Use the ctz and clz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Tue, 22 Nov 2016 12:38:46 +0000 (12:38 +0000)]
disas/ppc: Handle popcnt and cnttz
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 11:22:15 +0000 (12:22 +0100)]
disas/i386.c: Handle tzcnt
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Wed, 16 Nov 2016 08:23:28 +0000 (09:23 +0100)]
tcg: Add clz and ctz opcodes
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 18 Nov 2016 16:41:24 +0000 (17:41 +0100)]
tcg: Allow an operand to be matching or a constant
This allows an output operand to match an input operand
only when the input operand needs a register.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 18 Nov 2016 10:50:59 +0000 (11:50 +0100)]
tcg: Pass the opcode width to target_parse_constraint
This will let us choose how to interpret a given constraint
depending on whether the opcode is 32- or 64-bit. Which will
let us share more constraint combinations between opcodes.
At the same time, change the interface to return the advanced
pointer instead of passing it in/out by reference.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 18 Nov 2016 08:31:40 +0000 (09:31 +0100)]
tcg: Transition flat op_defs array to a target callback
This will allow the target to tailor the constraints to the
auto-detected ISA extensions.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 18 Nov 2016 07:35:03 +0000 (08:35 +0100)]
tcg: Add markup for output requires new register
This is the same concept as, and same markup as, the
early clobber markup in gcc.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 24 Oct 2016 03:44:32 +0000 (20:44 -0700)]
tcg/optimize: Fold movcond 0/1 into setcond
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 17 Oct 2016 21:50:31 +0000 (14:50 -0700)]
target-s390x: Use the new deposit and extract ops
Use the new primitives for RISBG.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Sat, 15 Oct 2016 18:37:19 +0000 (13:37 -0500)]
target-ppc: Use the new deposit and extract ops
Use the new primitives for RDWINM and RLDICL.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Sat, 15 Oct 2016 17:04:13 +0000 (12:04 -0500)]
target-mips: Use the new extract op
Use extract for EXT and DEXT.
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Sat, 15 Oct 2016 16:54:17 +0000 (11:54 -0500)]
target-i386: Use new deposit and extract ops
A couple of places where it was easy to identify a right-shift
followed by an extract or and-with-immediate, and the obvious
sign-extract from a high byte register.
Acked-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Sat, 15 Oct 2016 16:41:29 +0000 (11:41 -0500)]
target-arm: Use new deposit and extract ops
Use the new primitives for UBFX and SBFX.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 14 Oct 2016 22:35:42 +0000 (17:35 -0500)]
target-alpha: Use deposit and extract ops
Signed-off-by: Richard Henderson <rth@twiddle.net>