OSDN Git Service
Benjamin Kramer [Wed, 27 Dec 2017 13:31:50 +0000 (13:31 +0000)]
[X86] Fix vmul combine for AVX1 targets.
v8i32 is legal von AVX1, but it doesn't have pmuludq for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321490
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 27 Dec 2017 12:00:18 +0000 (12:00 +0000)]
[InstCombine] Gracefully handle out of range extractelement indices
InstSimplify is responsible for handling these, but we shouldn't just assert here.
Reduced from oss-fuzz #4808 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321489
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 27 Dec 2017 11:36:18 +0000 (11:36 +0000)]
[DAGCombine] foldBinOpIntoSelect can fail to constant fold in some cases.
For example, float operations may fail to constant fold under certain circumstances (inf/nan/denormal creation etc.)
Reduced from oss-fuzz #4802 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321488
91177308-0d34-0410-b5e6-
96231b3b80d8
Rui Ueyama [Wed, 27 Dec 2017 08:59:52 +0000 (08:59 +0000)]
Improve performance TokenizeWindowsCommandLine
Patcy by Takuto Ikuta.
This patch reduces lld link time of chromium's blink_core.dll in
component build.
Total size of input argument in .directives become nearly 300MB in the
build and calling many strchr and assert becomes bottleneck.
On my desktop machine, 4 times stats of the link time are like below.
Improved around 10%.
This patch
TotalSeconds : 13.
4918885
TotalSeconds : 13.
9474257
TotalSeconds : 13.
4941082
TotalSeconds : 13.
6077962
Avg : 13.
63530465
master
TotalSeconds : 15.
6938531
TotalSeconds : 15.
7022508
TotalSeconds : 15.
9567202
TotalSeconds : 14.
5851505
Avg : 15.
48449365
Differential Revision: https://reviews.llvm.org/D41590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321479
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikael Holmen [Wed, 27 Dec 2017 08:48:33 +0000 (08:48 +0000)]
[Lint] Don't warn about noalias argument aliasing if other argument is byval
Summary:
When using byval, the data is effectively copied as part of the call
anyway, so we aren't actually passing the pointer and thus there is no
reason to issue a warning.
Reviewers: rnk
Reviewed By: rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40118
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321478
91177308-0d34-0410-b5e6-
96231b3b80d8
Gadi Haber [Wed, 27 Dec 2017 08:35:57 +0000 (08:35 +0000)]
[X86][RD]: Adding full coverage of MC encoding for RD isa sets.<NFC>
NFC.
Adding MC regressions tests to cover RDPMC, RDRAND, RDRAND, RDSEED, RDTSCP, DWRFSGS isa sets.
This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenk
Differential Revision: https://reviews.llvm.org/D41328
Change-Id: Ie97b397546e6b1ed180c6abd7b41fccb136d2b82
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321476
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Wed, 27 Dec 2017 08:26:22 +0000 (08:26 +0000)]
[SCEV] Be careful with nuw/nsw/exact in InsertBinop
InsertBinop tries to find an appropriate instruction instead of
creating a new instruction. When it checks whether instruction is
the same as we need to create it ignores nuw/nsw/exact flags.
It leads to invalid behavior when poison instruction can be used
when it was not expected. Specifically, for example Expander
expands the SCEV built for instruction
%a = add i32 %v, 1
It is possible that InsertBinop can find an instruction
% b = add nuw nsw i32 %v, 1
and will use it instead of version w/o nuw nsw.
It is incorrect.
The patch conservatively ignores all instructions with any of
poison flags installed.
Reviewers: sanjoy, mkazantsev, sebpop, jbhateja
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321475
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Wed, 27 Dec 2017 07:15:23 +0000 (07:15 +0000)]
[SCEV] Do not insert if it is already in cache
This is fix for the crash caused by ScalarEvolution::getTruncateExpr.
It expects that if it checked the condition that SCEV is not in UniqueSCEVs cache in
the beginning that it will not be there inside this method.
However during recursion and transformation/simplification for sub expression,
it is possible that these modifications will end up with the same SCEV as we started from.
So we must always check whether SCEV is in cache and do not insert item if it is already there.
Reviewers: sanjoy, mkazantsev, craig.topper
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321472
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Wed, 27 Dec 2017 01:30:12 +0000 (01:30 +0000)]
[instcombine] add powi(x, 2) -> x * x
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321468
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Wed, 27 Dec 2017 01:14:30 +0000 (01:14 +0000)]
Sink a couple of transforms from instcombine into instsimplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321467
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Wed, 27 Dec 2017 00:16:12 +0000 (00:16 +0000)]
[NFC] Extract out a helper function for SimplifyCall(CS, Q)
This simplifies code, but the real motivation is that it lets me clean up some downstream code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321466
91177308-0d34-0410-b5e6-
96231b3b80d8
Zhaoshi Zheng [Tue, 26 Dec 2017 23:31:21 +0000 (23:31 +0000)]
[Unroll][DebugInfo] Propagate loop body's debug location to epilog preheader
NewExit and epilog PreHeader should has the same debug loc as the original loop
body, instead of original loop exit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321465
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 26 Dec 2017 23:27:44 +0000 (23:27 +0000)]
[DAGCombine] visitANDLike - ensure APInt is is in range for getSExtValue/getZExtValue
Reduced from oss-fuzz #4782 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321464
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 26 Dec 2017 22:22:58 +0000 (22:22 +0000)]
[X86] Return SDValue(N, 0) instead of an SDValue() after a successful combine.
Returning SDValue() means nothing changed, SDValue(N,0) means there was a change but the worklist management was taken care of.
I don't know if this has a real effect other than making sure the combine counter in the DAG combiner gets updated, but it is the correct thing to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321463
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 26 Dec 2017 22:22:57 +0000 (22:22 +0000)]
[X86] Regenerate test using update_llc_test_checks.py.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321462
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 26 Dec 2017 22:12:20 +0000 (22:12 +0000)]
[InstCombine] fix miscompile of frem with 0.0 operand (PR34870)
We might want to select NAN here or do this transform with fast-math,
but this should at least fix the miscompile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321461
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 26 Dec 2017 22:06:57 +0000 (22:06 +0000)]
[InstCombine] add test for frem with 0.0 (PR34870); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321460
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew V. Tischenko [Tue, 26 Dec 2017 18:29:52 +0000 (18:29 +0000)]
It's a fix for Bug 35741 - can't use comments after x86 prefixes.
Differential Revision: https://reviews.llvm.org/D41579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321459
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 26 Dec 2017 15:09:19 +0000 (15:09 +0000)]
[ValueTracking] ignore FP signed-zero when detecting a casted-to-integer fmin/fmax pattern
This is a preliminary step for the patch discussed in D41136 (and denoted here with the FIXME comment).
When we match an FP min/max that is cast to integer, any intermediate difference between +0.0 or -0.0
should be muted in the result by the conversion (either fptosi or fptoui) of the result. Thus, we can
enable 'nsz' for the purpose of matching fmin/fmax.
Note that there's probably room to generalize this more, possibly by fixing the current calls to the
weak version of isKnownNonZero() in matchSelectPattern() to the more powerful recursive version.
Differential Revision: https://reviews.llvm.org/D41333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321456
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 26 Dec 2017 14:48:28 +0000 (14:48 +0000)]
[DAGCombine] Don't combine (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2) for i1
Reduced from oss-fuzz #4773 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321455
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 26 Dec 2017 11:42:39 +0000 (11:42 +0000)]
[InstSimplify] Check for in range extraction index before calling APInt::getZExtValue()
Reduced from oss-fuzz #4768 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321454
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 26 Dec 2017 05:43:05 +0000 (05:43 +0000)]
[X86] Pass itins.rr/itins.rm through properly for some instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321452
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 26 Dec 2017 05:43:04 +0000 (05:43 +0000)]
[X86] Use SSE_INTMUL_ITINS_P for the AVX-512 MUL instructions to match their SSE/AVX counterparts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321451
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 26 Dec 2017 05:43:02 +0000 (05:43 +0000)]
[X86] Fix typo in assert message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321450
91177308-0d34-0410-b5e6-
96231b3b80d8
Martell Malone [Mon, 25 Dec 2017 20:11:02 +0000 (20:11 +0000)]
COFF: fix IMAGE_FILE_MACHINE_AM33
PE COFF spec value is 0x1D3 not 0x13
https://msdn.microsoft.com/en-us/library/windows/desktop/ms680547(v=vs.85).aspx
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321447
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Mon, 25 Dec 2017 14:16:07 +0000 (14:16 +0000)]
[docs] Use dbgs() instead of errs() for DEBUG()
The examples in llvm/Support/Debug.h use `DEBUG(dbgs() << ...)` instead
of `errs()`, so the examples in the Programmer's Manual should match
that.
Patch by: Moritz Sichert <moritz.sichert@googlemail.com>
Differential revision: https://reviews.llvm.org/D41170
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321444
91177308-0d34-0410-b5e6-
96231b3b80d8
Eugene Leviant [Mon, 25 Dec 2017 13:57:24 +0000 (13:57 +0000)]
[ThinLTO] Don't import functions with noinline attribute
Differential revision: https://reviews.llvm.org/D41489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321443
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Mon, 25 Dec 2017 09:41:00 +0000 (09:41 +0000)]
[MC] - Disallow invalid section groups declarations.
This fixes parseGroup() so that it always sets error condition on error.
Previously it was not done, because parseIdentifier looks never do that,
assuming that caller should do it if he wants to.
So previously cases from test were silently accepted and produced broken output.
Differential revision: https://reviews.llvm.org/D41559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321439
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Kazantsev [Mon, 25 Dec 2017 09:35:10 +0000 (09:35 +0000)]
[SafepointIRVerifier] Allow non-dereferencing uses of unrelocated or poisoned PHI nodes
PHI that has at least one unrelocated input cannot cause any issues by itself,
though its uses should be carefully verified. With this patch PHIs are allowed
to have any inputs but when all inputs are unrelocated the PHI is marked as
unrelocated and if not all inputs are unrelocated then the PHI is marked as
poisoned. Poisoned pointers can be used only in three ways: to derive new
pointers, in PHIs or in comparisons against constants that are exclusively
derived from null.
Patch by Daniil Suchkov!
Differential Revision: https://reviews.llvm.org/D41006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321438
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 25 Dec 2017 06:47:10 +0000 (06:47 +0000)]
[X86] Add a DAG combines to turn vXi64 muls into VPMULDQ/VPMULUDQ if the upper bits are all sign bits or zeros.
Normally we catch this during lowering, but vXi64 mul is considered legal when we have AVX512DQ.
This DAG combine allows us to avoid PMULLQ with AVX512DQ if we can prove its unnecessary. PMULLQ is 3 uops that take 4 cycles each. While pmuldq/pmuludq is only one 4 cycle uop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321437
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 25 Dec 2017 06:47:08 +0000 (06:47 +0000)]
[X86] Add avx512vl and avx512dq command lines to combine-pmuldq.ll to demonstrate where we fail to use pmuldq/pmuludq and use to pmullq instead.
It's nice that pmullq exists, but it has higher latency and probably lower throughput than pmuldq/pmuludq. We should prefer those if we can.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321436
91177308-0d34-0410-b5e6-
96231b3b80d8
Don Hinton [Mon, 25 Dec 2017 01:23:09 +0000 (01:23 +0000)]
[cmake] Always respect existing CMAKE_REQUIRED_FLAGS when adding additional ones.
Summary:
Always respect existing CMAKE_REQUIRED_FLAGS when adding
additional ones. This is important when cross compiling where
--sysroot and -target were already added.
In particular, this is needed when cross compiling from Darwin to
Linux, since --sysroot is required to find headers and libraries.
Cmake has a similar bug in check_include_file[_cxx] where
CMAKE_REQUIRED_LIBRARIES isn't passed, which causes
try_compile to fail.
(please see https://gitlab.kitware.com/cmake/cmake/merge_requests/1620)
Reviewers: compnerd, silvas, beanz, brad.king
Reviewed By: compnerd
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D41568
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321434
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 25 Dec 2017 00:54:53 +0000 (00:54 +0000)]
[X86] Make some helper methods static functions instead. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321433
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 25 Dec 2017 00:54:51 +0000 (00:54 +0000)]
[X86] Use SelectionDAG::getFPExtendOrRound to simplify some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321432
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 24 Dec 2017 12:51:54 +0000 (12:51 +0000)]
[X86][AVX] Add AVX1/AVX2 vmul tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321426
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Sun, 24 Dec 2017 12:46:22 +0000 (12:46 +0000)]
Make helpers static. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321425
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 24 Dec 2017 12:20:21 +0000 (12:20 +0000)]
[X86][X87] Mark pseudo memory fold instructions as load/sideeffects (PR21160, PR34080, PR34454).
Match regular x87 memory fold instructions with load/sideeffects tags, to prevent the schedulers from re-ordering them across the fnstcw/fldcw sequences for truncating stores while they are still pseudo during the stack conversion pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321424
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 24 Dec 2017 10:25:01 +0000 (10:25 +0000)]
[X86][X87] Renamed CHECK prefix, its not actually broken anymore just scheduled differently
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321423
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 24 Dec 2017 10:22:55 +0000 (10:22 +0000)]
[X86][X87] Add another test case mentioned on PR34080
Did my best to reduce this, but the X87 scheduling bug is hard to hit at the best of times...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321422
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 24 Dec 2017 06:51:36 +0000 (06:51 +0000)]
[X86] Fix (v2f64 (s/uint_to_fp (v2i1))) to avoid scalarization without AVX512DQ.
Previously we extended v2i1 to v2f64 and then tried to use cvtuqq2pd/cvtqq2pd, but that only works with avx512dq. So we ended up scalarizing it. Now we widen to v4i1 first and extend to v4i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321420
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Sun, 24 Dec 2017 06:13:36 +0000 (06:13 +0000)]
[MC] - Teach llvm-mc to handle comdats whose names are numbers.
Currently llvm-mc ignores COMDATs whose names are numbers,
for example following code:
.section .foo,"G",@progbits,123,comdat
would produce no COMDATs at all.
Patch fixes the issue.
Differential revision: https://reviews.llvm.org/D41552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321419
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 24 Dec 2017 02:05:18 +0000 (02:05 +0000)]
[DAGCombiners] Don't turn ANDs to shuffles with zero so early. Give some other combines a chance to run.
This moves the combine for turning ANDs into shuffle with zero out of SimplifyVBinOps and places it only in visitAND below the reassociate handling. This fixes the specific case I noticed where we failed to combine two ands with constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321417
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 24 Dec 2017 02:05:17 +0000 (02:05 +0000)]
[X86] Add assembler predicates to BITALG/VBMI2/VNNI features to be consistent with the other AVX512 ISAs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321416
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 24 Dec 2017 01:03:31 +0000 (01:03 +0000)]
[X86] Teach WidenMaskArithmetic to handle any constant buildvector on the RHS not just all zeros/ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321415
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 23 Dec 2017 20:21:29 +0000 (20:21 +0000)]
[SelectionDAG] Teach SelectionDAG::getNode to constant fold zext/aext/sext of constant build vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321414
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Sat, 23 Dec 2017 20:02:26 +0000 (20:02 +0000)]
[CallSiteSplitting] Remove isOrHeader restriction.
By following the single predecessors of the predecessors of the call
site, we do not need to restrict the control flow.
Reviewed By: junbuml, davide
Differential Revision: https://reviews.llvm.org/D40729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321413
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 23 Dec 2017 18:53:05 +0000 (18:53 +0000)]
[X86] Remove type restrictions from WidenMaskArithmetic.
This can help AVX-512 code where mask types are legal allowing us to remove extends and truncates to/from mask types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321408
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 23 Dec 2017 18:53:03 +0000 (18:53 +0000)]
[X86] In WidenMaskArithmetic, make sure we check the input type of a truncate on N1.
Later in the code we explicitly bypass the truncate so we should be checking its type to make sure that it's safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321407
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 23 Dec 2017 18:53:01 +0000 (18:53 +0000)]
[X86] Remove unneeded EVT variable. NFC
Immediately after it is created we check if its equal to another EVT. Then we inconsistently use one or the other variables in the code below.
Instead do the equality check directly on the getValueType result and remove the variable. Use the origina VT variable throughout the remaining code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321406
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 23 Dec 2017 17:25:59 +0000 (17:25 +0000)]
[X86][X87] Wrap FpI_ pseudo to use PseudoI. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321405
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Sat, 23 Dec 2017 15:06:30 +0000 (15:06 +0000)]
[SCCP] Manually fold branches on undef.
This code was originally removed and replace with an assertion
because believed unnecessary. It turns out there was simply
no test coverage for this case, and the constant folder doesn't
yet know about patterns like `br undef %label1, %label2`.
Presumably at some point the constant folder might learn about
these patterns, but it's a broader change.
A testcase will be added to make sure this doesn't regress again
in the future.
Fixes PR35723.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321402
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 23 Dec 2017 10:47:21 +0000 (10:47 +0000)]
[X86] Add default InstrItinClass to PseudoI
This will be used to help tidyup existing pseudos that we've added scheduling info to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321401
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 23 Dec 2017 06:52:03 +0000 (06:52 +0000)]
[X86] Pass the right VT to the getZeroExtendInReg introduced in r321398
Apparently we don't have tests for this which I didn't realize before. I'll try to fix that but wanted to fix the obvious bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321399
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 23 Dec 2017 02:54:52 +0000 (02:54 +0000)]
[X86] Use SelectionDAG::getZeroExtendInReg instead of implementing it manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321398
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 23 Dec 2017 02:54:50 +0000 (02:54 +0000)]
[SelectionDAG][X86] Don't use ->getValueType(0) after a call to getOperand to get the type of the operand.
getOperand returns an SDValue that contains the node and the result number. There is no guarantee that the result number if 0. By using the -> operator we are calling SDNode::getValueType rather than SDValue::getValueType. This requires supplying a result number and we shouldn't assume it was 0.
I don't have a test case. Just noticed while cleaning up some other code and saw that it occurred in other places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321397
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Fri, 22 Dec 2017 22:06:56 +0000 (22:06 +0000)]
[DAG] Add missing case check from findbaseoffset merge from r321389.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321391
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Fri, 22 Dec 2017 21:20:55 +0000 (21:20 +0000)]
Integrate findBaseOffset address analyses to BaseIndexOffset. NFCI.
BaseIndexOffset supercedes findBaseOffset analysis save only Constant
Pool addresses. Migrate analysis to BaseIndexOffset.
Relanding after correcting base address matching check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321389
91177308-0d34-0410-b5e6-
96231b3b80d8
Walter Lee [Fri, 22 Dec 2017 21:19:13 +0000 (21:19 +0000)]
[git-llvm] Handle files ignored by svn correctly
Summary: Correctly handle files ignored by svn (such as .o files,
which are ignored by default) by adding "--no-ignore" flag to "svn
status" and "svn add".
Differential Revision: https://reviews.llvm.org/D41404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321388
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Fri, 22 Dec 2017 21:18:50 +0000 (21:18 +0000)]
Unbreak the build. Combining chrono with Optional is annoying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321387
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Fri, 22 Dec 2017 20:31:39 +0000 (20:31 +0000)]
[WebAssembly] MC: Fix for address taken aliases
Previously, taking the address for an alias would result in:
"Symbol not found in table index space"
Increase test coverage for weak aliases.
This code should be more efficient too as it avoids building
the `IsAddressTaken` set.
Differential Revision: https://reviews.llvm.org/D41510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321384
91177308-0d34-0410-b5e6-
96231b3b80d8
Alina Sbirlea [Fri, 22 Dec 2017 19:54:03 +0000 (19:54 +0000)]
[MemorySSA] Allow reordering of loads that alias in the presence of volatile loads.
Summary:
Make MemorySSA allow reordering of two loads that may alias, when one is volatile.
This makes MemorySSA less conservative and behaving the same as the AliasSetTracker.
For more context, see D16875.
LLVM language reference: "The optimizers must not change the number of volatile operations or change their order of execution relative to other volatile operations. The optimizers may change the order of volatile operations relative to non-volatile operations. This is not Java’s “volatile” and has no cross-thread synchronization behavior."
Reviewers: george.burgess.iv, dberlin
Subscribers: sanjoy, reames, hfinkel, llvm-commits, Prazek
Differential Revision: https://reviews.llvm.org/D41525
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321382
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Fri, 22 Dec 2017 19:33:56 +0000 (19:33 +0000)]
Revert "[DAG] Integrate findBaseOffset address analyses to BaseIndexOffset. NFCI."
which was causing miscompilations in for some test-suite components.
This reverts commit
3e9de9ff0f3162920a2a3cba51c7dc14b54b4d16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321380
91177308-0d34-0410-b5e6-
96231b3b80d8
Guozhi Wei [Fri, 22 Dec 2017 18:54:04 +0000 (18:54 +0000)]
[SimplifyCFG] Don't do if-conversion if there is a long dependence chain
If after if-conversion, most of the instructions in this new BB construct a long and slow dependence chain, it may be slower than cmp/branch, even if the branch has a high miss rate, because the control dependence is transformed into data dependence, and control dependence can be speculated, and thus, the second part can execute in parallel with the first part on modern OOO processor.
This patch checks for the long dependence chain, and give up if-conversion if find one.
Differential Revision: https://reviews.llvm.org/D39352
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321377
91177308-0d34-0410-b5e6-
96231b3b80d8
Ben Dunbobbin [Fri, 22 Dec 2017 18:32:15 +0000 (18:32 +0000)]
[ThinLTO][CachePruning] explicitly disable pruning
In https://reviews.llvm.org/rL321077 and https://reviews.llvm.org/D41231 I fixed a regression in the c-api which prevented the pruning from being *effectively* disabled.
However this approach, helpfully recommended by @labath, is cleaner.
It is also nice to remove the weasel words about effectively disabling from the api comments.
Differential Revision: https://reviews.llvm.org/D41497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321376
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjoy Das [Fri, 22 Dec 2017 18:21:59 +0000 (18:21 +0000)]
(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
Re-land r321234. It had to be reverted because it broke the shared
library build. The shared library build broke because there was a
missing LLVMBuild dependency from lib/Passes (which calls
TargetMachine::getTargetIRAnalysis) to lib/Target. As far as I can
tell, this problem was always there but was somehow masked
before (perhaps because TargetMachine::getTargetIRAnalysis was a
virtual function).
Original commit message:
This makes the TargetMachine interface a bit simpler. We still need
the std::function in TargetIRAnalysis to avoid having to add a
dependency from Analysis to Target.
See discussion:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html
I avoided adding all of the backend owners to this review since the
change is simple, but let me know if you feel differently about this.
Reviewers: echristo, MatzeB, hfinkel
Reviewed By: hfinkel
Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D41464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321375
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Preobrazhensky [Fri, 22 Dec 2017 18:03:35 +0000 (18:03 +0000)]
[AMDGPU][MC] Corrected handling of negative expressions
See bug 35716: https://bugs.llvm.org/show_bug.cgi?id=35716
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D41488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321372
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 22 Dec 2017 17:18:13 +0000 (17:18 +0000)]
[SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left.
This seems to improve X86's ability to match this into an address computation. Otherwise the other operand gets assigned to the base register and the stack pointer + frame index ends up in the index register. But index registers can't encode ESP/RSP so we end up having to move it into another register to meet the constraint.
I could try to improve the address matcher in X86, but swapping the producer seemed easier. Several other places already have the operands in this order so this is at least consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321370
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 22 Dec 2017 17:18:11 +0000 (17:18 +0000)]
[X86] When lowering insert_vector_elt/extract_vector_elt of vXi1 with a non-constant index just use either a 128-bit type or the vXi8 type with the correct number of elements.
Despite what the comment said there isn't better codegen for 512-bit vectors. The 128/256/512 bit implementation jus stores to memory and loads an element. There's no advantage to doing that with a larger size. In fact in many cases it causes a stack realignment and generates worse code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321369
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 22 Dec 2017 17:18:10 +0000 (17:18 +0000)]
[X86] Improve the printing of address mode during isel matching.
Fix some inconsistent new line behavior and only print the FrameIndex when the address mode is a FrameIndexBase addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321368
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Preobrazhensky [Fri, 22 Dec 2017 17:13:28 +0000 (17:13 +0000)]
[AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32
See bug 35645: https://bugs.llvm.org/show_bug.cgi?id=35645
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D41186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321367
91177308-0d34-0410-b5e6-
96231b3b80d8
Haicheng Wu [Fri, 22 Dec 2017 17:09:09 +0000 (17:09 +0000)]
[InlineCost] Find more free binary operations
Currently, inline cost model considers a binary operator as free only if both
its operands are constants. Some simple cases are missing such as a + 0, a - a,
etc. This patch modifies visitBinaryOperator() to call SimplifyBinOp() without
going through simplifyInstruction() to get rid of the constant restriction.
Thus, visitAnd() and visitOr() are not needed.
Differential Revision: https://reviews.llvm.org/D41494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321366
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Fri, 22 Dec 2017 16:59:09 +0000 (16:59 +0000)]
[DAG] Integrate findBaseOffset address analyses to BaseIndexOffset. NFCI.
BaseIndexOffset supercedes findBaseOffset analysis save only Constant
Pool addresses. Migrate analysis to BaseIndexOffset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321364
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Preobrazhensky [Fri, 22 Dec 2017 15:18:06 +0000 (15:18 +0000)]
[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers
See bug 35561: https://bugs.llvm.org/show_bug.cgi?id=35561
This patch also affects implementation of SGPR and VGPR registers though changes are cosmetic.
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D41437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321359
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Fri, 22 Dec 2017 13:45:46 +0000 (13:45 +0000)]
[mips] Add test case to check that calls to mcount follow long calls / short calls options. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321357
91177308-0d34-0410-b5e6-
96231b3b80d8
Diana Picus [Fri, 22 Dec 2017 13:05:51 +0000 (13:05 +0000)]
[ARM GlobalISel] Support G_INTTOPTR and G_PTRTOINT for s32
Mark conversions between pointers and 32-bit scalars as legal, map them
to the GPR and select to a simple COPY.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321356
91177308-0d34-0410-b5e6-
96231b3b80d8
Diana Picus [Fri, 22 Dec 2017 11:09:18 +0000 (11:09 +0000)]
[ARM GlobalISel] Support pointer constants
Pointer constants are pretty rare, since we usually represent them as
integer constants and then cast to pointer. One notable exception is the
null pointer constant, which is represented directly as a G_CONSTANT 0
with pointer type. Mark it as legal and make sure it is selected like
any other integer constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321354
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Fri, 22 Dec 2017 08:36:25 +0000 (08:36 +0000)]
[DAGCombine] Revert r321259
Improve ReduceLoadWidth for SRL Patch is causing an issue on the
PPC64 BE santizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321349
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 22 Dec 2017 06:41:23 +0000 (06:41 +0000)]
Rewrite the cached map used for locating the most precise DIE among
inlined subroutines for a given address.
This is essentially the hot path of llvm-symbolizer when extracting
inlined frames during symbolization. Previously, we would read every
subprogram and every inlined subroutine, building a std::map across the
entire PC space to the best DIE, and then do only a handful of queries
as we symbolized a backtrace. A huge fraction of the time was spent
building the map itself.
This patch changes it two a two-level system. First, we just build a map
from PC-interval to DWARF subprograms. These are required to be disjoint
and so constructing this is pretty easy. Second, we build a map *just*
for the inlined subroutines within the subprogram containing the query
address. This allows us to look at far fewer DIEs and build a *much*
smaller set of cached maps in the llvm-symbolizer case where only a few
address get symbolized during the entire run.
It also builds both interval maps in a very different way. It constructs
a single flat vector of pairs that maps from offset -> index. The
indices point into collections of DIE objects, but can also be
"tombstones" (-1) to mark gaps. In the case of subprograms, this mostly
just simplifies the data structure a bit. For inlined subroutines,
because we carefully split them as we build the map, we end up in many
cases having no holes and not having to store both start and stop
offsets.
Finally, the PC ranges for the inlined subroutines are compressed into
32-bits by making them relative to the base PC of the outer subprogram.
This means that if you have a single function body with over 2gb of
executable code in it, we will stop mapping address past the first 2gb
of that function into inlined subroutines and just give you the
subprogram. This doesn't seem like a problem. ;]
All of this combines to make llvm-symbolizer *well* over 2x faster for
symbolizing backtraces out of LLVM's unittests. Death-test heavy unit
tests are running >2x faster. I'm still going to look at completely
disabling symbolization there, but figured while I had a good benchmark
we should make symbolization a bit better.
Sadly, the logic to build the flat interval map for the inlined
subroutines is fairly complex. I'm not super happy about this and
welcome any simplifying suggestions.
Huge thanks to Dave Blaikie who helped walk me through what the various
things I needed to do in DWARF to make this work.
Differential Revision: https://reviews.llvm.org/D40987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321345
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 22 Dec 2017 03:53:14 +0000 (03:53 +0000)]
[X86] Add missing initialization for the HasPREFETCHWT1 subtarget variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321340
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 22 Dec 2017 02:41:12 +0000 (02:41 +0000)]
[X86] Enable PRFCHW feature on KNL/KNM and all CPUs inherited from Broadwell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321336
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 22 Dec 2017 02:30:30 +0000 (02:30 +0000)]
[X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling for prefetch instructions.
Previously prefetch was only considered legal if sse was enabled, but it should be supported with 3dnow as well.
The prfchw flag now imply at least some form of prefetch without the write hint is available, either the sse or 3dnow version. This is true even if 3dnow and sse are explicitly disabled.
Similarly prefetchwt1 feature implies availability of prefetchw and the the prefetcht0/1/2/nta instructions. This way we can support _MM_HINT_ET0 using prefetchw and _MM_HINT_ET1 with prefetchwt1. And its assumed that if we have levels for the write hint we would have levels for the non-write hint, thus why we enable the sse prefetch instructions.
I believe this behavior is consistent with gcc. I've updated the prefetch.ll to test all of these combinations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321335
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 22 Dec 2017 02:30:26 +0000 (02:30 +0000)]
[X86] Use SIGN_EXTEND to implement ANY_EXTEND from vXi1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321334
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Fri, 22 Dec 2017 02:10:40 +0000 (02:10 +0000)]
inline-fp.ll was moved in r321332; delete it properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321333
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Fri, 22 Dec 2017 02:08:08 +0000 (02:08 +0000)]
[Inliner] Restrict soft-float inlining penalty.
The penalty is currently getting applied in a bunch of places where it
doesn't make sense, like bitcasts (which are free) and calls (which
were getting the call penalty applied twice). Instead, just apply the
penalty to binary operators and floating-point casts.
While I'm here, also fix getFPOpCost() to do the right thing in more
cases, so we don't have to dig into function attributes.
Differential Revision: https://reviews.llvm.org/D41522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321332
91177308-0d34-0410-b5e6-
96231b3b80d8
Easwaran Raman [Fri, 22 Dec 2017 01:33:52 +0000 (01:33 +0000)]
Add hasProfileData() to check if a function has profile data. NFC.
Summary:
This replaces calls to getEntryCount().hasValue() with hasProfileData
that does the same thing. This refactoring is useful to do before adding
synthetic function entry counts but also a useful cleanup IMO even
otherwise. I have used hasProfileData instead of hasRealProfileData as
David had earlier suggested since I think profile implies "real" and I
use the phrase "synthetic entry count" and not "synthetic profile count"
but I am fine calling it hasRealProfileData if you prefer.
Reviewers: davidxl, silvas
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41461
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321331
91177308-0d34-0410-b5e6-
96231b3b80d8
Wolfgang Pieb [Fri, 22 Dec 2017 01:12:24 +0000 (01:12 +0000)]
[DWARF] Fix formatting bug with r321295. This fixes a MIPS buildbot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321330
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 21 Dec 2017 22:08:23 +0000 (22:08 +0000)]
[X86] Use SIGN_EXTEND rather than ZERO_EXTEND for lowering extract_vector_elt from vXi1 with a non-const index.
We have a better range of instructions we can use if we can fill with the value i1 value rather than zeroing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321315
91177308-0d34-0410-b5e6-
96231b3b80d8
Alina Sbirlea [Thu, 21 Dec 2017 21:41:53 +0000 (21:41 +0000)]
[ModRefInfo] Add must alias info to ModRefInfo.
Summary:
Add an additional bit to ModRefInfo, ModRefInfo::Must, to be cleared for known must aliases.
Shift existing Mod/Ref/ModRef values to include an additional most
significant bit. Update wrappers that modify ModRefInfo values to
reflect the change.
Notes:
* ModRefInfo::Must is almost entirely cleared in the AAResults methods, the remaining changes are trying to preserve it.
* Only some small changes to make custom AA passes set ModRefInfo::Must (BasicAA).
* GlobalsModRef already declares a bit, who's meaning overlaps with the most significant bit in ModRefInfo (MayReadAnyGlobal). No changes to shift the value of MayReadAnyGlobal (see AlignedMap). FunctionInfo.getModRef() ajusts most significant bit so correctness is preserved, but the Must info is lost.
* There are cases where the ModRefInfo::Must is not set, e.g. 2 calls that only read will return ModRefInfo::NoModRef, though they may read from exactly the same location.
Reviewers: dberlin, hfinkel, george.burgess.iv
Subscribers: llvm-commits, sanjoy
Differential Revision: https://reviews.llvm.org/D38862
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321309
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 21 Dec 2017 20:45:13 +0000 (20:45 +0000)]
[X86] When lowering truncates to vXi1, don't sign extend i16/i8 types to 512-bit if we have VLX.
This should only affect what we do for v8i16. Previously we went to v8i64, but if we have VLX we only need v8i32. This prevents an unnecessary zmm usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321303
91177308-0d34-0410-b5e6-
96231b3b80d8
Wolfgang Pieb [Thu, 21 Dec 2017 19:38:13 +0000 (19:38 +0000)]
[DWARF v5] Rework of string offsets table reader
Reorganizes the DWARF consumer to derive the string offsets table
contribution's format from the contribution header instead of
(incorrectly) from the unit's format.
Reviewers: JDevliegehere, aprantl
Differential Revision: https://reviews.llvm.org/D41146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321295
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 21 Dec 2017 18:44:06 +0000 (18:44 +0000)]
[X86] Promote v8i1 shuffles to v8i32 instead of v8i64 if we have VLX.
We should have equally good shuffle options for v8i32 with VLX. This was spotted during my attempts to remove 512-bit vectors from SKX.
We still use 512-bits for v16i1, v32i1, and v64i1. I'm less sure we can handle those well with narrower vectors. i32 and i64 element sizes get the best shuffle support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321291
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 21 Dec 2017 18:12:31 +0000 (18:12 +0000)]
[X86][SSE] Split large PAVGB/PAVGW vectors to legal widths
Patch to allow detectAVGPattern handle vectors larger than the legal size (128 SSE2, 256 AVX2, 512 AVX512BW), splitting the vectors accordingly.
Differential Revision: https://reviews.llvm.org/D41440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321288
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Thu, 21 Dec 2017 17:14:13 +0000 (17:14 +0000)]
[YAML] Refactor escaping unittests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321284
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Thu, 21 Dec 2017 17:14:09 +0000 (17:14 +0000)]
[YAML] Fix UTF-8 handling
Previous YAML quoting patches broke UTF-8 printing in YAML: see https://reviews.llvm.org/D41290#961801.
Differential Revision: https://reviews.llvm.org/D41490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321283
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Thu, 21 Dec 2017 17:12:43 +0000 (17:12 +0000)]
[TableGen] Print more helpful information in case of type contradiction
Dump the failing TreePattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321282
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 21 Dec 2017 16:54:03 +0000 (16:54 +0000)]
[DAGCombiner] Remove (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) fold. NFCI.
More general cases are already handled by constant canonicalization and then the ReassociateOps call at line 5327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321280
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 21 Dec 2017 16:34:46 +0000 (16:34 +0000)]
[DAGCombiner] Generalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) combine to work on non-splat vectors
The knownbits_mask_or_shuffle_uitofp change is interesting - shuffle combines manage to kick in, removing the AND constant mask load. For targets with fast-variable-shuffle this should reduce further to VPOR+VPSHUFB+VCVTDQ2PS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321279
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 21 Dec 2017 16:08:41 +0000 (16:08 +0000)]
[X86] Add (or (and X, c1), c2) -> (and (or X, c2), c1|c2) non-splat vector test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321278
91177308-0d34-0410-b5e6-
96231b3b80d8
Tony Jiang [Thu, 21 Dec 2017 15:42:50 +0000 (15:42 +0000)]
[PowerPC] Fix parest build failure in SPEC2017.
The build failure was caused by an assertion in pre-legalization DAGCombine:
Combining: t6: ppcf128 = uint_to_fp t5
... into: t20: f32 = PPCISD::FCFIDUS t19
which is clearly wrong since ppcf128 are definitely different type with f32 and
we cannot change the node value type when do DAGCombine. The fix is don't
handle ppc_fp128 or i1 conversions in PPCTargetLowering::combineFPToIntToFP and
leave it to downstream to legalize it and expand it to small legal types.
Differential Revision: https://reviews.llvm.org/D41411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321276
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 21 Dec 2017 15:17:29 +0000 (15:17 +0000)]
[DAGCombiner] Generalize (and (or x, C), D) -> D iff (C & D) == D combine to work on non-splat vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321275
91177308-0d34-0410-b5e6-
96231b3b80d8