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Nick Lewycky [Mon, 1 Apr 2019 20:03:16 +0000 (20:03 +0000)]
Not all blocks are reachable from entry. Don't assume they are.
Fixes a bug in isPotentiallyReachable, noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357425
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Craig Topper [Mon, 1 Apr 2019 19:08:15 +0000 (19:08 +0000)]
[X86] Classify the AVX512 rounding control operand as X86::OPERAND_ROUNDING_CONTROL instead of MCOI::OPERAND_IMMEDIATE. Add an assert on legal values of rounding control in the encoder and remove an explicit mask.
This should allow llvm-exegesis to intelligently constrain the rounding mode.
The mask in the encoder shouldn't be necessary any more. We used to allow codegen to use 8-11 for rounding mode and the assembler would use 0-3 to mean the same thing so we masked here and in the printer. Codegen now matches the assembler and the printer was updated, but I forgot to update the encoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357419
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Yi Kong [Mon, 1 Apr 2019 18:12:43 +0000 (18:12 +0000)]
[llvm-objcopy] Add --keep-symbols option
Differential Revision: https://reviews.llvm.org/D60054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357418
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Simon Pilgrim [Mon, 1 Apr 2019 17:48:03 +0000 (17:48 +0000)]
[SLP] getVectorElementSize and isTreeTinyAndNotFullyVectorizable are const methods. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357416
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Simon Pilgrim [Mon, 1 Apr 2019 17:32:46 +0000 (17:32 +0000)]
[SLP] getGatherCost and isFullyVectorizableTinyTree are const methods. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357414
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Caroline Tice [Mon, 1 Apr 2019 16:29:40 +0000 (16:29 +0000)]
Commit accidentally omitted test case.
This test case was approved as part of
https://reviews.llvm.org/D49434, but was accidentally
omitted from the final commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357409
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Philip Reames [Mon, 1 Apr 2019 16:26:08 +0000 (16:26 +0000)]
[LoopPred] Be uniform about proving generated conditions
We'd been optimizing the case where the predicate was obviously true, do the same for the false case. Mostly just for completeness sake, but also may improve compile time in loops which will exit through the guard. Such loops are presumed rare in fastpath code, but may be present down untaken paths, so optimizing for them is still useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357408
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Bixia Zheng [Mon, 1 Apr 2019 16:10:26 +0000 (16:10 +0000)]
[NVPTX] Fix the codegen for llvm.round.
Summary:
Previously, we translate llvm.round to PTX cvt.rni, which rounds to the
even interger when the source is equidistant between two integers. This
is not correct as llvm.round should round away from zero. This change
replaces llvm.round with a round away from zero implementation through
target specific custom lowering.
Modify a few affected tests to not check for cvt.rni. Instead, we check
for the use of a few constants used in implementing round. We are also
adding CUDA runnable tests to check for the values produced by
llvm.round to test-suites/External/CUDA.
Reviewers: tra
Subscribers: jholewinski, sanjoy, jlebar, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357407
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Philip Reames [Mon, 1 Apr 2019 16:05:15 +0000 (16:05 +0000)]
[LoopPred] Delete the old condition expressions if unused
LoopPredication was replacing the original condition, but leaving the instructions to compute the old conditions around. This would get cleaned up by other passes of course, but we might as well do it eagerly. That also makes the test output less confusing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357406
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Philip Reames [Mon, 1 Apr 2019 15:35:30 +0000 (15:35 +0000)]
[Tests] Autogen all the LoopPredication tests
I'm about to make some changes to the pass which cause widespread - but uninteresting - test diffs. Prepare the tests for easy updating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357404
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Philip Reames [Mon, 1 Apr 2019 15:32:07 +0000 (15:32 +0000)]
[Tests] Add tests for a possible loop predication transform variant
As highlighted by tests, if one of the operands is loop variant, but guaranteed to have the same value on all iterations, we have a missed oppurtunity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357403
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Neil Henning [Mon, 1 Apr 2019 15:19:52 +0000 (15:19 +0000)]
[AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.
This change incorporates an effort by Connor Abbot to change how we deal
with WWM operations potentially trashing valid values in inactive lanes.
Previously, the SIFixWWMLiveness pass would work out which registers
were being trashed within WWM regions, and ensure that the register
allocator did not have any values it was depending on resident in those
registers if the WWM section would trash them. This worked perfectly
well, but would cause sometimes severe register pressure when the WWM
section resided before divergent control flow (or at least that is where
I mostly observed it).
This fix instead runs through the WWM sections and pre allocates some
registers for WWM. It then reserves these registers so that the register
allocator cannot use them. This results in a significant register
saving on some WWM shaders I'm working with (130 -> 104 VGPRs, with just
this change!).
Differential Revision: https://reviews.llvm.org/D59295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357400
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Nico Weber [Mon, 1 Apr 2019 14:59:50 +0000 (14:59 +0000)]
gn build: Merge r357383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357398
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David Spickett [Mon, 1 Apr 2019 14:56:37 +0000 (14:56 +0000)]
[AArch64] Add v8.5-a Memory Tagging STZGM instruction
This instruction writes a block of allocation tags
and stores zero to the associated data locations.
It differs from STGM by 1 bit and has the same
arguments.
The specification can be found here:
https://developer.arm.com/docs/ddi0596/c
Differential Revision: https://reviews.llvm.org/D60065
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357397
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Alex Bradbury [Mon, 1 Apr 2019 14:53:17 +0000 (14:53 +0000)]
[RISCV] Attach VK_RISCV_CALL to symbols upon creation
This patch replaces the addition of VK_RISCV_CALL in RISCVMCCodeEmitter by
creating the RISCVMCExpr when tail/call are parsed, or in the codegen case
when the callee symbols are created.
This required adding a new CallSymbol operand to allow only adding
VK_RISCV_CALL to tail/call instructions.
This patch will allow further expansion of parsing and codegen to easily
include PLT symbols which must generate the R_RISCV_CALL_PLT relocation.
Differential Revision: https://reviews.llvm.org/D55560
Patch by Lewis Revill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357396
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David Spickett [Mon, 1 Apr 2019 14:52:18 +0000 (14:52 +0000)]
[AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions
The STGV/LDGV instructions were replaced with
STGM/LDGM. The encodings remain the same but there
is no longer writeback so there are no unpredictable
encodings to check for.
The specfication can be found here:
https://developer.arm.com/docs/ddi0596/c
Differential Revision: https://reviews.llvm.org/D60064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357395
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Alex Bradbury [Mon, 1 Apr 2019 14:42:56 +0000 (14:42 +0000)]
[RISCV] Generate address sequences suitable for mcmodel=medium
This patch adds an implementation of a PC-relative addressing sequence to be
used when -mcmodel=medium is specified. With absolute addressing, a 'medium'
codemodel may cause addresses to be out of range. This is because while
'medium' implies a 2 GiB addressing range, this 2 GiB can be at any offset as
opposed to 'small', which implies the first 2 GiB only.
Note that LLVM/Clang currently specifies code models differently to GCC, where
small and medium imply the same functionality as GCC's medlow and medany
respectively.
Differential Revision: https://reviews.llvm.org/D54143
Patch by Lewis Revill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357393
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David Spickett [Mon, 1 Apr 2019 14:41:14 +0000 (14:41 +0000)]
[AArch64] Add v8.5-a Memory Tagging GMID_EL1 register
The latest version of the MTE spec added a system
register 'GMID_EL1'. It contains the block size used
by the LDGM and STGM instructions and is read only.
The specification can be found here:
https://developer.arm.com/docs/ddi0596/c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357392
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Mikael Holmen [Mon, 1 Apr 2019 14:10:10 +0000 (14:10 +0000)]
[InstCombine] Handle vector gep with scalar argument in evaluateInDifferentElementOrder
Summary:
This fixes PR41270.
The recursive function evaluateInDifferentElementOrder expects to be called
on a vector Value, so when we call it on a vector GEP's arguments, we must
first check that the argument is indeed a vector.
Reviewers: reames, spatel
Reviewed By: spatel
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60058
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357389
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Matt Arsenault [Mon, 1 Apr 2019 14:08:26 +0000 (14:08 +0000)]
X86: Fix override warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357388
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Mikael Holmen [Mon, 1 Apr 2019 14:06:45 +0000 (14:06 +0000)]
Revert "[InstCombine] Handle vector gep with scalar argument in evaluateInDifferentElementOrder"
This reverts commit
75216a6dbcfe5fb55039ef06a07e419fa875f4a5.
I'll recommit with a better commit message with reference to the
phabricator review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357387
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Matt Arsenault [Mon, 1 Apr 2019 14:03:44 +0000 (14:03 +0000)]
InstSimplify: Add baseline test for upcoming change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357386
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Mikael Holmen [Mon, 1 Apr 2019 13:48:56 +0000 (13:48 +0000)]
[InstCombine] Handle vector gep with scalar argument in evaluateInDifferentElementOrder
This fixes PR41270.
The recursive function evaluateInDifferentElementOrder expects to be called
on a vector Value, so when we call it on a vector GEP's arguments, we must
first check that the argument is indeed a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357385
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Clement Courbet [Mon, 1 Apr 2019 13:48:50 +0000 (13:48 +0000)]
[X86] Make post-ra scheduling macrofusion-aware.
Subscribers: MatzeB, arsenm, jvesely, nhaehnle, hiraditya, javed.absar, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357384
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Sanjay Patel [Mon, 1 Apr 2019 13:36:40 +0000 (13:36 +0000)]
[InstCombine] eliminate commuted select-shuffles + binop (PR41304)
If we have a commutable vector binop with inverted select-shuffles,
we don't care about the order of the operands in each vector lane:
LHS = shuffle V1, V2, <0, 5, 6, 3>
RHS = shuffle V2, V1, <0, 5, 6, 3>
LHS + RHS --> <V1[0]+V2[0], V2[1]+V1[1], V2[2]+V1[2], V1[3]+V2[3]> --> V1 + V2
PR41304:
https://bugs.llvm.org/show_bug.cgi?id=41304
...is currently titled as an SLP enhancement, but at least for the
given example, we can reduce that in instcombine because we are just
eliminating shuffles.
As noted in the TODO, this could be generalized, but I haven't thought
through those patterns completely, so this is limited to what appears
to be always safe.
Differential Revision: https://reviews.llvm.org/D60048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357382
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Clement Courbet [Mon, 1 Apr 2019 13:18:34 +0000 (13:18 +0000)]
[X86MacroFusion][NFC] Add more tests.
In preparation for D59688.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357381
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Krasimir Georgiev [Mon, 1 Apr 2019 11:42:54 +0000 (11:42 +0000)]
[X86] Fix a test from r357317
Summary:
The missing `<` causes the lld command to override the test file, which fails in
environments marking the test files as readonly.
Reviewers: bkramer
Reviewed By: bkramer
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357380
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Simon Pilgrim [Mon, 1 Apr 2019 10:54:04 +0000 (10:54 +0000)]
[X86][SSE] Add fcmp constant folding tests
Initial test coverage for D60006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357379
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Luis Marques [Mon, 1 Apr 2019 09:54:14 +0000 (09:54 +0000)]
[RISCV] Add seto pattern expansion
Adds a `seto` pattern expansion. Without it the lowerings of `fcmp one` and
`fcmp ord` would be inefficient due to an unoptimized double negation.
Differential Revision: https://reviews.llvm.org/D59699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357378
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Craig Topper [Mon, 1 Apr 2019 05:26:12 +0000 (05:26 +0000)]
[X86] Use ISD::INTRINSIC_VOID in getTgtMemIntrinsic for truncating stores and scatter intrinsics.
This is the appropriate opcode for only having a chain output. Though I'm not
sure it matters much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357375
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Alex Bradbury [Mon, 1 Apr 2019 02:38:27 +0000 (02:38 +0000)]
[RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation)
A pcrel_lo will point to the associated pcrel_hi fixup which in turn points to
the real target. RISCVMCExpr::evaluatePCRelLo will work around this
indirection in order to allow the fixup to be evaluate properly. However, if
relocations are forced (e.g. due to linker relaxation is enabled) then its
evaluation is undesired and will result in a relocation with the wrong target.
This patch modifies evaluatePCRelLo so it will not try to evaluate if the
fixup will be forced as a relocation. A new helper method is added to
RISCVAsmBackend to query this.
Differential Revision: https://reviews.llvm.org/D59686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357374
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Nico Weber [Sun, 31 Mar 2019 16:49:54 +0000 (16:49 +0000)]
gn build: Add build files for most clang-tools-extra unit tests
Differential Revision: https://reviews.llvm.org/D60038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357369
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Sanjay Patel [Sun, 31 Mar 2019 15:45:47 +0000 (15:45 +0000)]
[InstCombine] add tests for inverted select-shuffles + binop (PR41304); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357368
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Sanjay Patel [Sun, 31 Mar 2019 15:11:34 +0000 (15:11 +0000)]
[x86] allow movmsk with 2-element reductions
One motivation for making this change is that the lack of using movmsk is likely
a main source of perf difference between clang and gcc on the C-Ray benchmark as
shown here:
https://www.phoronix.com/scan.php?page=article&item=gcc-clang-2019&num=5
...but this change alone isn't enough to solve that problem.
The 'all-of' examples show what is likely the worst case trade-off: we end up with
an extra instruction (or 2 if we count the 'xor' register clearing). The 'any-of'
examples look clearly better using movmsk because we've traded 2 vector instructions
for 2 scalar instructions, and movmsk may have better timing than the generic 'movq'.
If we examine the llvm-mca output for these cases, it appears that even though the
'all-of' movmsk variant looks worse on paper, it would perform better on both
Haswell and Jaguar.
$ llvm-mca -mcpu=haswell no_movmsk.s -timeline
Iterations: 100
Instructions: 400
Total Cycles: 504
Total uOps: 400
Dispatch Width: 4
uOps Per Cycle: 0.79
IPC: 0.79
Block RThroughput: 1.0
$ llvm-mca -mcpu=haswell movmsk.s -timeline
Iterations: 100
Instructions: 600
Total Cycles: 358
Total uOps: 600
Dispatch Width: 4
uOps Per Cycle: 1.68
IPC: 1.68
Block RThroughput: 1.5
$ llvm-mca -mcpu=btver2 no_movmsk.s -timeline
Iterations: 100
Instructions: 400
Total Cycles: 407
Total uOps: 400
Dispatch Width: 2
uOps Per Cycle: 0.98
IPC: 0.98
Block RThroughput: 2.0
$ llvm-mca -mcpu=btver2 movmsk.s -timeline
Iterations: 100
Instructions: 600
Total Cycles: 311
Total uOps: 600
Dispatch Width: 2
uOps Per Cycle: 1.93
IPC: 1.93
Block RThroughput: 3.0
Finally, there may be CPUs where movmsk is horribly slow (old AMD small cores?), but if
that's true, then we're also almost certainly making the wrong transform already for
reductions with >2 elements, so that should be fixed independently.
Differential Revision: https://reviews.llvm.org/D59997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357367
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Sanjay Patel [Sun, 31 Mar 2019 15:01:30 +0000 (15:01 +0000)]
[InstCombine] canonicalize select shuffles by commuting
In PR41304:
https://bugs.llvm.org/show_bug.cgi?id=41304
...we have a case where we want to fold a binop of select-shuffle (blended) values.
Rather than try to match commuted variants of the pattern, we can canonicalize the
shuffles and check for mask equality with commuted operands.
We don't produce arbitrary shuffle masks in instcombine, but select-shuffles are a
special case that the backend is required to handle because we already canonicalize
vector select to this shuffle form.
So there should be no codegen difference from this change. It's possible that this
improves CSE in IR though.
Differential Revision: https://reviews.llvm.org/D60016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357366
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Liang Zou [Sun, 31 Mar 2019 14:49:00 +0000 (14:49 +0000)]
fix typo: "\t" => " "
Reviewers: llvm.org, Jim
Reviewed By: Jim
Subscribers: arsenm, jvesely, nhaehnle, rupprecht, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357365
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Fedor Sergeev [Sun, 31 Mar 2019 10:15:39 +0000 (10:15 +0000)]
SafepointIRVerifier port to new Pass Manager
Straightforward port of StatepointIRVerifier pass to new Pass Manager framework.
Fix By: skatkov
Reviewed By: fedor.sergeev
Differential Revision: https://reviews.llvm.org/D59825
This is a re-land of r357147/r357148 with LLVM_ENABLE_MODULES build fixed.
Adding IR/SafepointIRVerifier.h into its own module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357361
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Luqman Aden [Sun, 31 Mar 2019 08:58:50 +0000 (08:58 +0000)]
[NFC][InstCombine] Add tests for combining icmp of no-wrap sub w/ constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357360
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Nico Weber [Sun, 31 Mar 2019 00:03:37 +0000 (00:03 +0000)]
gn build: Merge r357340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357358
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Nico Weber [Sun, 31 Mar 2019 00:01:24 +0000 (00:01 +0000)]
gn build: Merge r357326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357357
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Simon Pilgrim [Sat, 30 Mar 2019 20:24:26 +0000 (20:24 +0000)]
[SystemZ] Remove fcmp undef from reduced test
Pre-commit for D60006 (Add fcmp UNDEF handling to SelectionDAG::FoldSetCC)
Approved by @uweigand (Ulrich Weigand)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357355
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Simon Pilgrim [Sat, 30 Mar 2019 20:16:16 +0000 (20:16 +0000)]
[MIPS] Remove fcmp undef from reduced test
Pre-commit for D60006 (Add fcmp UNDEF handling to SelectionDAG::FoldSetCC)
Approved by @atanasyan (Simon Atanasyan)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357354
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Craig Topper [Sat, 30 Mar 2019 18:59:17 +0000 (18:59 +0000)]
[X86] Teach isel for RMW binops to handle negate
Negate updates flags like a subtract. We should be able to use the flags from the RMW form of negate when we have (store (X86ISD::SUB 0, load A), A)
Differential Revision: https://reviews.llvm.org/D60007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357353
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Alex Bradbury [Sat, 30 Mar 2019 17:59:30 +0000 (17:59 +0000)]
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
This patch adds support for the RISC-V hard float ABIs, building on top of
rL355771, which added basic target-abi parsing and MC layer support. It also
builds on some re-organisations and expansion of the upstream ABI and calling
convention tests which were recently committed directly upstream.
A number of aspects of the RISC-V float hard float ABIs require frontend
support (e.g. flattening of structs and passing int+fp for fp+fp structs in a
pair of registers), and will be addressed in a Clang patch.
As can be seen from the tests, it would be worthwhile extending
RISCVMergeBaseOffsets to handle constant pool as well as global accesses.
Differential Revision: https://reviews.llvm.org/D59357
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357352
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Simon Pilgrim [Sat, 30 Mar 2019 17:12:29 +0000 (17:12 +0000)]
[X86][SSE] detectAVGPattern - Match zext(or(x,y)) 'add like' patterns (PR41316)
Fixes PR41316 where the expanded PAVG intrinsic had had one of its ADDs turned into an OR due to its operands having no conflicting bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357351
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Alex Bradbury [Sat, 30 Mar 2019 15:53:38 +0000 (15:53 +0000)]
[RISCV] Add RV64 CHECK lines to test/CodeGen/RISCV/vararg.ll and prepare for hard float tests
vararg.ll previously missed RV64 tests. This patch also prepares for using
vararg.ll to test handling of varargs for the ilp32f/ilp32d/lp64f/lp64d hard
float ABIs. In these ABIs, varargs are passed as in either the ilp32 or lp64
ABI. Due to some slight codegen differences, different check lines are needed
for when RV32D is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357350
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Simon Pilgrim [Sat, 30 Mar 2019 15:31:53 +0000 (15:31 +0000)]
[X86][SSE] detectAVGPattern - begin generalizing ADD matches
Move the ADD matching into a helper - first NFC stage towards supporting 'ADD like' cases such as in PR41316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357349
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Fangrui Song [Sat, 30 Mar 2019 14:38:51 +0000 (14:38 +0000)]
[cmake] Change deprecated $<CONFIG> to $<CONFIGURATION>. NFC
See rL357338 for a similar change. The informational expression
$<CONFIGURATION> has been deprecated since CMake 3.0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357348
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Fangrui Song [Sat, 30 Mar 2019 14:08:59 +0000 (14:08 +0000)]
[llvm-objcopy] Replace the size() helper with SectionTableRef::size
Summary:
BTW, STLExtras.h provides llvm::size() which is similar to std::size()
for random access iterators. However, if we prefer qualified
llvm::size(), the member function .size() will be more convenient.
Reviewers: jhenderson, jakehehrlich, rupprecht, grimar, alexshap, espindola
Reviewed By: grimar
Subscribers: emaste, arichardson, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357347
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Simon Pilgrim [Sat, 30 Mar 2019 13:53:11 +0000 (13:53 +0000)]
[X86][SSE] Add PAVG test case from PR41316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357346
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Heejin Ahn [Sat, 30 Mar 2019 11:04:48 +0000 (11:04 +0000)]
[WebAssembly] Fix unwind destination mismatches in CFG stackify
Summary:
Linearing the control flow by placing `try`/`end_try` markers can create
mismatches in unwind destinations. This patch resolves these mismatches
by wrapping those instructions with an incorrect unwind destination with
a nested `try`/`catch`/`end_try` and branching to the right destination
within the new catch block.
Reviewers: dschuff
Subscribers: sunfish, sbc100, jgravelle-google, chrib, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D48345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357343
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Heejin Ahn [Sat, 30 Mar 2019 09:29:57 +0000 (09:29 +0000)]
[WebAssembly] Run ExplicitLocals pass after CFGStackify
Summary:
While this does not change any final output, this will greatly simplify
ixing unwind destination mismatches in CFGStackify (D48345), because we
have to create some new registers there.
Reviewers: dschuff
Subscribers: sunfish, sbc100, jgravelle-google, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59652
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357342
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Alex Bradbury [Sat, 30 Mar 2019 09:15:47 +0000 (09:15 +0000)]
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))
The SplitF64 node is used on RV32D to convert an f64 directly to a pair of i32
(necessary as bitcasting to i64 isn't legal). When performed on a ConstantFP,
this will result in a FP load from the constant pool followed by a store to
the stack and two integer loads from the stack (necessary as there is no way
to directly move between f64 FPRs and i32 GPRs on RV32D). It's always cheaper
to just materialise integers for the lo and hi parts of the FP constant, so do
that instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357341
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Anton Afanasyev [Sat, 30 Mar 2019 08:42:48 +0000 (08:42 +0000)]
Adds `-ftime-trace` option to clang that produces Chrome `chrome://tracing` compatible JSON profiling output dumps.
This change adds hierarchical "time trace" profiling blocks that can be visualized in Chrome, in a "flame chart" style. Each profiling block can have a "detail" string that for example indicates the file being processed, template name being instantiated, function being optimized etc.
This is taken from GitHub PR: https://github.com/aras-p/llvm-project-
20170507/pull/2
Patch by Aras Pranckevičius.
Differential Revision: https://reviews.llvm.org/D58675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357340
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Alex Bradbury [Sat, 30 Mar 2019 05:24:42 +0000 (05:24 +0000)]
[RISCV][NFC] Remove floating point operations from test/CodeGen/RISCV/vararg.ll
This minimises differences in output when compiling with hardware floating
point support, which will be done in a future patch (to demonstrate the same
vararg calling convention is used).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357339
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Shoaib Meenai [Sat, 30 Mar 2019 01:35:01 +0000 (01:35 +0000)]
[cmake] Remove use of deprecated generator expression. NFC
Use $<CONFIG> instead of $<CONFIGURATION>, since the latter has been
deprecated since CMake 3.0, and the former is entirely equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357338
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Heejin Ahn [Sat, 30 Mar 2019 01:31:11 +0000 (01:31 +0000)]
[WebAssembly] Optimize the number of routing blocks in FixIrreducibleCFG
Summary:
Currently we create a routing block to the dispatch block for every
predecessor of every entry. So the total number of routing blocks
created will be (# of preds) * (# of entries). But we don't need to do
this: we need at most 2 routing blocks per loop entry, one for when the
predecessor is inside the loop and one for it is outside the loop. (We
can't merge these into one because this will creates another loop cycle
between blocks inside and blocks outside) This patch fixes this and
creates at most 2 routing blocks per entry.
This also renames variable `Split` to `Routing`, which I think is a bit
clearer.
Reviewers: kripken
Subscribers: sunfish, dschuff, sbc100, jgravelle-google, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357337
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Hubert Tong [Fri, 29 Mar 2019 23:32:47 +0000 (23:32 +0000)]
[Support] Implement is_local_impl with AIX mntctl
Summary:
On AIX, we can determine whether a filesystem is remote using `mntctl`.
If the information is not found, then claim that the file is remote
(since that is the more restrictive case). Testing for the associated
interface is restored with a modified version of the unit test from
rL295768.
Reviewers: jasonliu, xingxue
Reviewed By: xingxue
Subscribers: jsji, apaprocki, Hahnfeld, zturner, krytarowski, kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58801
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357333
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Philip Reames [Fri, 29 Mar 2019 23:10:01 +0000 (23:10 +0000)]
[LoopPredication] Remove stale TODO
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357331
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Philip Reames [Fri, 29 Mar 2019 23:06:57 +0000 (23:06 +0000)]
[LoopPredication] Use the builder's insertion point everywhere [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357330
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Alina Sbirlea [Fri, 29 Mar 2019 22:55:59 +0000 (22:55 +0000)]
[MemorySSA] Temporary fix assert when reaching 0 limit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357327
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Sanjoy Das [Fri, 29 Mar 2019 22:27:10 +0000 (22:27 +0000)]
Try to fix buildbot error
Error is:
llvm/lib/Analysis/ScalarEvolution.cpp:3534:10: error: chosen constructor is explicit in copy-initialization
return {UniqueSCEVs.FindNodeOrInsertPos(ID, IP), std::move(ID), IP};
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/bin/../lib/gcc/aarch64-linux-gnu/5.4.0/../../../../include/c++/5.4.0/tuple:479:19: note: explicit constructor declared here
constexpr tuple(_UElements&&... __elements)
^
1 error generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357324
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Thomas Lively [Fri, 29 Mar 2019 22:00:18 +0000 (22:00 +0000)]
[WebAssembly] Add mutable globals feature
Summary:
This feature is not actually used for anything in the WebAssembly
backend, but adding it allows users to get it into the target features
sections of their objects, which makes these objects
future-compatible.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jdoerfert, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D60013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357321
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Sanjoy Das [Fri, 29 Mar 2019 22:00:12 +0000 (22:00 +0000)]
[SCEV] Check the cache in get{S|U}MaxExpr before doing any work
Summary:
This lets us avoid e.g. checking if A >=s B in getSMaxExpr(A, B) if we've
already established that (A smax B) is the best we can do.
Fixes PR41225.
Reviewers: asbirlea
Subscribers: mcrosier, jlebar, bixia, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357320
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Alina Sbirlea [Fri, 29 Mar 2019 21:56:09 +0000 (21:56 +0000)]
[MemorySSA] Limit clobber walks.
Summary: This patch limits all getClobberingMemoryAccess() walks to MaxCheckLimit.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357319
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Jessica Paquette [Fri, 29 Mar 2019 21:39:36 +0000 (21:39 +0000)]
[GlobalISel][AArch64] Add isel support for G_INSERT_VECTOR_ELT on v2s32s
This adds support for v2s32 vector inserts, and updates the selection +
regbankselect tests for G_INSERT_VECTOR_ELT.
Differential Revision: https://reviews.llvm.org/D59910
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357318
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Amara Emerson [Fri, 29 Mar 2019 21:30:51 +0000 (21:30 +0000)]
[X86] When using Win64 ABI, exit with error if SSE is disabled for varargs
We need XMM registers to handle varargs with the Win64 ABI. Before we would
silently generate bad code resulting in an assertion failure elsewhere in the
backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357317
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Alina Sbirlea [Fri, 29 Mar 2019 21:16:31 +0000 (21:16 +0000)]
[MemorySSA] Don't optimize incomplete phis.
Summary:
MemoryPhis cannot be optimized out until they are complete.
Resolves PR41254.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357315
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Nirav Dave [Fri, 29 Mar 2019 20:26:23 +0000 (20:26 +0000)]
[DAGCombiner] Rewrite ImproveLifetimeNodeChain to avoid DAG loop.
Avoid EXPENSIVE_CHECK failure. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357309
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Heejin Ahn [Fri, 29 Mar 2019 19:36:51 +0000 (19:36 +0000)]
[WebAssembly] Handle END_LOOP in unreachable BB in CFGStackify
Summary:
This fixes crashes when a BB in which an END_LOOP is to be placed is
unreachable and does not have any predecessors. Fixes PR41307.
Reviewers: dschuff
Subscribers: yurydelendik, sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357303
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Matt Arsenault [Fri, 29 Mar 2019 19:14:54 +0000 (19:14 +0000)]
AMDGPU: Remove dx10-clamp from subtarget features
Since this can be set with s_setreg*, it should not be a subtarget
property. Set a default based on the calling convention, and Introduce
a new amdgpu-dx10-clamp attribute to override this if desired.
Also introduce a new amdgpu-ieee attribute to match.
The values need to match to allow inlining. I think it is OK for the
caller's dx10-clamp attribute to override the callee, but there
doesn't appear to be the infrastructure to do this currently without
definining the attribute in the generic Attributes.td.
Eventually the calling convention lowering will need to insert a mode
switch somewhere for these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357302
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Simon Pilgrim [Fri, 29 Mar 2019 19:14:52 +0000 (19:14 +0000)]
[Hexagon] Remove fcmp undef from reduced tests
Pre-commit for D60006 (Add fcmp UNDEF handling to SelectionDAG::FoldSetCC)
Approved by @kparzysz (Krzysztof Parzyszek)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357301
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Craig Topper [Fri, 29 Mar 2019 19:09:37 +0000 (19:09 +0000)]
[X86] Add test cases showing failure to use RMW form of negate when only flags are used. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357300
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Nirav Dave [Fri, 29 Mar 2019 18:50:22 +0000 (18:50 +0000)]
[DAG] Avoid redundancy in StoreMerge TokenFactor generation.
Avoid generating redundant TokenFactor when all merged stores have
the same chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357299
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Craig Topper [Fri, 29 Mar 2019 18:36:40 +0000 (18:36 +0000)]
[X86] Use cached OptForSize in X86ISelDAGToDAG.cpp instead of pulling it from the function attribute. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357297
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Simon Pilgrim [Fri, 29 Mar 2019 18:23:08 +0000 (18:23 +0000)]
[SystemZ] Regenerate double constant comparison test
Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357295
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Simon Pilgrim [Fri, 29 Mar 2019 18:22:18 +0000 (18:22 +0000)]
[MIPS] Regenerate double constant comparison test
Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357294
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Simon Pilgrim [Fri, 29 Mar 2019 18:21:19 +0000 (18:21 +0000)]
[ARM] Regenerate execute-only float comparison tests
Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357293
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Sanjay Patel [Fri, 29 Mar 2019 17:51:39 +0000 (17:51 +0000)]
[InstCombine] autogenerate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357291
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Scott Linder [Fri, 29 Mar 2019 17:49:51 +0000 (17:49 +0000)]
[AMDGPU] Add an additional Code Object V3 assembler example
Document the intended use of the `.amdgcn.next_free_{s,v}gpr` in the
context of multiple kernels and functions.
Differential Revision: https://reviews.llvm.org/D59949
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357289
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Sanjay Patel [Fri, 29 Mar 2019 17:47:51 +0000 (17:47 +0000)]
[InstCombine] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357288
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Simon Pilgrim [Fri, 29 Mar 2019 17:46:06 +0000 (17:46 +0000)]
[AArch64] Regenerate half precision tests
Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357286
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Mircea Trofin [Fri, 29 Mar 2019 17:39:17 +0000 (17:39 +0000)]
[llvm][NFC] Factor out logic for getting incoming & back Loop edges
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357284
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Nirav Dave [Fri, 29 Mar 2019 17:35:56 +0000 (17:35 +0000)]
[DAGCombine] Prune unnused nodes.
Summary:
Nodes that have no uses are eventually pruned when they are selected
from the worklist. Record nodes newly added to the worklist or DAG and
perform pruning after every combine attempt.
Reviewers: efriedma, RKSimon, craig.topper, spatel, jyknight
Reviewed By: jyknight
Subscribers: jdoerfert, jyknight, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357283
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Simon Pilgrim [Fri, 29 Mar 2019 17:35:11 +0000 (17:35 +0000)]
[ARM] Regenerate vector comparison tests
Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357281
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Evandro Menezes [Fri, 29 Mar 2019 17:28:11 +0000 (17:28 +0000)]
[CodeGen] Refactor the option for the maximum jump table size
Refactor the option `max-jump-table-size` to default to the maximum
representable number. Essentially, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357280
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Nirav Dave [Fri, 29 Mar 2019 17:26:40 +0000 (17:26 +0000)]
[DAG] Set up infrastructure to avoid smart constructor-based dangling nodes
Summary:
Various SelectionDAG non-combine operations (e.g. the getNode smart
constructor and legalization) may leave dangling nodes by applying
optimizations without fully pruning unused result values. This results
in nodes that are never added to the worklist and therefore can not be
pruned.
Add a node inserter for the combiner to make sure such nodes have the
chance of being pruned. This allows a number of additional peephole
optimizations.
Reviewers: efriedma, RKSimon, craig.topper, jyknight
Reviewed By: jyknight
Subscribers: msearles, jyknight, sdardis, nemanjai, javed.absar, hiraditya, jrtc27, atanasyan, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357279
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Simon Pilgrim [Fri, 29 Mar 2019 17:20:27 +0000 (17:20 +0000)]
[X86] Fix some tests using fcmp with undef arguments
Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357278
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Sanjay Patel [Fri, 29 Mar 2019 16:49:38 +0000 (16:49 +0000)]
[InstCombine] move shuffle canonicalizations before other transforms
This may not be NFC, but I'm not sure how to expose any diffs in
tests. In theory, it should be slightly more efficient and possibly
more profitable to do the canonicalizations (which can increase the
undef elements in the mask) ahead of SimplifyDemandedVectorElts().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357272
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Jordan Rupprecht [Fri, 29 Mar 2019 16:48:19 +0000 (16:48 +0000)]
[llvm-readobj] Add some generic notes (e.g. NT_VERSION)
Summary: Support reading notes that don't have a standard note name.
Reviewers: MaskRay
Reviewed By: MaskRay
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59969
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357271
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Jordan Rupprecht [Fri, 29 Mar 2019 16:43:13 +0000 (16:43 +0000)]
[llvm-readelf] Allow prefix flags for -p and -x
Summary: This allows syntax like `llvm-readelf -p.data1 -x.data2`.
Reviewers: jhenderson
Reviewed By: jhenderson
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357270
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Simon Pilgrim [Fri, 29 Mar 2019 15:28:25 +0000 (15:28 +0000)]
[SLP] Add support for commutative icmp/fcmp predicates
For the cases where the icmp/fcmp predicate is commutative, use reorderInputsAccordingToOpcode to collect and commute the operands.
This requires a helper to recognise commutativity in both general Instruction and CmpInstr types - the CmpInst::isCommutative doesn't overload the Instruction::isCommutative method for reasons I'm not clear on (maybe because its based on predicate not opcode?!?).
Differential Revision: https://reviews.llvm.org/D59992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357266
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Fangrui Song [Fri, 29 Mar 2019 15:27:58 +0000 (15:27 +0000)]
[llvm-objcopy] Fix case style of LayoutSegments. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357265
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Simon Atanasyan [Fri, 29 Mar 2019 15:15:22 +0000 (15:15 +0000)]
[mips] Fix lowering a signed immediate for *.d MSA instructions
The `lowerMSASplatImm` function zero-extends `i32` immediates while
building constant. If target type is `i64`, negative immediate loses
the sign. As a result, for example `__builtin_msa_ldi_d(-1)` lowered
to series of instruction loads incorrect value 0xffffffff to the `$w0`
register instead of single `ldi.d $w0, -1` instruction.
The fix zero-extends unsigned immediates and signed-extend signed
immediates.
Differential Revision: http://reviews.llvm.org/D59884
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357264
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Roman Lebedev [Fri, 29 Mar 2019 14:58:01 +0000 (14:58 +0000)]
[NFC][llvm-exegesis] Also promote getSchedClassPoint() into ResolvedSchedClass.
Summary:
It doesn't need anything from Analysis::SchedClassCluster class,
and takes ResolvedSchedClass as param, so this seems rather fitting.
Reviewers: courbet, gchatelet
Reviewed By: courbet
Subscribers: tschuett, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59994
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357263
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Dmitry Preobrazhensky [Fri, 29 Mar 2019 14:50:20 +0000 (14:50 +0000)]
[AMDGPU][MC] Corrected conversion rules for inlinable constants to match rules for literals
See bug 40806: https://bugs.llvm.org/show_bug.cgi?id=40806
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D59786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357262
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Nico Weber [Fri, 29 Mar 2019 14:31:28 +0000 (14:31 +0000)]
gn build: Merge r357248
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357261
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Nico Weber [Fri, 29 Mar 2019 14:30:01 +0000 (14:30 +0000)]
gn build: Merge r357259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357260
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Roman Lebedev [Fri, 29 Mar 2019 14:24:27 +0000 (14:24 +0000)]
[NFC][llvm-exegesis] Refactor ResolvedSchedClass & friends
Summary:
`ResolvedSchedClass` will need to be used outside of `Analysis`
(before `InstructionBenchmarkClustering` even), therefore promote
it into a non-private top-level class, and while there also
move all of the functions that are only called by `ResolvedSchedClass`
into that same new file.
Reviewers: courbet, gchatelet
Reviewed By: courbet
Subscribers: mgorny, tschuett, mgrang, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59993
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357259
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Sanjay Patel [Fri, 29 Mar 2019 14:20:38 +0000 (14:20 +0000)]
[DAGCombiner] simplify shuffle of shuffle
After investigating the examples from D59777 targeting an SSE4.1 machine,
it looks like a very different problem due to how we map illegal types (256-bit in these cases).
We're missing a shuffle simplification that maps elements of a vector back to a shuffled operand.
We have a more general version of this transform in DAGCombiner::visitVECTOR_SHUFFLE(), but that
generality means it is limited to patterns with a one-use constraint, and the examples here have
2 uses. We don't need any uses or legality limitations for a simplification (no new value is
created).
It looks like we miss this pattern in IR too.
In one of the zext examples here, we have shuffle masks like this:
Shuf0 = vector_shuffle<0,u,3,7,0,u,3,7>
Shuf = vector_shuffle<4,u,6,7,u,u,u,u>
...so that's moving the high half of the 1st vector into the low half. But the high half of the
1st vector is already identical to the low half.
Differential Revision: https://reviews.llvm.org/D59961
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357258
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